Introduction to CMOS VLSI Design Logical Effort Part B Original Lecture b Ja Brockman Universit of Notre Dame Fall 2008 Modified b Peter Kogge Fall 2010,2011,2015, 2018 Based on lecture slides b David Harris, Harve Mudd College http://www.cmosvlsi.com/coursematerials.html Logical Effort B Slide 1 Review: Motivating Eample Ben Bitdiddle is the memor designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a 1632 register file. [3:0] [3:0] 32 bits 16 Decoder specifications: Register File 16 word register file Each word is 32 bits wide Each file bit presents load of 3 unit-sized transistors Both true & complementar address inputs [3:0] available Each address input ma drive 10 unit-sized transistors Ben needs to decide: How man stages to use in decoder driver output buffers? How large should each gate be? How fast can decoder operate? 4:16 Decoder 16 words Slide 2 1
Review: Ideal Gate Dela Imagine ideal unit inverter (no parasitic diffusion capacitance & unit on resistance) driving identical inverter 2 X 2C 2C 2 R 2C 1 X 1C C 1 R C = 3RC = Ideal Inverter Dela Slide 3 Review: Linear Dela Model dela d = p + f = p + hg Prior dela had two parts p: Parasitic dela due to internal diffusion capacitance of gate 3RC for inverter Independent of load = sum of diffusion caps f: Effort dela due to load capacitance of gates being driven 3h RC when driving h unit inverters Proportional to total load capacitance = h*g if driving identical circuits (copies of itself) h = # of copies of gate (also called Fanout ) g = Logical Effort (function of gate compleit) 3RC for inverter Slide 4 2
Review: Normalized Linear Dela Remember 3RC = parasitic dela of unit inverter 3RC + 3hRC = dela if driving h inverter copies Normalized dela: divide dela b 3RC Measure of how much slower a circuit is than an inverter = 1 + h for inverter driving h identical inverters Slide 5 Determining Logical Effort Logical effort g: ratio of input capacitance of a gate to input capacitance of an inverter delivering the same output current (pullup/down resistance). Measured from dela vs. fanout plots Or estimate b counting transistor widths ND divide b 3 to normalize to unit inverter 2 Y 1 B 2 2 2 2 Y B 4 4 1 1 Y C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Question: does g change if we scale all the transistors wided? Slide 6 3
Summar: (p.156) Number of inputs Gate Tpe 1 2 3 4 N Inverter 3 1 1 NND 4 2 4/3 5 3 5/3 6 4 6/3 N+2 N (N+2)/3 NOR 5 2 5/3 7 3 7/3 9 4 9/3 2N+1 N (2N+1)/3 TriState/mu 2 2 4 2 6 2 8 2 2N 2 XOR, XNOR 4 4,4 6 6,12,6 8 8,16,16,8 (,,z) = Input Cap, p, g ll inputs are not the same! Parasitic: dela driving 0 load (divided b 3RC) Logical effort: Input Cap of gate / Input Cap of inverter of same current Logical Effort CMOS VLSI Design Slide 7 d = f + p = gh + p Lets take our invertor: d = h + 1 p = 1 (-intercept) g = 1 (slope) Dela Plots Normalized Dela: d 6 5 4 3 2 1 0 Electrical Effort: h = C out / C in Inverter g = 1 p = 1 d = h + 1 Effort Dela: f Parasitic Dela: p 0 1 2 3 4 5 What does Normalized Dela mean to designer? Slide 8 4
d = f + p = gh + p 2 input NND Normalized Dela: d 6 5 4 3 2 2-input NND Remember we normalize b unit inverter 3RC Inverter g = p = d = g = 1 p = 1 d = h + 1 1 0 0 1 2 3 4 5 Electrical Effort: h = C out / C in Slide 9 More 2 input NND d = f + p = gh + p Normalized Dela: d 6 5 4 3 2 2-input NND Inverter g = 4/3 p = 2 d = (4/3)h + 2 g = 1 p = 1 d = h + 1 Effort Dela: f 1 0 Parasitic Dela: p 0 1 2 3 4 5 Electrical Effort: h = C out / C in Slide 10 5
3 Input NND Slide 11 Eg: Ring Oscillator (p.158) Estimate the frequenc of an N-stage ring oscillator N odd Each Stage: Logical Effort: g = 1 Electrical Effort: h = 1 Parasitic Dela: p = 1 Stage Dela: d = (1 + h) = (1 + 1) = 2 Total dela: Nd = 2N (normalized) = 2Dτ (in seconds) Overall Frequenc: f osc = 1/(2Nτ) 31 stage ring oscillator 65nm process (3ps dela) = 2.7GHz 0.6 m process ~ 200 MHz Slide 12 6
Eample: FO4 Inverter Estimate the dela of a fanout-of-4 (FO4) inverter d Logical Effort: g = Electrical Effort: h = Parasitic Dela: p = Stage Dela: d = Slide 13 Eample: FO4 Inverter Estimate the dela of a fanout-of-4 (FO4) inverter d Logical Effort: g = 1 Electrical Effort: h = 4 Parasitic Dela: p = 1 Stage Dela: d = 5 The FO4 dela is approimatel 200 ps in 0.6 m process 60 ps in a 180 nm process f/3 ns in an f m process Slide 14 7
Drive (p.159) Most libraries have multiple versions of common gates Named <gate-tpe>_# Versions differ b size of transistors Denoted b # in name Called the gate version s drive Relative to unit inverter Drive = C in / g Thus dela = C out / + p Question: what s speed difference between nand2_1 nand2_3 Slide 15 (p. 160) (180 nm process) _1 dela driving h _1 inverters = 20 + 3.6*h*3. ps XL= Low Power Xi = drive of i = 20 + 12.4h ps Input cap Parasitic dela = (25.3 + 14.6)/2 = 20ps τ = 12.4ps p inv = 20ps = (20/12.4)τ = 1.6 in normalized terms verage (4.53+2.37)/2 = 3.ns/pf Slide 16 8
(p. 160) (180 nm process) Lets look at input Parasitic dela = (31.3+19.5)/2 = 25.4ps C in = 4.2fF K load = (4.53+2.84)/2 ns/pf = 3.69 ns/pf = 3.69 ps/ff t pd = 25.4 +4.2*3.69*h ps = 25.4 + 15.5*h ps Normalizing b inverter 12.4ps p = 25.4/12.4 = 2.05 g = 15.5/12.4 = 1.25 versus 4/3 = 1.33 from model Input Cap Wh the difference? Slide 17 (p. 161) Limitations to Linear Dela Model Input & output slopes: not square Input arrival times: comple interactions when 2 or more inputs change at same time Velocit Saturation: We assume N transistors in series must be N times wider But series transistors see less velocit saturation & hence less resistance Voltage Dependencies: τ ~ V* V DD /(V DD V T ) α Gate/Source Dependencies: We assumed gate caps terminate on a fied rail In realit to middle of channel Bootstrapping: Transistors have gate to drain capacitance Causes input to output lifting Slide 18 9
Bootstrapping Real-world: some cap from gate to drain Slide 19 Dela in Multi-Stage Circuits Slide 20 10
Sample Multi Stage Circuit p=2 g=4/3 h=15/4 Table Lookup Wh? Slide 21 C 90 Number of inputs Gate Tpe 1 2 3 4 N Inverter 3 1 1 NND 4 2 4/3 5 3 5/3 6 4 6/3 N+2 N (N+2)/3 NOR 5 2 5/3 7 3 7/3 9 4 9/3 2N+1 N (2N+1)/3 TriState/mu 2 2 4 2 6 2 8 2 2N 2 XOR, XNOR 4 4,4 6 6,12,6 8 8,16,16,8 (,,z) = Input Cap, p, g B Scaling Transistors What if all transistors in gate G got wider b k? Denote as gate G(k) Parasitic dela of G(k): dela of unloaded gate Diffusion capacitance increases b k Resistance decreases b k Result: No change Effort dela: ratio of load cap to input cap If drive same # of G(k) as before, no change If drive same # of G(1) as before, decrease b 1/k If drive k times as man G(1), no change Result: fanout to tpe G(1) gates increases b k YOU CN DRIVE MORE GTES T SME SPEED! OR DRIVE SME GTES FSTER Slide 22 11
Design Question Given a signal path thru multiple gates Of different tpes nd different #s on each output How do we select transistor scale factors? nswer: analze/select input capacitance nd then adjust transistor scaling to give ou that value Slide 23 MultiStage Logic Networks (p. 163) Relative Input Capacitance (based on gate design & transistor size) FIG 4.29 g i = logical effort to drive a gate of tpe i = input cap/cap of inverter h i = fanout of gates of tpe i = load cap/input cap Slide 24 12
Question If dela thru one gate is p + hg, Can we simplif multistage to something like P+HG? Slide 25 Overall Dela dela thru circuit = dela(i) where dela(i) = dela thru i th stage of logic dela(i) = p i + h i * g i p i function onl of gate tpe at stage i g i function onl of gate tpe at stage i input cap/cap of inverter h i depends on connected gates at stage i+1 total load on output of gate i/input cap of gate i Thus dela = (p i + h i * g i ) = (p i ) + (h i * g i ) Clearl P = (p i ) Can we write (h i * g i ) as some H*G? Slide 26 13
(p. 164) Path Logical Effort Path Electrical Effort Path Effort Definitions G g i C H C out-path in-path F f gh i i i 10 g 1 = 1 h 1 = /10 g 2 = 5/3 h 2 = / g 3 = 4/3 h 3 = z/ z g 4 = 1 h 4 = 20/z 20 Question: Can we write F = GH? Slide 27 Can We State F =GH? Branch point No! Consider paths that branch: Not all load at one stage is on path to output 15 90 Individual terms 5 g 1 = g 2 = 1 (inverters) h 1 = (15 +15) / 5 = 6 15 Output 90 h 2 = 90 / 15 = 6 Path Terms G = Πg i = 11 = 1 Question: What H = C out /C in = 90 / 5 = 18 did GH overlook? Thus GH = 18 Versus F = g 1 h 1 g 2 h 2 = 36 = 2GH!= GH Slide 28 14
Branching Effort Introduce Branching Effort B ccounts for signal branching between stages in path Con path b C B b i C on path off path h i BH Now we compute the Path Effort F = GBH Or dela = P + GBH Slide 29 Individual terms g 1 = g 2 = 1 (inverters) h 1 = (15 +15) / 5 = 6 h 2 = 90 / 15 = 6 b 1 = (15+15)/15 = 2 b 2 = 90/90 =1 Path Terms G = Πg i = 11 = 1 H = C out /C in = 90 / 5 = 18 B = 21 = 2 Thus GBH = 36 Versus F = g 1 h 1 g 2 h 2 = 36! Redo Slide 30 5 Branch point 15 15 90 90 In this case: eact match 15
Designing Fast Multistage Circuits Slide 31 Designing Fast Circuits D d D P i F = f i + p i = P + F = P + GBH D is Path Dela P is Path Parasitic Dela - independent of widths F is Path Effort G = Πg i = Path Logical Effort ind. of width B = Branching Factor H = C outpath /C inpath = Path Electrical Effort To minimize f i when GBH is constant: MKE ECH STGE HVE SME EFFORT f^ For N stage circuit: f^ = (GBH) 1/N Minimum possible dela = P + Nf^!!!! Slide 32 16
How Do We Find Gate Sizes to Reach this Equal Effort? How wide should gates be for least dela? Tpicall C in of first gate is pre-specified Working backward from load, appl transformation to find input capacitance of each gate, given the load it drives. Use this for the load capacitance on previous stage Check work b verifing input cap spec i Then use input cap of each gate to size each gate ˆ Cout f gh g Cin gc i Cin i fˆ out i Slide 33 Eample: 3-stage path Select input capacitance and for least dela from to B, given capacitance on is 8C 8 Input cap speced at 8C: Min size NND gives Cin = 4C Thus scale widths 2X or n-tpe are 2X2 = 4 wide p-tpe are also 22 = 4 wide Slide 34 B 17
8 Compute f^ & Dela Logical Effort G = Electrical Effort H = Branching Effort B = Path Effort F = Best Stage Effort ˆf Parasitic Dela P = Dela D = B Slide 35 8 Compute f^ & Dela B Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = /8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 Best Stage Effort f^ = 125 1/3 = 5 Parasitic Dela P = 2 + 3 + 2 = 7 Dela D = Nf^ + P = 3*5 + 7 = 22 Slide 36 18
Work Backwards Work backward for sizes using C in[i] = C out[i]* g i /f^ = = 8 B Slide 37 Work Backwards Work backward for sizes using C in[i] = C out[i]* g i /f^ = * (5/3) / 5 = 15 8 B Logical Effort C CMOS VLSI Design Slide 38 19
Work Backwards Work backward for sizes using C in[i] = C out[i]* g i /f^ = * (5/3) / 5 = 15 = (15*2) * (5/3) / 5 = 10 15 8 15 B Load = 30 Logical Effort C CMOS VLSI Design Slide 39 Work Backwards Work backward for sizes using C in[i] = C out[i]* g i /f^ = * (5/3) / 5 = 15 = (15*2) * (5/3) / 5 = 10 = (10+10+10)*(4/3)/5 = 8 ND IT CHECKS! 10 10 15 8 Load = 30 10 15 B Logical Effort C CMOS VLSI Design Slide 40 20
Size Last Gate Now size last stage: = 15 2 input NOR has unit input cap of 5 To get an input cap of 15=> widths 15/5 = 3X unit! => p-tpe are 3*4 = 12 wide => n-tpe are 3*1 = 3 wide 8 P: 12 15 N: 3 B Slide 41 Size Middle Gate Now size 2 nd stage 3 input NND = 10; unit input cap of 5 => widths 10/5 = 2X unit! p:n ratio of 2:3 => p-tpe are 2*2 = 4 wide => n-tpe are 3*2 = 6 wide 8 P: 4 10 N: 6 P: 12 N: 3 15 B Slide 42 21
Size First Gate Now size 1st stage Cin = 8; 2 input NND has unit input cap of 4 => widths 8/4 = 2X unit! p:n ratio of 1:1 => p-tpe are 2*2 = 4 wide => n-tpe are 2*2 = 4 wide P: 4 N: 4 8 10 P: 4 N: 6 P: 12 15 N: 3 B Slide 43 Checking Dela Let s check dela d 1 = g 1 h 1 + p 1 = {(10+10+10)/8}*(4/3) + 2 = 7 d 2 = g 2 h 2 + p 2 = {(15+15)/10}*(5/3) + 3 = 8 d 3 = g 3 h 3 + p 3 = {/15}*(5/3) + 2 = 7 dela = 7 + 8 + 7 = 22 in 65nm process τ = 3ps, so circuit is 22*3 = 66ps P: 4 8 N: 4 P: 4 10 N: 6 P: 12 N: 3 15 B Slide 44 22
What If We Tr to Tweak? What if we made stage 2 even bigger (to be faster) d 2 = g 2 h 2 + p 2 = {(15+15)/15}*(5/3) + 3 = 6.3 (faster) but d 1 = g 1 h 1 + p 1 = {(15+15+15)/8}*(4/3) + 2 = 9.5 (slower) and d 3 = g 3 h 3 + p 3 = {/15}*(5/3) + 2 = 7 (no change) dela = 9.5 + 6.3 + 7 = 22.8 > 22 SLOWER CIRCUIT P: 4 8 N: 4 P: 6 15 N: 9 P: 12 15 N: 3 B Slide Choosing Best # of Stages Man logic functions have multiple possible circuits (topologies) Goal: select topolog, est. dela, & size transistors We know in general NNDs better than NORs Gates with fewer inputs better than more inputs Tpical shortcut: estimate dela b # of stages ssuming constant gate dela and thus shorter paths are faster THIS IS NOT LWYS TRUE! Eg: dding inverters at end with increasing sizes can speed up circuit, esp. when high load Slide 46 23
Eample (p. 166) How man stages should a path use? Minimizing number of stages is not alwas fastest Eample: drive 64-bit datapath with unit inverter Each bit eqvt to unit inverter in load Initial Driver 1 1 1 1 Datapath Load N: f: D: 64 64 64 64 1 2 3 4 Slide 47 Best Number of Stages How man stages should a path use? Minimizing number of stages is not alwas fastest Eample: drive 64-bit datapath with unit inverter Initial Driver 1 1 1 1 H = 64 G = 1 F = HG = 64 D = NF 1/N + P = N(64) 1/N + N Datapath Load N: f: D: 1 64 65 8 4 2.8 16 8 23 64 64 64 64 2 8 18 3 4 15 Fastest 4 2.8 15.3 Slide 48 24
General Derivation Consider adding inverters to end of n 1 stage path How man give least dela? 1 N n 1 D NF p N n p i1 i p 1ln 0 inv 1 inv D 1 1 1 N N N F ln F F pinv 0 N 1 Define best stage effort F N Logic Block: n 1 Stages Path Effort F N - n 1 Etra Inverters N total stages with (N-n 1 ) Inverters do not change logical effort do add parasitic dela Slide 49 Best Stage Effort p 1ln 0 inv has no closed-form solution Neglecting parasitics (p inv = 0), we find = 2.718 (e) For p inv = 1, solve numericall for = 3.59 gain, these ρ values are best logical effort per stage ^ when ou have N = log ρ F stages Slide 50 25
Sensitivit nalsis How sensitive is dela to using eactl the best 1.6 number of stages? 1.51 D(N) /D(N) 1.4 1.2 1.15 1.0 1.26 (=6) ( =2.4) 0.5 0.7 1.0 1.4 2.0 2.4 < < 6 gives dela within 15% of optimal We can be slopp! Book likes = 4 0.0 N / N = actual N vs optimal N Slide 51 1 st Eample, Revisited Ben Bitdiddle is the memor designer for the Motoroil 68W86, an embedded automotive processor. Help Ben design the decoder for a register file. [3:0] [3:0] 32 bits 16 Decoder specifications: 16 word register file Each word is 32 bits wide Each bit presents load of 3 unit-sized transistors True and complementar address inputs [3:0] Each input ma drive 10 unit-sized transistors Ben needs to decide: How man stages to use? How large should each gate be? How fast can decoder operate? 4:16 Decoder Register File 16 words Slide 52 26
What Does This Mean? 16 word register file There are 16 separate row lines Branching factor of 16 at end Each word is 32 bits wide & each bit presents load of 3 unit-sized transistors The load on each row line is 32*3 = 96 True and complementar address inputs [3:0] n address input needed for onl 8 row lines Each input ma drive 10 unit-sized transistors Total input capacitance from 1 st stage gates on inputs = 10 Slide 53 Number of Stages Decoder effort is mainl electrical and branching Electrical Effort: H = (32*3) / 10 = 9.6 Branching Effort: B = 8 If we neglect logical effort (assume G = 1) Path Effort: F = GBH = 76.8 Number of Stages: N = log 4 F = 3.1 Tr a 3-stage design Slide 54 27
3 Stage Gate Sizes & Dela Logical Effort: G = 1 * 6/3 * 1 = 2 Path Effort: F = GBH = 2*8*9.6 =154 1/3 Stage Effort: f ˆ F 5.36 Path Dela: D3 fˆ 14 1 22.1 Gate sizes: z = 96*1/5.36 = 18 = 18*2/5.36 = 6.7 [3] [3] [2] [2] [1] [1] [0] [0] 10 10 10 10 10 10 10 10 Inverter=>NND=>Inverter z word[0] 96 units of wordline capacitance z word[15] Slide 55 Comparison Compare man alternatives with a spreadsheet Fastest Design N G P D NND4-INV 2 2 5 29.8 NND2-NOR2 2 20/9 4 30.1 INV-NND4-INV 3 2 6 22.1 NND4-INV-INV-INV 4 2 7 21.1 NND2-NOR2-INV-INV 4 20/9 6 20.5 NND2-INV-NND2-INV 4 16/9 6 19.7 INV-NND2-INV-NND2-INV 5 16/9 7 20.4 NND2-INV-NND2-INV-INV-INV 6 16/9 8 21.6 Slide 56 28
Review of Definitions Term Stage Path number of stages 1 N logical effort g G g i C C out out-path electrical effort h H Cin Cin-path Con-path Coff-path branching effort b C B b on-path i effort f gh F GBH effort dela f DF fi parasitic dela p P p i dela d f p D di DF P Slide 57 Method of Logical Effort 1) Compute path effort 2) Estimate best number of stages 3) Sketch path with N stages 4) Estimate least dela 5) Determine best stage effort 6) Find gate sizes F GBH N log 4 F 1 N D NF P fˆ F C ini 1 N gc i fˆ outi Slide 58 29
Limits of Logical Effort Chicken and egg problem Need path to compute G But don t know number of stages without G Simplistic dela model Neglects input rise time effects Interconnect Iteration required in designs with wire Maimum speed onl Not minimum area/power for constrained dela Slide 59 Summar Logical effort is useful for thinking of dela in circuits Numeric logical effort characterizes gates NNDs are faster than NORs in CMOS Paths are fastest when effort delas are ~4 Path dela is weakl sensitive to stages, sizes But using fewer stages doesn t mean faster paths Dela of path is about log 4 F FO4 inverter delas Inverters and NND2 best for driving large caps Provides language for discussing fast circuits But requires practice to master Slide 60 30