Overview. Introduction 2. Testability measuring 3. Design for testability 4. Built in Self-Test
Built-In Self-Test Outline Motivation for BIST Testing SoC with BIST Test per Scan and Test per Clock HW and SW based BIST Hybrid BIST Pseudorandom test generation with LFSR Ehaustive and pseudoehaustive test generation Response compaction methods Signature analyzers
Testing Challenges: SoC Test Cores have to be tested on chip Source: Elcoteq Source: Intel
Built-In Self-Test System-on-Chip 4 9. S c U D L e g Da c o r e c I C U D L C o p c o r E D n o m Advances in microelectronics technology have introduced a new paradigm in IC design: System-on-Chip (SoC) Many systems are nowadays designed by embedding predesigned and preverified comple functional blocks (cores) into one single die Such a design style allows designers to reuse previous designs and will lead to shorter time-to-market and reduced cost SoC structure breakdown: 0% UDL 75% memory 50% in-house cores 60-70% soft cores
Self-Test in Comple Digital Systems Source SoC Test Access Mechanism SRAM CPU MPEG Peripheral Component Interconnect Wrapper Core Under Test UDL SRAM ROM DRAM Test Access Mechanism Sink Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution need for eternal ATE Combined solution mostly on-chip, ATE needed for control On-chip solution BIST
Self-Test in Comple Digital Systems SoC SRAM CPUSource MPEG Peripheral Component Interconnect Wrapper Core Under Test UDL Sink SRAM ROM DRAM Test architecture components: Test pattern source & sink Test Access Mechanism Core test wrapper Solutions: Off-chip solution need for eternal ATE Combined solution mostly on-chip, ATE needed for control On-chip solution BIST
What is BIST On circuit Test pattern generation Response verification Random pattern generation, very long tests Response compression IC BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA)
SoC BIST Optimization: Embedded Tester Test Controller Core BIST Test access mechanism - testing time Core 2 - memory cost - power consumption BIST - hardware cost - test quality Tester Memory BIST BIST BIST Core 3 Core 4 Core 5 System on Chip
Built-In Self-Test Motivations for BIST: Need for a cost-efficient testing (general motivation) Doubts about the stuck-at fault model Increasing difficulties with TPG (Test Pattern Generation) Growing volume of test pattern data Cost of ATE (Automatic Test Equipment) Test application time Gap between tester and UUT (Unit Under Test) speeds Drawbacks of BIST: Additional pins and silicon area needed Decreased reliability due to increased silicon area Performance impact due to additional circuitry Additional design time and cost
Costly Test Problems Alleviated by BIST Increasing chip logic-to-pin ratio harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing size of test vectors stored in ATE Epensive ATE needed for GHz clocking chips Hard testability insertion designers unfamiliar with gatelevel logic, since they design at behavioral level In-circuit testing no longer technically feasible Shortage of test engineers Circuit testing cannot be easily partitioned
BIST in Maintenance and Repair Useful for field test and diagnosis (less epensive than a local automatic test equipment) Disadvantages of software tests for field test and diagnosis (nonbist): Low hardware fault coverage Low diagnostic resolution Slow to operate Hardware BIST benefits: Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis
Benefits and Costs of BIST with DFT Level Design and test Fabrication Manuf. Test Maintenance test Diagnosis and repair Service interruption Chips + / - + - Boards + / - + - - System + / - + - - - - + Cost increase - Cost saving +/- Cost increase may balance cost reduction
Economics BIST Costs Chip area overhead for: Test controller Hardware pattern generator Hardware response compacter Testing of BIST hardware Pin overhead -- At least pin needed to activate BIST operation Performance overhead etra path delays due to BIST Yield loss due to increased chip area or more chips In system because of BIST Reliability reduction due to increased area Increased BIST hardware compleity happens when BIST hardware is made testable
Faults tested: BIST Benefits Single stuck-at faults Delay faults Single stuck-at faults in BIST hardware BIST benefits Reduced testing and maintenance cost Lower test generation cost Reduced storage / maintenance of test patterns Simpler and less epensive ATE Can test many units in parallel Shorter test application times Can test at functional system speed
BIST Techniques BIST techniques are classified: on-line BIST - includes concurrent and nonconcurrent techniques off-line BIST - includes functional and structural approaches On-line BIST - testing occurs during normal functional operation Concurrent on-line BIST - testing occurs simultaneously with normal operation mode, usually coding techniques or duplication and comparison are used Nonconcurrent on-line BIST - testing is carried out while a system is in an idle state, often by eecuting diagnostic software or firmware routines Off-line BIST - system is not in its normal working mode, usually on-chip test generators and output response analyzers or microdiagnostic routines Functional off-line BIST is based on a functional description of the Component Under Test (CUT) and uses functional high-level fault models Structural off-line BIST is based on the structure of the CUT and uses structural fault models (e.g. SAF)
General Architecture of BIST BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA) BIST components: Test pattern generator (TPG) Test response analyzer (TRA) TPG & TRA are usually implemented as linear feedback shift registers (LFSR) Two widespread schemes: test-per-scan test-per-clock
Detailed BIST Architecture Source: VLSI Test: Bushnell-Agrawal
Built-In Self-Test Test pattern generator BIST Control Test response analysator Test per Scan: Scan Path Scan Path... Scan Path CUT Initial test set: T: 00 T2: 00 T3: 00 T4: 00 Assumes eisting scan architecture Drawback: Long test application time Test application: 00 T 00 T 00T 00 T Number of clocks = 4 4 + 4 = 20
Scan-Path Design IN Combinational circuit OUT The compleity of testing is a function of the number of feedback loops and their length Scan-IN q R q The longer a feedback loop, the more clock cycles are needed to initialize and sensitize patterns Scan-register is a aregister with both shift and parallel-load capability Scan-OUT T = 0 - normal working mode T = - scan mode q Scan-IN T & & D C T q Scan-OUT Normal mode : flip-flops are connected to the combinational circuit Test mode: flip-flops are disconnected from the combinational circuit and connected to each other to form a shift register
Built-In Self-Test Test per Clock: Combinational Circuit Under Test Initial test set: T: 00 T2: 00 T3: 00 T4: 00 Test application: Scan-Path Register 0 0 0 0 0 0 00 T T 4 T 3 T 2 Number of clocks = 0
BILBO BIST Architecture Working modes: B B2 0 0 Reset 0 Flip-flop (normal) 0 Scan mode Test mode Testing modes: CC: LFSR - TPG LFSR 2 - SA CC2: LFSR 2 - TPG LFSR - SA B B2 B B2 LFSR CC LFSR 2 CC2
BILBO BIST Architecture: Eample Testing epoch I: LFSR generates tests for CUT and CUT2 BILBO2 (LFSR3) compacts CUT (CUT2) Testing epoch II: BILBO2 generates test patterns for CUT3 LFSR3 compacts CUT3 response Source: VLSI Test: Bushnell-Agrawal
Pattern Generation Store in ROM too epensive Ehaustive Pseudo-ehaustive Pseudo-random (LFSR) Preferred method Binary counters use more hardware than LFSR Modified counters Test pattern augmentation LFSR combined with a few patterns in ROM Hardware diffracter generates pattern cluster in neighborhood of pattern stored in ROM
Pattern Generation Pseudorandom Test generation by LFSR: ho h hn Xo X...... LFSR CUT Xn Using special LFSR registers Several proposals: BILBO CSTP Main characteristics of LFSR: polynomial initial state test length LFSR
Some Definitions LFSR Linear feedback shift register, hardware that generates pseudo-random pattern sequence BILBO Built-in logic block observer, etra hardware added to flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops Ehaustive testing Apply all possible 2 n patterns to a circuit with n inputs Pseudo-ehaustive testing Break circuit into small, overlapping blocks and test each ehaustively Pseudo-random testing Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns
More Definitions Irreducible polynomial Boolean polynomial that cannot be factored Primitive polynomial Boolean polynomial p() that can be used to compute increasing powers n of n modulo p() to obtain all possible non-zero polynomials of degree less than p() Signature Any statistical circuit property distinguishing between bad and good circuits TPG Hardware test pattern generator PRPG Hardware Pseudo-Random Pattern Generator MISR Multiple Input Response Analyzer
Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Standard LFSR 2 3 4 Modular LFSR 2 3 4 Polynomial: P() = 4 + 3 +
Theory of LFSR c c 2 c 3 y y 2 y 3 y 4 c 4 2 3 4 y 0 y j y j ( t) = y ( t ) ( t) = y0( t j) y = ( t) j ( t) y0 j where j represents the time translation units j for j j 0 j = y0( t) = c j y j ( t) j= n j = n 0( t) = c j y0 j= y ( t) j
Theory of LFSR c c 2 c 3 y y 2 y 3 y 4 c 4 2 3 4 y 0 j = n 0( t) = c j y0 j= y ( t) j n = y t y t 0 ( ) = 0( ) = j c j j j j = n j= j y0 ( t)( c j + ) = Polynomial: y0 ( t) Pn ( ) = 0 0
Theory of LFSR c c 2 c 3 y y 2 y 3 y 4 c 4 2 3 4 y 0 Characteristic polynomial: y0 ( t) Pn ( ) = 0 For y where 0 ( t) 0 P n P n ( ) = ( ) = j n + = j= 0 c j j
Pseudorandom Test Generation LFSR Linear Feedback Shift Register: 2 3 4 Polynomial: P() = 4 + 3 +
Matri Equation for Standard LFSR X n (t + ) X n- (t + ). X 3 (t + ) X 2 (t + ) X (t + ) = 0 0... 0 0 0... 0 0 h n- 0... 0 0 h n-2 0 0... 0 h 2 0 0... 0 h X n (t) X n- (t). X 3 (t) X 2 (t) X (t) X (t + ) = T s X (t) (T s is companion matri) 2 3 4
Pseudorandom Test Generation 2 3 4 Polynomial: P() = 4 + 3 + X 4 (t + ) X 3 (t + ) X 2 (t + ) X (t + ) = 0 0 0 0 0 h 3 0 0 h 2 0 0 h 0 0 X 4 (t) X 3 (t) X 2 (t) X (t) t 2 3 4 t 2 3 4 0 0 0 9 0 0 2 0 0 0 0 0 0 3 0 0 0 0 4 0 0 0 2 0 5 0 0 3 6 0 0 4 0 7 0 0 5 0 0 8 0 6 0 0 0
Theory of LFSR: Primitive Polynomials Properties of Polynomials: Irreducible polynomial cannot be factored, is divisible only by itself Irreducible polynomial of degree n is characterized by: An odd number of terms including term Divisibility into + k, where k = 2 n Any polynomial with all even eponents can be factored and hence is reducible An irreducible polynomial is primitive if it divides the polynomial + k for k = 2 n, but not for any smaller positive integer k
Theory of LFSR: Eamples Polynomials of degree n=3 (eamples): k = 2 n = 2 3 =7 Primitive polynomials: 3 3 + 2 + + + The polynomials will divide evenly the polynomial 7 +, but not any one of k<7, hence, they are primitive They are also reciprocal: coefficients are 0 and 0 Reducible polynomials (non-primitive): 3 3 + = + 2 ( + )( + + = 2 + + ) ( + )( 2 + ) The polynomials don t divide evenly the polynomial 7 +
Theory of LFSR: Eamples Comparison of test sequences generated: Primitive polynomials Non-primitive polynomials 3 3 2 3 3 2 + + + + + + + + 00 0 0 0 00 00 00 00 00 0 0 0 00 00 00 00 00 00 00 00 00 00 00 0 0 00 00 0 0 00
Theory of LFSR: Eamples Reducible polynomial (non-primitive): 3 2 + = ( + )( + 00 00 00 00 0 0 0 0 + ) 3 2 + + + + 2 Primitive polynomial Multiplication of two primitive polynomials: Is 4 + 2 + 2 2 2 3 4 4 + + + + + + a primitive polynomial? + + + 2 + 3 + 2 + 2
Theory of LFSR: Eamples Is 4 + 2 + a primitive polynimial? Irreducible polynomial of degree n is characterized by: 4 - An odd number of terms including term? Yes, it includes 3 terms -Divisibility into + k, where k = 2 n No, there is remainder + 2 + is non-primitive? 3 + 4 Divisibility check: + 2 + 9 5 + + + 5 5 3 3 9 9 7 7 3 + + + + + + + + + 7 5 5 3 + + + + + + 5 3 9 3
Theory of LFSR: Eamples Non-primitive polynomial 4 + 2 + Primitive polynomial 4 + + 2 3 4 2 3 4 000 000 000 00 00 000 000 00 00 0 0 00 00 00 0 0 00 000 000 00 0 0 0 00 00 0 00 00 00 000 000 000
Theory of LFSR: Eamples Primitive polynomial 4 + + 2 3 4 Zero generation: 2 3 4 000 000 00 0 0 0 00 00 0 00 00 00 000 000 000 0000 000 00 0 0 0 00 00 0 00 00 00 000 000 000 0000
Theory of LFSR: Reciprocal Polynomials The reciprocal polynomial of P(X) is defined by: (X) =X N P N (/X) = X N { + C j X -J } (X) = X N + C j X N-J for i N Thus every coefficient C i in P(X) is replaced by C N-I. Eample: The reciprocal of polynomial P 3 (X) = + X + X 3 is P 3 (X) = + X 2 + X 3 The reciprocal of a primitive polynomial is also primitive
Theory of LFSR: Primitive Polynomials Number of primitive polynomials of degree N N No 2 4 2 8 6 6 2048 32 6708864 Table of primitive polynomials up to degree 3 N Primitive Polynomials,2,3,4,6,7,5,22 + X + X n 5,, 2, 29 + X 2 + X n 0,7,20,25,28,3 + X 3 + X n 9 + X 4 + X n 23 + X 5 + X n 8 + X 7 + X n 8 + X 2 + X 3 + X 4 + X n 2 + X + X 3 + X 4 + X n 3 + X + X 4 + X 6 + X n 4, 6 + X + X 3 + X 4 + X n
Theory of LFSR: Primitive Polynomials Eamples of PP (eponents of terms): Number of PP of degree n n No 2 4 2 8 6 6 2048 32 6708864 n other n other 0 9 4 0 2 0 0 3 0 3 0 2 0 4 0 2 7 4 3 0 5 2 0 3 4 3 0 6 0 4 2 0 7 0 5 0 8 6 5 0 6 5 3 2 0
Deterministic Synthesis of LFSR Generation of the polynomial and seed for the given test sequence Creation of the shortest bit-stream: Epected shortest LFSR sequence: Given test sequence: () 000 (2) 00 (3) 00 (4) 0 000 0 0 Seed 0 (4) 0 00 00 (3) 000 (2) 000 000 ()
Deterministic Synthesis of LFSR Generation of the polynomial and seed for the given test sequence Epected shortest LFSR sequence: 0 (4) 0 0 0 00 (3) 0 00 (2) 0 00 000 () System of linear equations: 0 0 00 00 000 000 2 3 4 5 : 2 3 4 5 2 3 4 5 = 0 0 0 We are looking for values of i
Deterministic Synthesis of LFSR Generation of the polynomial and seed for the given test sequence 2 3 4 5 6 System of linear equations: 0 0 00 00 000 000 2 3 4 5 = 0 0 0 Polynomial: 5 + + Seed: 0,2,4,6 4,6,3 2,4,2,3,4,6 Solving the equation by Gaussian elimination: 0000 0000 0000 0000 0000 0000 2 3 4 5 = 0 0 0 2 3 4 5 5 Solution: 2 3 4 5 0 0 0
Deterministic Synthesis of LFSR Embedding deterministic test patterns into LFSR sequence: Polynomial: 5 + + Seed: 0 2 3 4 5 Given deterministic test sequence: () 000 (2) 00 (3) 00 (4) 0 5 LFSR sequence: () 0 (4) (2) 0 (3) 00 (4) 00 (3) (5) 000 (2) (6) 000 (7) 000 ()
BIST: Test Generation Pseudorandom Test generation by LFSR: breakpoint Fault Coverage Problems: Very long test application time Low fault coverage Area overhead Additional delay Fault Coverage Possible solutions Weighted pattern PRPG Combining pseudorandom test with deterministic test Multiple seed Hybrid BIST Time Time
BIST: Fault Coverage Fault coverage is rapidly growing: 00% 2 0% 93,75% 4. pat. 87,5% n Combinational circuit under test Faulty functions covered by. pattern 3. pattern Faulty functions covered by 2. pattern 75% Number of patterns Truth table: Patterns 00 000 00 00 00 00 Functions 0 0 0 0 00 00 0 00 00 2 n - 2 tested 50%! 50% 2 n Number of functions 00 00 00 2 n 2
BIST: Fault Coverage Pseudorandom Test generation by LFSR: Motivation of using LFSR: Fault Coverage - low generation cost - high initial efeciency Reasons of the high initial efficiency: A circuit may implement n 2 2 functions A test vector partitions the functions into 2 equal sized equivalence classes (correct circuit in one of them) The second vector partitions into 4 classes etc. After m patterns the fraction of functions distinguished from the correct function is 2 m n 2 i= 2 2 n i, n m 2 Time
BIST: Different Techniques Pseudorandom Test generation by LFSR: Full identification is achieved only after 2 n input combinations have been tried out (ehaustive test) 2 m n 2 n 2 i= n m 2 2 A better fault model (stuck-at-0/) may limit the number of partitions necessary, Pseudorandom testing of sequential circuits: The following rules suggested: clock-signals should not be random control signals such as reset, should be activated with low probability data signals may be chosen randomly Microprocessor testing A test generator picks randomly an instruction and generates random data patterns By repeating this sequence a specified number of times it will produce a test program which will test the microprocessor by randomly ecercising its logic
BIST: Structural Approach to Test Testing of structural faults: 2 n Combinational circuit under test Not tested faults 3. patttern 4. pat. 2. pattern Faults covered by. pattern 00% Fault coverage Number of patterns 4
BIST: Two Approaches to Test Testing of functions: 00% 0% 93,75% 4. pat. 87,5% Testing of faults: Not tested faults 3. patttern 4. pat. 2. pattern 00% will be reached only after 2 n test patterns Faulty functions covered by. pattern 50% 3. pattern Faulty functions covered by 2. pattern 75% Testing of faults 00% Testing of functions Faults covered by. pattern 00% will be reached when all faults from the fault list are covered
BIST: Other test generation methods Universal test sets. Ehaustive test (trivial test) 2. Pseudo-ehaustive test Properties of ehaustive tests. Advantages (concerning the stuck at fault model): - test pattern generation is not needed - fault simulation is not needed - no need for a fault model - redundancy problem is eliminated - single and multiple stuck-at fault coverage is 00% - easily generated on-line by hardware 2. Shortcomings: - long test length (2 n patterns are needed, n - is the number of inputs) - CMOS stuck-open fault problem
BIST: Other test generation methods Pseudo-ehaustive test sets: Output function verification maimal parallel testability partial parallel testability Segment function verification Segment function verification Primitive polynomials Output function verification 4 4 4 4 00 00 F & 2 6 = 65536 >> 46 = 64 > 6 Ehaustive test Pseudoehaustive sequential Pseudoehaustive parallel
Testing ripple-carry adder Output function verification (maimum parallelity) Ehaustive test generation for n-bit adder: Good news: Bit number n - arbitrary Test length - always 8 (!) Bad news: The method is correct only for ripple-carry adder c 0 a 0 b 0 c a b c 2 a 2 b 2 c 3 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 4 0 0 0 0 5 0 0 0 0 0 0 6 0 0 0 7 0 0 0 8 0-bit testing -bit testing 2-bit testing 3-bit testing etc
Testing carry-lookahead adder General epressions: i i i b a G = i i i i i b a b a P = = n n n n C P G C 2 2 ) ( = = n n n n n n n n n n n n C P P P G G C P G P G C n-bit carry-lookahead adder: 0 2 3 2 3 2 3 3 3 C P P P P P G P G G C = ),, ( 0 0 0 0 C b a f a b C b C a a b PC G C = = = 0 2 2 2 2 3 3 3 3 0 2 3 ) )( )( ( C a b b a b a b a b a b a P PC P =
Testing carry-lookahead adder P 3 P2 PC 0 = a3b3 a3b3 )( a2b2 a2b2 )( ab ab ) ( C 0 R Testing 0 Testing 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 For 3-bit carry lookahead adder for testing only this part of the circuit at least 9 test patterns are needed Increase in the speed implies worse testability
BIST: Other test generation methods Output function verification (partial parallelity) F F 3 F 2 F 4 F 5 00- - 00-0 000 000 00-- 000 2 3 4 F (, 2 ) F 2 (, 3 ) F 3 ( 2, 3 ) F 4 ( 2, 4 ) F 5 (, 4 ) F 6 ( 3, 4 ) Ehaustive testing - 6 Pseudo-ehaustive, full parallel - 4 Pseudo-ehaustive, partially parallel - 6
Problems with Pseudorandom Test The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: low fault coverage LFSR Decoder & Fault Coverage Counter Reset Time If Reset = signal has probability 0,5 then counter will not work and for AND gate may never be produced
Sequential BIST A DFT technique of BIST for sequential circuits is proposed The approach proposed is based on all-branches coverage metrics which is known to be more powerful than all-statement coverage S 0 S 0 S 0 A = S S 5 A = S S 5 A = S S 5 A = 0 S 2 B = 0 B = A = 0 S 2 B = 0 B = A = 0 S 2 B = 0 B = S 3 S 4 S 3 S 4 S 3 S 4
Sequential BIST reset clock test/normal mode (TM) primary inputs masked status bits Digital System primary outputs FSM control signals Datapath observation points status signals MUX Status signals entering the control part are made controllable In the test mode we can force the UUT to traverse all the branches in the FSM state transition graph The proposed idea of architecture requires small device area overhead since a simple controller can be implemented to manipulate the control signals
BIST: Weighted pseudorandom test Hardware implementation of weight generator LFSR & & & /6 /8 /4 /2 Weight select MUX Desired weighted value Scan-IN
BIST: Weighted pseudorandom test Problem: random-pattern-resistant faults Solution: weighted pseudorandom testing The probabilities of pseudorandom signals are weighted, the weights are determined by circuit analysis Faults to be tested NCV NCV non-controlling value The more faults that must be tested through a gate input, the more the other inputs should be weighted to NCV & Propagated faults NDI G NDI I NDI - number of circuit inputs for each gate to be the number of PIs or SRLs in the backtrace cone PI - primary inputs SRL - scan register latch NDI - relative measure of the number of faults to be detected through the gate I & G
BIST: Weighted pseudorandom test Faults to be tested NCV & Propagated faults R I = NDI G / NDI I R I - the desired ratio of the NCV to the controlling value for each gate input NCV - noncontrolling value The more faults that must be tested through a gate input, the more the other inputs should be weighted to NCV NDI G NDI I I & G
BIST: Weighted pseudorandom test Eample: PI PI PI PI PI PI 2 3 & G R = NDI G / NDI I = 6/ = 6 R 2 = NDI G / NDI I = 6/2 = 3 R 3 = NDI G / NDI I = 6/3 = 2 More faults must be detected through the third input than through others This results in the other inputs being weighted more heavily towards NCV
BIST: Weighted pseudorandom test Calculation of signal weights: R 2 = 3 W0 2 = W 2 = 3 PI PI PI PI PI PI 2 3 R 3 = 2 W0 3 = W 3 = 2 & R = 6 W0 = W = 6 G W0 G = W G = W0, W - weights of the signals WV - the value to which the input is biased WV = 0, if W0 > W else WV = Calculation of W0, W Function WO I W I AND WO G R I W G NAND W G R I WO G OR R I WO G W G NOR R I W G WO G
BIST: Weighted pseudorandom test Calculation of signal weights: R = W0 = 6 W = R = 2 W0 = 2 W = 3 R = 3 W0 = 3 W = 2 PI PI 2 PI 3 PI 4 PI 5 PI 6 2 3 & W0 = W = 6 G W0 2 = W 2 = 3 Backtracing from all the outputs to all the inputs of the given cone Weights are calculated for all gates and PIs Function WO I W I OR R I WO G W G NOR R I W G WO G W0 3 = W 3 = 2
BIST: Weighted pseudorandom test Calculation of signal probabilities: R = W0 = 6 W = R = 2 W0 = 2 W = 3 R = 3 W0 = 3 W = 2 PI PI 2 PI 3 PI 4 PI 5 PI 6 2 3 & G WF - weighting factor indicating the amount of biasing toward weighted value WF = ma {W0,W} / min {W,W0} Probability: P = WF / (WF + ) For PI : W0 = 6 W = P = /7 = 0.5 For PI 2 and PI 3 : W0 = 2 W = 3 P = 3/5 = 0.6 For PI 4 - PI 6 : W0 = 3 W = 2 P = 2/5 = 0.4
BIST: Weighted pseudorandom test Calculation of signal probabilities: PI PI PI PI PI PI 2 3 & For PI : P = 0.5 For PI 2 and PI 3 : P = 0.6 For PI 4 - PI 6 : P = 0.4 G Probability of detecting the fault at the input 3 of the gate G: ) equal probabilities (p = 0.5): P = 0.5 (0.25 + 0.25 + 0.25) 0.5 3 = = 0.5 0.75 0.25 = = 0.046 2) weighted probabilities: P = 0.85 (0.6 0.4 + 0.4 0.6 + 0.6 2 ) 0.6 3 = = 0.85 0.84 0.22 = = 0.6
BIST: Response Compression. Parity checking P( R) = ( m i= r i ) mod 2 2. One counting P( R) = m i= r i 3. Zero counting P( R) = m i= r i Test UUT r i P i- Test r i UUT Counter T
BIST: Response Compression 4. Transition counting r i a) Transition 0 P( R) = m i= 2 ( r i r i ) Test UUT T & r i- b) Transition 0 r i P( R) = m i= 2 ( r i r i ) Test UUT T & r i- 5. Signature analysis
Pseudorandom Test Generation LFSR Linear Feedback Shift Register: Standard LFSR 2 3 4 Modular LFSR 2 3 4 Polynomial: P() = 4 + 3 +
BIST: Signature Analysis Signature analyzer: Standard LFSR UUT 2 3 4 Modular LFSR Response string 4 2 Response in compacted by LFSR The content of LFSR after test is called signature 3 Polynomial: P() = + 3 + 4
Theory of LFSR The principles of CRC (Cyclic Redundancy Coding) are used in LFSR based test response compaction Coding theory treats binary strings as polynomials: Eample: R = r m- r m-2 r r 0 - m-bit binary sequence R() = r m- m- + r m-2 m-2 + + r + r 0 - polynomial in 00 R() = 4 + 3 + Only the coefficients are of interest, not the actual value of However, for = 2, R() is the decimal value of the bit string
BIST: Signature Analysis Arithmetic of coefficients: - linear algebra over the field of 0 and : all integers mapped into either 0 or - mapping: representation of any integer n by the remainder resulting from the division of n by 2: n = 2m + r, r { 0, } or r n (modulo 2) Linear - refers to the arithmetic unit (modulo-2 adder), used in CRC generator (linear, since each bit has equal weight upon the output) Eamples: 4 + 3 + + + 4 + 2 + 3 + 2 + 4 + 3 + + + 5 + 4 + 2 + 4 + 3 + + 5 + 3 + 2 +
Theory of LFSR Characteristic Polynomials: = = + + + + + = 0 2 2 0...... ) ( m m m m m c c c c c G Multiplication of polynomials 3 4 2 3 4 2 2 2 + + + + + + + + + +
Theory of LFSR Characteristic Polynomials: = = + + + + + = 0 2 2 0...... ) ( m m m m m c c c c c G Division of polynomials 2 2 3 2 3 2 4 3 4 2 2 + + + + + + + + + + + + Quotient Remainder Dividend Divider
BIST: Signature Analysis Division of one polynomial P() by another G() produces a quotient polynomial Q(), and if the division is not eact, a remainder polynomial R() ) ( ) ( ) ( ) ( ) ( G R Q G P + = Eample: ) ( ) ( 3 5 2 2 3 3 5 3 7 + + + + + + + = + + + + + = G P Remainder R() is used as a check word in data transmission The transmitted code consists of the unaltered message P() followed by the check word R() Upon receipt, the reverse process occurs: the message P() is divided by known G(), and a mismatch between R() and the remainder from the division indicates an error
BIST: Signature Analysis In signature testing we mean the use of CRC encoding as the data compressor G() and the use of the remainder R() as the signature of the test response string P() from the UUT Signature is the CRC code word P( ) G( ) = Q( ) + R( ) G( ) Eample: G() 0 = Q() = 2 + 0 0 0 0 0 0 0 P( ) G( ) = 7 3 + + 5 3 + + + 0 0 0 0 0 0 0 0 0 P() Signature 0 0 0 = R() = 3 + 2 +
BIST: Signature Analysis G() IN: 0 0000 P() P( ) G( ) = 0 2 3 4 G() 7 3 + + 5 3 + + + Shifted into LFSR Compressor 0 0 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 The division process can be mechanized using LFSR The divisor polynomial G() is defined by the feedback connections Shift creates 5 which is replaced by 5 = 3 + + Response P() Signature 0 0 0 = R() = 3 + 2 +
BIST: Signature Analysis Aliasing: UUT Response L SA N L - test length N - number of stages in Signature Analyzer L k = 2 All possible responses Faulty response Correct response N << L All possible signatures N k = 2
BIST: Signature Analysis Aliasing: UUT Response L SA N L - test length N - number of stages in Signature Analyzer L k = 2 - number of different possible responses No aliasing is possible for those strings with L - N leading zeros since they are represented by polynomials of degree N - that are not divisible by characteristic polynomial of LFSR L N 2 Probability of aliasing: - aliasing is possible P = L 2 2 N L 000000000000000... 00000 XXXXX L >> L P = 2 N N
BIST: Signature Analysis Parallel Signature Analyzer: Single Input Signature Analyser UUT 4 2 3 4 2 3 UUT Multiple Input Signature Analyser (MISR)
BIST: Signature Analysis Signature calculating for multiple outputs: LFSR - Test Pattern Generator LFSR - Test Pattern Generator Combinational circuit Combinational circuit Multipleer Multipleer LFSR - Signature analyzer LFSR - Signature analyzer
BIST: Joining TPG and SA LFSR UUT 2 3 4 FF FF FF FF Response string for Signature Analysis Test Pattern (when generating tests) Signature (when analyzing test responses)
BIST Architectures General Architecture of BIST BIST Control Unit Test Pattern Generation (TPG) Circuitry Under Test CUT Test Response Analysis (TRA) BIST components: Test pattern generator (TPG) Test response analyzer (TRA) BIST controller A part of a system (hardcore) must be operational to eecute a self-test At minimum the hardcore usually includes power, ground, and clock circuitry Hardcore should be tested by eternal test equipment or it should be designed selftestable by using various forms of redundancy
BIST Architectures Test per Clock: Disjoint TPG and SA: BILBO Joint TPG and SA: CSTP - Circular Self-Test Path: LFSR - Test Pattern Generator LFSR - Test Pattern Generator & Signature analyser Combinational circuit Combinational circuit LFSR - Signature analyzer
BIST: Circular Self-Test Architecture Circuit Under Test FF FF FF
BIST: Circular Self-Test Path CC CSTP CC CSTP CSTP CC R R CC CC CSTP CSTP
BIST Embedding Eample LFSR LFSR2 M M2 CSTP M4 MUX M5 M3 BILBO Concurrent testing: MISR LFSR, CSTP M2 MISR M2 M5 MISR2 (Functional BIST) CSTP M3 CSTP LFSR2 M4 BILBO MUX MISR2 M6
BIST Architectures STUMPS: Self-Testing Unit Using MISR and Parallel Shift Register Sequence Generator Test Pattern Generator LOCST: LSSD On-Chip Self-Test Scan Path BS BS CUT Scan chain CUT... Scan chain CUT TPG SA MISR SI IC Test Controller SO Error
Scan-Based BIST Architecture PS Phase shifter Scan-Forest Scan-Trees Scan-Segments (SC) Weighted scanenables for SS Compactor - EXORs Copyright: D.Xiang 2003
Software BIST SoC Software based test generation: CPU Core load (LFSRj); for (i=0; i<nj; i++)... end; Core j Core j+ ROM LFSR: 0000000000 N: 275 LFSR2: 0000000 N2: 900... Core j+... To reduce the hardware overhead cost in the BIST applications the hardware LFSR can be replaced by software Software BIST is especially attractive to test SoCs, because of the availability of computing resources directly in the system (a typical SoC usually contains at least one processor core) The TPG software is the same for all cores and is stored as a single copy All characteristics of the LFSR are specific to each core and stored in the ROM They will be loaded upon request. For each additional core, only the BIST characteristics for this core have to be stored
Problems with BIST The main motivations of using random patterns are: - low generation cost - high initial efeciency Problems: Very long test application time Low fault coverage Area overhead Additional delay Fault Coverage Time Possible solutions Weighted pseudorandom test Combining pseudorandom test with deterministic test Multiple seed Bit flipping Hybrid BIST Fault Coverage Time
Problems with BIST: Hard to Test Faults The main motivations of using random patterns are: - low generation cost - high initial efeciency Problem: Low fault coverage Pseudorandom Patterns from LFSR: test window: 2 n - Hard to test faults Fault Coverage Dream solution: Find LFSR such that: 2 n - Time Hard to test faults
Deterministic patterns Hybrid Built-In Self-Test ROM...... BIST Controller Pseudorandom patterns PRPG......... CORE UNDER TEST MISR SoC Core Hybrid test set contains pseudorandom and deterministic vectors Pseudorandom test is improved by a stored test set which is specially generated to target the random resistant faults Optimization problem: Where should be this breakpoint? Pseudorandom Test Determ. Test
Optimization of Hybrid BIST Cost of BIST: FAST estimation Number of remaining faults after applying k pseudorandom test patterns r NOT (k) # faults min C TOTAL Total Cost C TOTAL Cost of pseudorandom test patterns C GEN Cost of stored test C MEM Number of pseudorandom test patterns applied, k Figure 2: Cost calculation for hybrid BIST Pseudorandom Test C TOTAL = α k + β t(k) α k SLOW analysis # tests Det. Test β t(k) PR test length k PR test length # faults not detected # tests needed k r DET (k) r NOT (k) FC(k) t(k) 55 839 5.6% 04 2 76 763 23.2% 04 3 65 698 29.8% 00 4 90 608 38.8% 0 5 44 564 43.3% 99 0 04 42 57.6% 95 20 44 3 68.7% 87 50 5 28 78.% 74 00 6 45 85.4% 52 200 8 4 88.5% 4 4 3 70 93.0% 26 954 8 28 97.2% 2 560 8 6 98.4% 7 253 5 99.5% 3 3449 2 3 99.7% 2 459 2 99.9% 4520 0 00.0% 0
Deterministic Test Length Estimation Deterministic test (DT) Fault coverage Pseudorandom test (PT) 00% F* F F D k ( i ) F P E k ( i ) j i i * T D F k i Fast estimation for the length of deterministic test: For each PT length i* we determine - PT fault coverage F*, and - the imaginable part of DT FD k (i) to be used for the same fault coverage Then the remaining part of DT TD E k(i) will be the estimation of the DT length T D E k ( i ) Pseudorandom test length Deterministic test length estimation
Calculation of the Deterministic Test Cost Two possibilities to find the length of deterministic data for each possible breakpoint in the pseudorandom test sequence: ATPG based approach For each breakpoint of P- sequence, ATPG is used Fault table based approach A deterministic test set with fault table is calculated For each breakpoint of P-sequence, the fault table is updated for not yet detected faults FAST estimation Only fault coverage is calculated ATPG based: ATPG Detected Faults All PR patterns? No Net PR pattern Yes End Fault table based: ATPG Fault table update All PR patterns? No Net PR pattern Yes End
Calculation of the Deterministic Test Cost ATPG based approach For each breakpoint of P-sequence, ATPG is used ATPG based: R R 2 R k R k+ R k+2 R n ATPG Detected Faults All PR patterns? Task for fault simulator T T 2.... T n Faults detected by pseudorandom patterns Faults to be detected by deterministic patterns No Net PR pattern End Yes Task for ATPG T n+ T p New detected faults
Calculation of the Deterministic Test Cost Fault table based approach A deterministic test set with fault table is calculated For each breakpoint of P-sequence, the fault table is updated Fault table based: R R 2 R k R k+ R k+2 R n ATPG Fault table update Task for fault simulator T T 2.... T n Faults detected By pseudorandom patterns Fault table for full deterministic test All PR patterns? No Net PR pattern Yes End Updated fault tabel T n+ T p To be detected faults
Eperimental Data: HBIST Optimization Finding optimal brakepoint in the pseudorandom sequence: Pseudorandom Test Det. Test L OPT L MAX S OPT S MAX Optimized hybrid test process: Pseudorandom Test Det. Test Circuit L MAX L OPT S MAX S OPT B k C TOTAL C432 780 9 80 2 4 86 C499 2036 78 32 60 6 386 C880 5589 2 77 48 8 48 C355 522 2 26 52 6 388 C908 5803 05 43 23 5 62 C2670 658 444 55 77 30 26867 C3540 8734 297 2 0 7 889 C535 238 7 7 2 23 985 C6288 20 20 45 20 4 00 C7552 8704 583 267 6 5 26
Hybrid BIST with Reseeding The motivation of using random patterns is: - low generation cost - high initial efeciency Problem: low fault coverage long PR test Pseudorandom test: 2 n - Fault Coverage Hard to test faults Pseudorandom test: 2 n - Solution: many seeds: Time
Store-and-Generate Test Architecture # seeds ROM TPG UUT ADR Seeds RD Window Counter 2 Counter ROM contains test patterns for hard-to-test faults Each pattern P k in ROM serves as an initial state of the LFSR for test pattern generation (TPG) - seeds Counter counts the number of pseudorandom patterns generated starting from P k - width of the windows After finishing the cycle for Counter 2 is incremented for reading the net pattern P k+ beginning of the new window CL Pseudorandom test windows Seeds
HBIST Optimization Problem Using many seeds: Pseudorandom test: 2 n - Seed Pseudorandom sequences: Problems: How to calculate the number and size of blocks? Which deterministic patterns should be the seeds for the blocks? Deterministic test (seeds): Seed Seed 2 Seed n L Seed 2 Seed n Block size: 00% FC M Constraints Minimize L at given M and 00% FC
Hybrid BIST Optimization Algorithm D-patterns are ranked ATPG patterns Pattern selection Pseudorandom sequence PR i Algorithm is based on D-patterns ranking Deterministic test patterns with 00% quality are generated by ATPG Modified ATPG pattern table FC(PR i ) Detected faults subtraction, optimization of ATPG patterns The best pattern is selected as a seed A pseudorandom block is produced and the fault table of ATPG patterns is updated The procedure ends when 00% fault coverage is achieved
Hybrid BIST Optimization Algorithm 2 P-blocks are ranked PT min Deterministic test vector (seed) DT i Pseudorandom test sequence PR i Pseudorandom sequence removed with the block length optimization PT * Algorithm is based on P-blocks ranking Deterministic test patterns with 00% quality are generated by ATPG All P-blocks are generated for all D-patterns and ranked The best P-block is selected includeed into sequence and updated The procedure ends when 00% fault coverage is achieved
Cost Curves for Hybrid BIST with Reseeding Two possibilities for reseeding: Constant block length (less HW overhead) Dynamic block length (more HW overhead) Test length L 0000 9000 8000 7000 6000 5000 4000 3000 2000 000 0 L(b) C908 L2(b) M(b) Memory cost M 40 0 500 000 500 2000 2500 3000 20 00 80 60 40 20 0 Block size
Functional Self-Test Traditional BIST solutions use special hardware for pattern generation on chip, this may introduce area overhead and performance degradation New methods have been proposed which eploit specific functional units like arithmetic blocks or processor cores for on-chip test generation It has been shown that adders can be used as test generators for pseudorandom and deterministic patterns Today, there is no general method how to use arbitrary functional units for built-in test generation
Functional BIST Quality Fault coverage of FBIST compared to Functional test Data Functional testing Functional BIST B B2 Total B B2 Total 4/2 3.2 5.09 4.5 35.4 40.57 29.72 7/2 2.23 6.98 9.0 38.44 47.64 29.25 6/3 9.34 3.6 25.47 4.04 39.62 42.45 8/2 25.47 0.38 7.92 32.07 40.57 25.00 9/4 8.96 5.66 7.3 36.56 47.64 25.47 9/3 32.55 26.89 29.72 43.63 46.07 40.57 2/6 3.44 8.02 8.87 36.08 39.62 32.55 4/2 8.6 25.00.32 37.50 49.06 25.94 5/3 29.48 3.3 27.83 47.88 50.00 45.75 2/4 7.8 7.55 8.02 29.0 20.75 33.02 Aver. 8.96 7.83 7.97 37.74 42.5 32.97 Gain.0.0.0 2.0 2.4.8 Traditional Functional test UUT Result Reference Go/NoGo FBIST UUT Result HW overhead Signature Reference Go/NoGo FBIST: collection and analysis of samples during the working mode Fault coverage is better, however, still very low (ranging from 42% to 70%)
Eample: Functional BIST Functional BIST quality analysis Samples from N=20 cycles DB=64 Register block Control K Data SB=05 ALU Signature analyser K*N Functional test Data compression: N*SB / DB = 97 Fault simulator Fault coverage Test patterns (samples) are produced on-line during the working mode
Hybrid Functional BIST To improve the quality of FBIST we introduce the method of Hybrid FBIST The idea of Hybrid FBIST consists in using for test purposes the miture of functional patterns produced by the microprogram (no additional HW is needed), and additional stored deterministic test patterns to improve the total fault coverage (HW overhead: MUX-es, Memory) Tradeoff should be found between the testing time and the HW/SW overhead cost
Functional Hybrid Self-Test Functional BIST implementation MUX M Automatic Test Pattern Generator Register block ALU Deterministic test set Random resistant faults K Data Signature analyser Test patterns are stored in the memory
Cost Functions for Hybrid Functional BIST Total cost: Cost C Total = C FB_Total +C D_Total C Total = C FB_Total +C D_Total The cost of functional test part: C FB_Total = C FB_Const + αc FB_T + βc FB_M Opt. cost The cost of deterministic test part: αc FB_T + βc FB_M αc D_T + βc D_M C D_Total = C D_Const + αc D_T + βc D_M C D_Const C FB_Const Length of FBIST C FB_Const, C D_Const - HW/SW overhead C FB_T, C D_T - testing time cost α, β - weights of time and memory epenses Opt. length Problem: minimize C Total
Functional Self-Test with DFT Eample: N-bit multiplier N cycles Improving controllability T MUX Register block ALU F EXOR Improving observability K Signature analyser Data
Hybrid BIST for Multiple Cores Embedded tester for testing multiple cores Embedded Tester C2670 C3540 Test Controller BIST Test access mechanism BIST Tester Memory BIST BIST BIST C908 C880 C355 SoC
Hybrid BIST for Multiple Cores Deterministic test (DT) How to pack knapsack? How to compress the test sequence? Pseudorandom test (PT)
Multi-Core Hybrid BIST Optimization Cost of BIST: C TOTAL = α k + β t(k) FAST estimation Number of remaining faults after applying k pseudorandom test patterns r NOT (k) # faults min C TOTAL Total Cost C TOTAL α k SLOW analysis # tests Cost of pseudorandom test patterns C GEN Cost of stored test C MEM β t(k) Number of pseudorandom test patterns applied, k Figure 2: Cost calculation for hybrid BIST Pseudorandom Test Det. Test PR test length k Two problems: ) Calculation of DT cost is difficult 2) We have to optimize n (!) processes How to avoid the calculation of the very epensive full DT cost curve?
Deterministic Test Length Estimation Deterministic test (DT) Fault coverage Pseudorandom test (PT) 00% F* F F D k ( i ) F P E k ( i ) j i i * T D F k i Solution of the first problem: For each PT length i* we determine - PT fault coverage F*, and - the imaginable part of DT FD k (i) to be used for the same fault coverage Then the remaining part of DT TD E k(i) will be the estimation of the DT length T D E k ( i ) Pseudorandom test length Deterministic test length estimation for a single core
Deterministic Test Cost Estimation Total cost calculation of core costs: 8000 DT cost Memory Constraint 6000 5500 Constraint Core name: c499 c880 c355 c908 c535 c6288 c432 Memory usage: 5357 bits Memory usage: 353 480 025 363 236 0 0 Deterministic time: 33 8 25 2 0 0 Memory (bits) 4000 Core costs Cost Estimates for Individual Cores Real Cost Real cost Estimated Cost 2000 0 500 542 Solution Estimated cost 000 Total Test Lenght (clocks) 500 Total test length
Total Test Cost Estimation COST Using total cost solution we find the PT length: DT cost PT cost E COST D,k COST E* T COST T,k Total cost Total cost solution COST P,k j* k j min PT length solution E Solution Pseudorandom test (PT) length j Using PT length, we calculate the test processes for all cores: c432 c6288 4 4 2 c880 6 3 c908 c535 c355 c499 9 40 2 86 46 205 36 203 90 69 50 Total Test 23 Deterministic Pseudorandom 0 50 00 50 200 48 73 25
Multi-Core Hybrid BIST Optimization Iterative optimization process: - First estimation * - Real cost calculation 2 - Correction of the estimation 2* - Real cost calculation 3 - Correction of the estimation 3* - Final real cost
Optimized Multi-Core Hybrid BIST Pseudorandom test is carried out in parallel, deterministic test - sequentially
Test-per-Scan Hybrid BIST Every core s BIST logic is capable to produce a set of independent pseudorandom test The pseudorandom test sets for all the cores can be carried out simultaneously Embedded Tester Test Controller LFSR s327 Scan Path Scan Path Scan Path Scan Path LFSR LFSR s298 Scan Path Scan Path Scan Path Scan Path LFSR TAM Deterministic tests can only be carried out for one core at a time Tester Memory Only one test access bus at the system level LFSR Scan Path Scan Path Scan Path LFSR LFSR Scan Path Scan Path Scan Path LFSR is needed. Scan Path Scan Path SoC s423 s838
Bus-Based BIST Architecture Self-test control broadcasts patterns to each CUT over bus parallel pattern generation Awaits bus transactions showing CUT s responses to the patterns: serialized compaction Source: VLSI Test: Bushnell-Agrawal
Broadcasting Test Patterns in BIST Concept of test pattern sharing via novel scan structure to reduce the test application time:...... CUT CUT 2...... CUT CUT 2 Traditional single scan design Broadcast test architecture While one module is tested by its test patterns, the same test patterns can be applied simultaneously to other modules in the manner of pseudorandom testing
Broadcasting Test Patterns in BIST Eamples of connection possibilities in Broadcasting BIST: CUT CUT 2 CUT CUT 2 j-to-j connections Random connections
Broadcasting Test Patterns in BIST Scan configurations in Broadcasting BIST: Scan-In Scan-In...... CUT... CUT n...... MISR Scan-Out Common MISR...... CUT CUT n...... MISR MISR n Scan-Out Individual and multiple MISRs
Fault-Model Free Fault Diagnosis Combined cause-effect and effect-cause diagnosis Effect Effect Cause Faulty area Cause Faulty area ) Cause-Effect Fault Diagnosis Suspected faulty area is located Faulty system 2) Effect-Cause Fault Diagnosis Faulty block is located in the suspected faulty area 3) Fault Reasoning Failing test patterns are mapped into the suspected defect or into a set of suspected defects in the faulty block Test Faulty block Fault Failing test patterns
Embedded BIST Based Fault Diagnosis BISD scheme: Pseudorandom test sequence: Test Pattern Generator (TPG)...... BISD Control Unit Circuit Under Diagnosis (CUD)...... Output Response Analyser (ORA) Test patterns Pattern Signature Faults........................................................................... Diagnostic Points (DPs) patterns that detect new faults Further minimization of DPs as a tradeoff with diagnostic resolution May -4, 2008 26th International Conference on Microelectronics, Niš, Serbia 4/20
Built-In Fault Diagnosis Diagnosis procedure: Test Pattern Generator (TPG)...... BIST Control Unit. test 2. test 3. test Faulty signature Circuit Under Test (CUT)...... Output Response Analyser (ORA) Test patterns Number Signature Faults........................................................................ Correct signature 3. test Faulty signature
Built-In Fault Diagnosis Pseudorandom test fault simulation Binary search with bisectioning of test patterns All faults New faults Coverage 5 5 6.67% 2 5 0 50.00% 3 6 53.33% 4 7 56.67% 5 20 3 66.67% 6 2 70.00% 7 25 4 83.33% 8 26 86.67% 9 29 3 96.67% 0 30 00.00% 5 2 8 3 6 9 5 0 4 7 3 3 4 Average number of test sessions: 3,3 Average number of clocks: 8,67 0
Built-In Fault Diagnosis Pseudorandom test fault simulation Binary search with bisectioning of faults All faults New faults Coverage 5 5 6.67% 2 5 0 50.00% 3 6 53.33% 4 7 56.67% 5 20 3 66.67% 6 2 70.00% 7 25 4 83.33% 8 26 86.67% 9 29 3 96.67% 0 30 00.00% 2 5 0 5 3 4 3 4 6 8 7 9 3 Average number of test sessions: 3,06 Average number of clocks: 6,43 0
Built-In Fault Diagnosis Diagnosis with multiple signatures: Test pattern generator SA SA 2 Fault CUD D 3 D D 2 D 7 D 5 D6 SA 3 D 4 SA SA 2 SA 3
Built-In Fault Diagnosis Diagnosis with multiple signatures: No Codeword Diagnosis h 0 0 R Diagnostic tree R i 0 0 R R, R 2, R 3 h R j 0 R 2 P F/00 F/00 k l 0 R, R 2 R 3 v F/ F/0 k P i P j R 2 F/0 l R 3 F/ R, R 2 v R, R 2, R 3
Built-In Fault Diagnosis BIST with multiple signature analyzers Faulty signature Fault Test pattern generator CUD Intersection using tests Faulty signature Correct signature SA SA 2 SA SA 2 SA 3 Intersection using SA-s D 3 D D 2 D 7 D 5 D 6 Optimization of the interface between CUD and SA-s SA 3 D 4
Built-In Fault Diagnosis SA Resolution 5 SA Resolution 0 SA Resolution SA Test length 5 SA Test length 0 SA Test length Average resolution 240.0 230.0 220.0 20.0 200.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 0.0 00.0 90.0 80.0 70.0 60.0 50.0 40.0 30.0 20.0 0.0 0.0 Gain in speed of diagnosis Optimal number of failed patterns 5.0 2 3 4 5 6 7 8 9 0 ALL 65.0 60.0 55.0 50.0 45.0 40.0 35.0 30.0 25.0 20.0 5.0 0.0 Average test length Diagnosis with multiple signatures: Measured: - average resolution - average test length Compared: SA, 5SA, 0SA Gain in test length: 6 times Failed patterns
Etended Fault Models Etensions of the parallel critical path tracing for two large general fault classes for modeling physical defects: 0 0 Defect Multiple fault Resistive bridge fault SAF Conditional fault Pattern fault Constrained SAF Single faulty signal X-fault Byzantine fault Bridges Stuck-opens Multiple faulty signal
Diagnosis of Fault Model Free Defects Real test eperiment Simulation Circuit Under Diagnosis τ t Faulty machine FM(f) Fault evidence: for test pattern t σ t l t f Fault e(f,t) = ( τ t, σ t, l t, γ t ) γ t = min ( σ t, l t ) for full test T (sum) e(f,t) = ( τ, σ, l, γ) Test pattern t Copyright: H.J.Wunderlich 2007
Diagnosis of Fault Model Free Defects Real test eperiment Simulation Different classical fault cases Circuit Under Diagnosis Faulty machine FM(f) Classic model l t τ t γ t τ t σ t l t Test pattern t f Fault Single SAF 0 0 0 Multiple SAF 0 >0 0 Single conditional SAF >0 0 0 Multiple cond. SAF >0 >0 0 Delay fault >0 0 >0 General case >0 >0 >0 Copyright: H.J.Wunderlich 2007
Diagnosis of Fault Model Free Defects Real test eperiment Circuit Under Diagnosis τ t σ t l t Test pattern t Simulation Faulty machine FM(f) f Fault Ranking (on the top the most suspicious faults): () By increasing γ T (single SAF on top) (2) If γ T are equal then by decreasing σ T (3) If γ T and σ T are equal then by increasing l T γ t = min ( σ t, l t ) Eample: SAF γ T σ T l T f 0 42 0 f 2 30 42 5 f 3 30 42 25 f 4 30 42 30 f 5 30 36 38 f 6 38 23 22 f 7 38 23 23 Copyright: H.J.Wunderlich 2007
Fault Diagnosis Without Fault Models Transistor level Reverse defect mapping Logic level & & & & & & R IN M M 2 RT Level + * M 3 R 2 2 3 4 5 Defect W d Logic level Defective area dy System level Error detection Error (defective area) diagnosis
Fault Model Free Fault Diagnosis System network graph Test response: 0 0 S S 2 S 5 S 8 S S 3 S 6 S 9 Diagnosis: s S 4 S 7 S 0 No match Because of the unidirectional distortions of test responses, rectification is possible Rectified code Diagnostic table 2 3 4 2 3 4 5 0 6 7 8 0 9 0 0 Technical University Tallinn, ESTONIA 0 0