Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking diodes and transistors
Dynamic Power Dissipation Vdd Energy/transition = * V dd 2 Power = Energy/transition * f = * V dd 2 * f Not a function of transistor sizes! Need to reduce, V dd, and f to reduce power. Modification for Circuits with Reduced Swing V dd V dd V dd -V t E 0 1 = V dd ( V dd V t ) Can exploit reduced swing to lower power (e.g., reduced bit-line swing in memory)
Node Transition Activity and Power Consider switching a CMOS gate for N clock cycles E = C V N L 2 nn dd ( ) E N : the energy consumed for N clock cycles n(n): the number of 0->1 transition in N clock cycles P = lim avg N E N ------- f N clk = nn ( ) lim ------------ C N N L V 2 fclk dd α 0 1 = nn ( ) lim ------------ N N P avg = α 0 1 C L V 2 fclk dd Short Circuit Currents Vd d 0.15 I VDD (ma) 0.10 0.05 0.0 1.0 2.0 3.0 V in (V) 4.0 5.0
Short Circuit Power Consumption I sc Finite slope of the input signal causes a direct current path between V DD and GND for a short period of time during switching when both the NMOS and PMOS transistors are conducting. Short Circuit Currents Determinates E sc = t sc V DD I peak P 0 1 P sc = t sc V DD I peak f 0 1 Duration and slope of the input signal, t sc I peak determined by the saturation current of the P and N transistors which depend on their sizes, process technology, temperature, etc. strong function of the ratio between input and output slopes a function of
Impact of on P sc I sc 0 I sc I max Large capacitive load Small capacitive load Output fall time significantly larger than input rise time. Output fall time substantially smaller than the input rise time. I peak as a Function of x 10-4 2.5 2 = 20 ff When load capacitance is small, I peak is large. 1.5 I peak (A) 1 0.5 0 = 100 ff = 500 ff 0 2 4 6-0.5 x 10-10 time (sec) 500 psec input slope Short circuit dissipation is minimized by matching the rise/fall times of the input and output signals - slope engineering.
P normalized P sc sc as a Function of Rise/Fall Times 8 7 6 5 4 3 2 1 0 V DD = 3.3 V V DD = 2.5 V V DD = 1.5V 0 2 t sin /t sout 4 When load capacitance is small (t sin /t sout > 2 for V DD > 2V) the power is dominated by P sc If V DD < V Tn + V Tp then P sc is eliminated since both devices are never on at the same time. W/L p = 1.125 µm/0.25 µm normalized wrt zero input W/L n = 0.375 µm/0.25 µm rise-time dissipation = 30 ff Leakage Vdd Drain Junction Leakage Sub-Threshold Current Sub-threshold current one of most compelling issues in low-energy circuit design!
Reverse-Biased Diode Leakage GATE p + p+ N Reverse Leakage Current + - V dd I DL = J S A JS = 10-100 pa/µm2 at 25 deg C for 0.25µm CMOS JS doubles for every 9 deg C! Subthreshold Leakage Component
Review: Power Equations P = V DD2 f 0 1 + t sc V DD I peak f 0 1 + V DD I leakage Dynamic power (~90% today and decreasing relatively) Short-circuit power (~8% today and decreasing absolutely) Leakage power (~2% today and increasing) Static Power Consumption Vdd I stat V out V in =5V P stat = P (In=1).V dd. I stat Wasted energy Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)
Principles for Power Reduction Prime choice: Reduce voltage! Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 0.9 V by 2010!) Reduce switching activity Reduce physical capacitance