S P E C I F I C A T I O N

S P E C I F I C A T I O N SYMB. NO. APPD. CHKD. DSGD. LG INNOTEK CO., LTD. APPD. CHKD. DSGD. NOTE : TDQX P001F 04.09.06 Hyung- Teak Lim 04.0906 Ko- Young Yuen TITLE : SPECIFICATION DOCUMENT NO:NC40050 (1 / 17) LG INNOTEK Co., Ltd. (30)-4019

Index NO I T E M Page 1 General specification 3 2 Standard test condition 4 3 Electrical specification 5 4 PLL Information 6 5 Block Diagram 7 6 I 2 C H/W Interface 8 7 Block Diagram of H/W Power 8 8 Application Circuit 9 9 Reliability specification 10 10 Mechanical specification 10 LG INNOTEK Co., Ltd. Page 2 of 2

1. General specification NO I T E M S P E C I F I C A T I O N S N O T E S 1-1 RF input range 950MHz ~ 2150MHz 1-2 Input dynamic range - 65dBm ~ - 25dBm 1-3 Input connector F-female 1-4 Input impedance 75Ω 1-5 Channel selection system I 2 C Bus Interface (Clock 16.0 MHz) 1-6 Symbol rate 2 ~ 45Msps 1-7 Transport Stream Output Parallel and serial data output 1-8 QPSK Silicon Tuner IC TDA10086 Philips 1-10 Ambient temperature Operating 0 ~ +60 Storage -20 ~ +70 1-11 Humidity Operating Storage Less than 85% R.H. Less than 95% R.H. LG INNOTEK Co., Ltd. Page 3 of 3

2. Standard test condition Test for electrical specification shall be performed at following condition unless otherwise specified. NO I T E M S P E C I F I C A T I O N S 2-1 Ambient condition Temperature: 25 ± 2 Humidity: 65% ± 2%R.H If no doubt on test results, temperature + 5 +30 and humidity 45% 85%R.H could be applied. 30 minutes after DC power supplied. 2-2 Supply Voltage PIN No PIN Name Supply Voltage 3 VA1 + 3.3V ±0.05V 4 VA2 + 3.3V ±0.05V 11 VDD + 3.3V ±0.05V 8,9 SCL, SDA Specified tuning pulse 2-3 Current consumption *Receiving Frequency : 2150MHz / -10dBm SR =30MSps PR=7/8 PIN No PIN Name MIN TYP MAX Unit Condition * 3 VA1 25 30 ma VA1= + 3.3 V 4 VA2 160 ma VA2= + 3.3 V 11 VDD 210 ma VDD= + 3.3 V 2-4 Absolute maximum voltage (DC) PIN NO PIN Name MIN TYP MAX 1, 2 LNB Power + 25V ( 500mA-MAX) 3 VA1 3.135 3.3V 3.465 4 VA2 3.135 3.3V 3.465 11 VDD 3.135 3.3V 3.465 LG INNOTEK Co., Ltd. Page 4 of 4

3. Electrical specification Test Condition Item Condition Supply Voltage PIN No PIN Name Supply Voltage 3 VA1 + 3.3V ±0.05V 4 VA2 + 3.3V ±0.05V 11 VDD + 3.3V ±0.05V 8,9 SCL, SDA Specified tuning pulse Ambient temperature 25 ±5 Ambient humidity 65% ±10% NO Item Specification Condition Min TYP MAX Unit 3-1 RF Input VSWR 2.5 3.5 950MHz 2150MHz 3-2 Noise Figure(N.F) 8 12 db 950MHz 2150MHz 3-3 3-4 Desired signal Fo Intermodulation rejection 40 60 db Undesired signal (Fo+29.5MHz,Fo+59MHz) Or (Fo-29.5MHz,Fo-59MHz) Input Level :-25dBm I/Q Output level : 06Vp-p(1KΩ Load) Local oscillation signal leakage -68-63 dbm 950MHz 2150MHz at input terminal 3-5 Loop Through VSWR 2.5 4.5 3-6 Loop Through Gain -10 +10 db 950MHz 2150MHz 3-7 PLL Phase Noise -75-70 dbc/hz At 10KHz offset -85-80 dbc/hz At 100KHz offset PR = 1/2 4.0 4.5 3-8 Eb/No PR = 2/3 4.5 5.0 PR = 3/4 5.0 5.5 PR = 5/6 5.5 6.0 db BER = 2 10-4 at viterbi output PR =7/8 6.0 6.4 LG INNOTEK Co., Ltd. Page 5 of 5

4. PLL Information PROGRAMMING The programming of the ZIF-PLL is done through the I 2 C-bus. The READ/WRITE selection is done through the R/W bit (address LSB). The ZIF-PLL fulfils the mode I 2 C-bus, according to the Philips I 2 C-bus specification I 2 C-bus input The I 2 C-bus lines SCL and SDA can be connected to an I 2 C-bus system tied either to 3.3 V or 5.0 V, which allow direct connection to most of existing microcontrollers. Use of 2.5 V and 1.8 V impossible with option. Data transfer format should be MSB first, and 8bits word + Acknowledge bit. Pin SCL is the clock input Pin SDA is the data input/output Pin AS is for Address select Address selection (pin AS) Voltage on pin AS Write address Read address 0 to 0.1 Vcc C0 C1 0.2 Vcc to 0.3 Vcc or open pin C2 C3 0.4 Vcc to 0.6 Vcc C4 C5 0.9 Vcc to Vcc C6 C7 Master-Slave selection (pin MS): Voltage on pin MS Quartz mode IC mode 0 to 0.1 Vcc Master Normal functional mode in master 0.9 Vcc to Vcc Slave Normal functional mode in slave Data transfer in Write mode The data transfer in write mode use the following patten: Address Ack SubAddress Ack Data1 Ack Data2 Ack Data N Ack Subaddrress is automatically incremented starting from the initial value. LG INNOTEK Co., Ltd. Page 6 of 6

I 2 C table in Write mode Sub-address (hex) Table 4 : I 2 C Write Mode Map 9X BBIAS3 BBIAS2 BBIAS1 BBIAS0 X mean does not care I 2 C table in Write mode (Default at POR) Bits description: MSB 6 5 4 3 2 1 LSB 0X PDPLL PDZIF PFLOOPT PDXTOUT PDRSSI PDLNA PDQUARTZ TEST1 1X R2 R1 R0 D4 D3 D2 D1 D0 2X N14 N13 N12 N11 N10 N9 N8 N7 3X N6 N5 N4 N3 N2 N1 N0 CALMANUAL 4X FC4 FC3 FC2 FC1 FC0 5X BBGAIN3 BBGAIN2 BBGAIN1 BBGAIN0 RFATT 6X CPCURSEL CPTST FUP FDN CP2TST FPFD2 CPHIGH 7X AMPVCO2 AMPVCO1 AMPVCO0 PORT1 PORT0 8X CALTIME SELVTH1 SELVTH0 SELVTL1 SELVTL0 Sub-address (hex) Table 5 : I 2 C Write Mode Map (default at POR) MSB 6 5 4 3 2 1 LSB 0X 0 0 0 0 1 0 0 1 1X 0 0 1 0 0 0 0 0 2X 0 0 0 0 0 0 0 1 3X 0 0 0 0 0 0 0 1 4X 0 0 0 0 0 - - - 5X 0 0 0 0 - - - 0 6X 0 0 X X 0 X 0-7X 1 0 0 - - - 0 0 8X 0 - - 0 0 0 0-9X 0 0 0 0 - - - - PDxxx Power down section: PDPLL: Power down of all the synthesizer part. PDZIF: Power down of all signal decoding part except: LNA, Rssi, and Loop-through. PDLOOPT: Power down of the LOOP-through. PDXTOUT: Power down of the Xtout output. PDRSSI: Power down of the input level detecter (Rssi). PDLNA: Power down of the Low noise amplifier. PDQUARTZ: Power down of the quartz oscillator. For all those signals: State Action 0 Function On 1 Function Off TEST1 Should be 1. LG INNOTEK Co., Ltd. Page 7 of 7

R<2:0> Reference divider range. This register select the ratio between the comparison frequency and the quartz frequency. R<2:0> state action R2 R1 R0 Comparison frequency 0 0 0 2 MHz 0 0 1 1 MHz 0 1 0 500 khz 0 1 1 250 khz 1 0 0 125 khz 1 0 1 125 khz 1 1 0 125 khz 1 1 1 125 khz D<4:0> VCO pre programming range: This register is also called Dword: It determines the ratio between LO frequency and VCO frequency Dec D<4:0> state ratio Flo/Fvco D4 D3 D2 D1 D0 0 0 0 0 0 0 0.27 1 0 0 0 0 1 0.29 2 0 0 0 1 0 0.31 3 0 0 0 1 1 0.33 4 0 0 1 0 0 0.36 5 0 0 1 0 1 0.36 6 0 0 1 1 0 0.38 7 0 0 1 1 1 0.40 8 0 1 0 0 0 0.42 9 0 1 0 0 1 0.43 10 0 1 0 1 0 0.44 11 0 1 0 1 1 0.45 12 0 1 1 0 0 0.46 13 0 1 1 0 1 0.47 14 0 1 1 1 0 0.50 15 0 1 1 1 1 0.54 16 1 0 0 0 0 0.55 17 1 0 0 0 1 0.56 18 1 0 0 1 0 0.58 19 1 0 0 1 1 0.60 20 1 0 1 0 0 0.63 21 1 0 1 0 1 0.64 22 1 0 1 1 0 0.67 23 1 0 1 1 1 0.70 24 1 1 0 0 1 0.75 25 1 1 0 0 1 0.78 26 1 1 0 1 0 0.88 27 1 1 0 1 1 0.88 28 1 1 1 0 0 0.88 29 1 1 1 0 1 0.88 30 1 1 1 1 0 0.88 31 1 1 1 1 1 0.88 Those bits are used for the calibration protocol of the internal VCO. LG INNOTEK Co., Ltd. Page 8 of 8

N<14:0> Main divider range. This register control the ratio between the LO frequency and the comparison frequency. The ratio N is equal to N14 x 2 14 + N13 x 2 13 + + N1 x 2 + N0 CALMANUAL Select manual or automatic LC oscillator calibration. This bit control the LC VCO frequency programming mode. State Action Automatic process control. 0 The LC VCO search the better ratio of the Dword in way to have the optimum tuning frequency. Manual process control. 1 The LC VCO is tuned by selecting the programmed Dword. FC<4:0> RX s base band cutoff frequency control. The register select the cutoff frequency of the RX s base band filter. The cutoff frequency could be set from 5MHz to 36 MHz in 32 steps of 1MHz. Dec FC<4:0> state base band cutoff FC 4 FC 3 FC 2 FC 1 FC 0 Frequency (in MHz) (2) 0 0 0 0 0 0 5 1 0 0 0 0 1 6 2 0 0 0 1 0 7 3 0 0 0 1 1 8 4 0 0 1 0 0 9 5 0 0 1 0 1 10 6 0 0 1 1 0 11 7 0 0 1 1 1 12 8 0 1 0 0 0 13 9 0 1 0 0 1 14 10 0 1 0 1 0 15 11 0 1 0 1 1 16 12 0 1 1 0 0 17 13 0 1 1 0 1 18 14 0 1 1 1 0 19 15 0 1 1 1 1 20 16 1 0 0 0 0 21 17 1 0 0 0 1 22 18 1 0 0 1 0 23 19 1 0 0 1 1 24 20 1 0 1 0 0 25 21 1 0 1 0 1 26 22 1 0 1 1 0 27 23 1 0 1 1 1 28 24 1 1 0 0 0 29 25 1 1 0 0 1 30 26 1 1 0 1 0 31 27 1 1 0 1 1 32 28 1 1 1 0 0 33 29 1 1 1 0 1 34 30 1 1 1 1 0 35 31 1 1 1 1 1 36 LG INNOTEK Co., Ltd. Page 9 of 9

BBGAIN<3:0> RX s base band gain control. This register control the additional gain of the base band between 0 and 0dB. BBGAIN<3:0> BBGAIN3 BBGAIN2 BBGAIN1 BBGAIN0 Additional gain in db (3) 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1.6 0 1 1 0 3 0 1 1 1 4.6 1 0 0 0 6.3 1 0 0 1 7.3 1 0 1 0 8.2 1 0 1 1 8.5 1 1 0 0 8.8 1 1 0 1 8.8 1 1 1 0 9 1 1 1 1 9 RFATT 20dB RF attenuation control. This bit control the RF attenuation inside the LNA amplifier When active, the LNA works in attenuation (-8dB gain). The Loop-through signal is also attenuated by 20dB. State Action 0 Normal gain of RF path 1 20dB attenuation in RF path CPCURSEL Select main loop charge pump current State Action 0 Low charge pump current 1 High charge pump current CPTST, FUP, FDN Main loop charge pump test. Those bits force the inputs of the main loop charge pump. Thus the current and leakage measurement could be done. This test could be used also to force the VCO at its maximum or minimum tuning voltage. CPTST FUP FDN action 0 X X Test disable 1 0 0 Sink and source OFF. Leakage measurement 1 0 1 Sink Off, source On. Source measurement 1 1 0 Sink On. Source Off. Sink measurement 1 1 1 Sink On, source On. CP2TST, FDF2 Second loop charge pump test. Those bits force the input of the second loop charge pump. This test could be used to force the LO VCO at its Maximum or minimum tuning voltage. CPTST FPFD2 action 0 X Test disable 1 0 Sink On and Source Off. LO VCO maximum frequency measurement 1 1 Sink Off, source On. LO VCO maximum frequency measurement LG INNOTEK Co., Ltd. Page 10 of 10

CPHIGH Select main loop charge pump current range State action 0 First charge pump active (low currents) 1 Second charge pump active (high currents) PORT<1:0> Control PORT output. Those bits control the use of PORT0 and PORT1. PORT are realized with open drain NMOS transistor. PORT0 action 0 PORT0 at high impedance 1 PORT0 in sink mode. Min 9mA drive capability PORT1 action 0 PORT1 at high impedance 1 PORT1 in sink mode. Min 9mA drive capability CALTIME Calibration wait time control. This register controls the duration of the wait time of the calibration. This time is use to wait PLL locking after programming Dword. The reference clock of the time is the comparison frequency of the PLL. CALTIME Fe divider ratio Wait time for Fc = 1MHz (in ms) 0 28673 28.673 1 32769 32.769 SELVTH<1:0> and SELVTL<1:0> Maximum voltage tuning threshold for calibration control. Those register controls the voltage threshold for ACUP and ACDN comparators. Those comparators sense the LC VCO tuning voltage at pin VT. SELVTL 1 SELVTL 0 Voltage threshold in volt 0 0 0.6 0 1 0.5 1 0 0.4 SELVTH 1 1 0.3 VT bi t Voltage 11 2.1 10 2.0 01 1.9 00 1.8 SELVTH 1 SELVTH 0 Voltage threshold in volt 0 0 1.8 0 1 1.9 1 0 2.0 1 1 2.1 SELVTL 00 0.6 01 0.5 10 0.4 11 0.3 LG INNOTEK Co., Ltd. Page 11 of 11

BBIAS<3:0> Base band bias current control. This register modifies the band bias current through different parts: Output buffer or other amplifier. Output Buffer All others Amp. Current in BBIAS code BBIAS3 BBIAS2 BBIAS1 BBIAS0 Buffer Amp ua 0 0 0 0 0 80u 80u 1 0 0 0 1 80u 106u 2 0 0 1 0 80u 133u 3 0 0 1 1 80u 160u 4 0 1 0 0 106u 80u 5 0 1 0 1 106u 106u 6 0 1 1 0 106u 133u 7 0 1 1 1 106u 160u 8 1 0 0 0 133u 80u 9 1 0 0 1 133u 106u 10 1 0 1 0 133u 133u 11 1 0 1 1 133u 160u 12 1 1 0 0 160u 80u 13 1 1 0 1 160u 106u 14 1 1 1 0 160u 133u 15 1 1 1 1 160u 160u Nominal value should be settled maximum: BBIAS<3:0>=1111 Data transfer in Read mode The data transfer in read mode use the following pattern Address Ack Data1 Ack Data2 Ack I 2 C table in Read mode Table 6 : I 2 C Read Mode Map Bytes MSB 6 5 4 3 2 1 LSB 0 POR LOCK ACUP ACDN ERRORCAL x x x 1 1 INLEVEL1 INLEVEL0 DW4 DW3 DW2 DW1 DW0 Bits description POR Power On Reset This bit is set to 1 at the VCCDIG power supply ramp-up. It is set to 0 after first read of the IC. When VCCDIG falls below 1.5 volt, this bit is set to 1. This is to prevent loss in internal I 2 C register programming. LOCK Synthesizer lock indicator This bit is set to 1 when the synthesizer is locked. ACUP Auto Calibration Up threshold control State Condition 0 LC VCO tuning voltage is lower than VTH (see SELVTH<1:0>) 1 LC VCO tuning voltage is upper than VTH (see SELVTH<1:0>) ACDN Auto Calibration Down threshold control State Condition 0 LC VCO tuning voltage is upper than VTL (see SELVTL<1:0>) 1 LC VCO tuning voltage is lower than VTL (see SELVTL<1:0>) LG INNOTEK Co., Ltd. Page 12 of 12

ERRORCAL Calibration defect detection This bit is set to 1 when the calibration unit control tries to go lower or higher than the minimum or maximum Dword ratio. INLEVEL<1:0> RF input level indicator This register gives the RF input level in dbm INLEVEL<1:0> INLEVEL1 INLEVEL0 dec RF Power in dbm 0 0 0 Power<-30 0 1 1-30<power<-20 1 0 2-20<power<-15 1 1 3-15<power DW<4:0> Internal Dword register This register gives the internal Dword value. This value could be programmed D<4:0> value in manual mode or the calculated value after LC VCO calibration in automatic mode. See table of D<4:0> for ratio of Flo/Fvco. LG INNOTEK Co., Ltd. Page 13 of 13

5. Block Diagram LG INNOTEK Co., Ltd. Page 14 of 14

6. I2C H/W Interface 7. Block Diagram of H/W Power PIN No PIN Name Supply Voltage Current (Typical) Ripple (Max) 3 VA1 + 3.3 V ±0.125V 25mA 20mVp-p 4 VA2 + 3.3V ±0.125V 160mA 20mVp-p 11 VDD + 3.3V ±0.125V 210mA 20mVp-p LG INNOTEK Co., Ltd. Page 15 of 15

8. Application Circuit Pin NO Pin Name PIN DESCRIPTION 1 LNBB LNB voltage supply. To put 1000pF of ceramic capacitor into ground. 2 LNBA LNB voltage supply. To put 1000pF of ceramic capacitor into ground. 3 VA1 +3.3V Supply for RF Amp (1 st Amp) 4 VA2 +3.3V Supply for ZIF IC (TDA 8263) 5,6,7,10 NC It is not connected inside the unit. We advise to ground it. 8 SDA I 2 C Bus 9 SCL I 2 C Bus 11 VDD + 3.3V Supply for QPSK Link IC. (TDA 10086) 12 F22 22 khz Tone or Programmable Output Port or DiSEqC Output 13 NC NC 14 ~ 21 D0 ~ D7 Output Data 22 BCLK Output Byte Clock; or Bit Clock in Serial Mode. 23 D/P Data/Parity Signal. 24 STR OUT Output 1st byte Signal (synchro byte clock) 25 ERROR Output Error Signal. Set in case of uncorrectable packet. 26 RESET Reset, active at low level. If L is inputted, the Silicon Tuner IC is initialized. When powering the unit, please input the reset signal. LG INNOTEK Co., Ltd. Page 16 of 16

9. Reliability specification Following value shall be maintained after each reliability test compared with initial value (1) Tuning voltage change±1.5v MAX (2) Practical receiving shall be maintained with PLL locked NO I T E M S P E C I F I C A T I O N S 9-1 Heat Load Test a Initial value measured at standard test condition. b Leave samples in 70 ±2 for 96±5 hours, and in standard test condition for 30 minutes, then take measurements within 1 hour 9-2 Humidity Load Test a Leave samples in 40 ±2 for 24±2 hours with standard power supply,then in standard ambient for 30 minutes, b Initial values are measured at standard test condition. c Leave samples in 40 ±2, 90 ~ 95%RH for 96±5 hours, then in standard test condition for 2 hours. d Take measurements within 1 hour. 9-3 Cold Test 9-4 Life Test 9-5 Vibration Test a Leave samples in -20 ±2 for 96±5 hours, then in standard ambient for 60 minutes with standard power supply b Take measurements within 1 hour. a Take measurements in standard test condition. b Leave samples for 1000 hours, in nominal ambient with standard power supply. c Take measurements within 1 hour. a Vibration test fixture is used to vibrate the tuner with Total amplitude: 1mVp-p Frequency range: 10 55 Hz Freq. Consecutiveness: once per minute b Time duration for each three time directions: 40 minutes 10. Mechanical specification NO I T E M S P E C I F I C A T I O N S 10-1 Outline View No defects of wiring, soldering and assembling No dirt, rust, corrosion or foreign material 10-2 Terminal strength Vertical direction: More than 2N(2Kgf) Folding: Bending left and right up to 45 o 2 times 1 time 1 time should not damage the terminals. 45 o 45 o (Bending speed is 2 sec/time) LG INNOTEK Co., Ltd. Page 17 of 17

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