REALIZATION OF EFFECTIVE REVERSIBLE DECODER BASED COMBINATIONAL CIRCUITS

Volume 120 No. 6 2018, 4503-4517 ISSN: 1314-3395 (on-line version) url: http://www.acadpubl.eu/hub/ http://www.acadpubl.eu/hub/ REALIZATION OF EFFECTIVE REVERSIBLE DECODER BASED COMBINATIONAL CIRCUITS V.Rama Krishna Reddy 1, V.Venkata Rao 2, M.Sailaja 3, Ch.Karthik 4, E.Narendra 5 1,3,4,5 Assistant Professor, 2 Professor, Electronics & Communication Engineering. 1,2,4,5 Narasaraopeta Engineering College, Narasaraopet, 3 GVR&S College of Eng. & Tech., Guntur, India. krishna.venna83@gmail.com June 26, 2018 Abstract Reversible logic circuit design is having vibrant role in the zones likelow power CMOS, DNA computing, quantum computing, opticaland nanotechnology etc. Now a days all the electronic devices are suffering with power dissipation and heat removal complications. These problems will be easily catered by reversible logic circuits. The categorized elements which are capable to decode the instructions and address in all computational systemsare decoders. Thispaper boon the design of combinational circuitsviz comparator,half adder/subtractor, full adder/subtractor, multiplexer, de-multiplexer using reversible decoder circuit. And also presents a comparative study and analysis of reversible gates to obtain finest solution.hl gate is used as a 2:4 decoder and it is a 4-input, 4-output reversible logic gate. This proposed method targets the 1 4503

minimization of quantum cost (Q.C), constant inputs (K.Is), garbage outputs (G.Os) and complexity of the circuit. In this proposed design mainlyr gate, HL gate are utilized. Keywords: Reversible logic, Decoder, HL gate, R gate,feynman gate. 1 INTRODUCTION In digital circuit design the major issue for designer a well as customer is power consumption and power dissipation.power dissipation leads to damage the electronic gadgets, limits the life span of the device and reduces the performance of the system.all the digital logic circuits are constructed by using irreversible(conventional) logic gates like AND, OR, XOR gates etc. and such logic circuits are known as irreversible logic circuit.all these logic gates dissipates energy in the form of heat whenever there is a loss of data.in 1960,Laundauer research[1] shown that the irreversible logic circuit dissipates K*T*ln 2 Joules of heat energy for every bit of information loss where k-boltzmanns constant,t-room temperature at which circuit is operated, at the room temperature the dissipated heat can be very small but not negligible in quantity. In 1973,C.H.Bennett[2]shown that power dissipation will be made zero if the computations are carried out in reversible fashion.in reversible logic circuit the amount of dissipated heat energy becomes zero by maintaining no information loss i.e always the dissipated heat energy is proportional to information loss. A circuit which results information loss is irreversible circuit. A circuit which results no information loss is reversible circuit.a group of such reversible logic gates are needed to build a reversible circuit.in 1980,Edward Fredkin and Tommaso Toffoli [4]developed the universal reversible logic gates named as Fredkin and Toffoli gates and works on reversibility with 3 inputs and 3 outputs.these Fredkin and Toffoli gates gives no information loss and no power dissipation. Later on different reversible gates are developed such as Feynman gate, double Feynman gate, Peres gate, R gate, URG gate, HNG gate and HL gate. A logic gate is said to be reversible if and only if the gate is having equal number 2 4504

of input and output terminals,for every input bit stream there must be a unique output bit stream and provides one-to-one mapping between input and output lines.rest of the paper systematizedby way oftracking section-iipresents basic reversible logic gates, section-iii presents existed design methods,section-iv presents proposed method of decoder based combinational circuits,section-v presents analysis of proposed designs, section-vi gives comparative study between proposed & reference methods and section-vi presents conclusion of the work. 2 REVERSIBLE LOGIC GATES A circuit designed with solitary reversible logic gates is known a reversible logic circuit and it gives no power dissipation. A reversible logic gate is defined as a N*N logic gate with equal number of input and output terminals and one to one mapping among input & output bit streams.to maintain reversibility, it is necessary to apply some extra inputs as logic 0/1 are known as K.I s and also a reversible logic gate generates annoying outputs(unemployed outputs) are known as G.O s.a reversible logic circuit performance will be measureded interms of Q.C, K.I s, G.Os.Q.C is the number of primitive gates used to construct a particular reversible logic gate.the primitive gates are 1*1 and 2*2 basic gates.the existed and useful reversible logic gates for the proposed deigns are as follows. Figure 1: Gate Feynman Figure 2: Double Feynman Gate Figure 3: Gate Fredkin Many reversible logic gates are developed to construct reversible circuits. NOT gate is treated as a 1*1 reversible logic gate with Q.C of zero. Fig. 1 shows 2*2 Feynman gate which isalso known as CNOT gate and is one of the primitive reversible logic gate.feynman gate performs XOR function with one G.O. Reversible logic gates dont support Fan-out, in such a situation 3 4505

Figure 4: Peres Gate Figure 5: R Gate Figure 6: HL Gate Feynman gate is used to duplicate the desired logic values.outputs of Feynman gate are given asp=a,q=a B.Q.C of the Feynman gate is one.fig. 2 shows 3*3double Feynman gate which performs two XOR operations, Outputs of double Feynman gate are P=A, Q=A B, R=A C.Q.C of the double Feynman gate is two.fredkin gate is shown in Fig. 3 with inputs A, B, C & outputs P, Q, and R. It is a 3*3 gate with outputs P=A, Q= B AC, R= AB and it will be used as AND, OR, NOR, NAND logic functions and 2:1 multiplexer by applying one of the input as a constant logic 0/1. Fredkin gateq.c is five. Peres gate is shown in Fig. 4 with inputs A, B, C and output expressions P=A, Q=A B, R=AB C and is used to have the functions XOR,AND, and NAND with Q. C 4. R gate is shown in Fig. 5 with output expressions P=A, Q=AB, R= B+AC and is used to get the functions OR, AND with Q.C 4. Fig. 6 depicts the HL gate which is a 4*4 special gate with Q.C 7.Outputs of HL gate are defined as P=A C B, Q=AB C BD, R= B C BD, S=A BC D. HL gate will be used as a 2:4 Decoder with two K.I s i.e. C=0, D=1. 3 EXISTING METHOD Decoders are the prime elements in all communication devices for decoding information codes and widely used in computing systems to select the memory devices & for instruction decoding. Thus farmany reversible decoders are developed with different reversible logic gates. Initially2:4decoder [7] was built using 3-Fredkin gates with 3-K.I s, 2-G.O s and Q.C is 15 is shown in Fig. 7. Later it was implemented by using 1-Feynman gates & 2-Fredkin gates [8] with 3-K.I s, 1-G.O s and Q.C11 is shown in Fig. 8. Later on 2:4 decoder came in to picture[9] using a single gate known as HL gate with 2-K.I s,no G.O s and Q.C 7 is shown in Fig. 9.Many 4 4506

combinational circuits like comparator, adders, subtractors, MUX, DEMUX, were proposed earlier[6] by using 2:4 decoder. In all these designs decoders were designed using Feynman gates & Fredkin gates, in such way that all the circuits may have more number of reversible logic gates, more number of K.I, more G.O s and gives high Q.C. In the existing method a full adder, full subtractor, 4:1 MUX, and 1-bit comparator were designed using Feynman & Fredkin gates with G.Os 12, 12,17,5 and Q.C 61,63,46,16 respectively. All these Fredkin gates are replaced with HL gate and R gates to get healthier G.O s with lowq.c. Figure 7: 2:4 Decoder with 3-FREDKIN gates Figure 8: 2:4 Decoder with 1-Feynman 5 4507

Figure 9: 2:4 Decoder with HLgate 4 PROPOSED METHOD TO IMPLEMENT COMBINATIONAL CIRCUITS This paper presents design of 1-bit comparator,half adder/subtractor, Full adder/subtractor, Multiplexer, De-multiplexer using HL gate.in all the designs decoder is used to produce minterms.design of 1-bit comparator using 1-HL gate and 1-Feynman gate is shown in Fig. 10 with A,B as input bits & LT(lessthan),GT(greaterthan),EQ(equal) asoutput bits.it has2-k.i s, 1-G.O&Q.C is 8. The output signals LT=1 indicates A<B, GT=1 indicates A>B, and EQ=1 indicates A=B.Design of Half adder is shown in Fig. 11 as A,B are inputs & Carry, Sum are outputs and having 3-K.I s, 3-G.O s.fig. 12 shows Half Subtractor with A,B as inputs & Diff(difference), Br(barrow) as outputs.it is having 4-K.I s,4-g.o s. Fig. 13 shows 3:8 decoder ussing 1-HL gate, 4-R gates and A,B,C are inputs & D0 to D7 are the outputs.it has 6-constant inputs, 1-G.O.Fig. 14 shows Full Adder deign using a 3:8 decoder and R gates with A,B,C as inputs & CARRY, SUM as outputs. It has 12-K.I s,13-g.o s. Fig. 15 shows Full subtractor deign using a 3:8 decoder and R gates with A,B,C as inputs & BARROW, DIIFFERENCE as outputs. It has 12-K.I s, 13-G.O s. A full adddder / subtractor circuit is 6 4508

depicted in Fig. 16 which is having 13-K.I s, 13-G.O s. Figure 10: 1-bit comparator Figure 11: Half adder with SUM,CARRY, BARROW as outputs.multiplexer and Demultiplexer circuits are shown in Fig. 17, Fig. 18 respectively, both are designed using HL & R gates. The multiplexerdesigned with S1,S0 as selection lines, A,B,C,D as inputs, K1 to K7 as K.I s & MUX as output. De-multiplexer is having 1-data, 2-control inputs & D0 t0 D3 as outputs. All the proposed dessigns are summerised in the Table 1. 7 4509

Figure 12: Half Subtractor Figure 13: 3:8 Decoder 8 4510

Figure 14: Full Adder Figure 15: Full subtractor Figure 16: Full Adder / subtractor 9 4511

5 ANALYSIS OF PROPOSED DESIGNS All the proposed designs are Analysed interms of K.I s, G.O s, number of gates used in the design, Q.C and that analysis report is graphically shown in Fig. 19. Figure 17: Multiplexer Figure 18: De-Multiplexer 10 4512

6 COMPARISON REPORT OF PROPOSED AND REFERENCE METHODS The proposed designs are compared with ref[6] interms of number of G.Os obtained in the circuit, total Q.C of the designed circuit and it is graphically shown in Fig. 20, Fig. 21 respectively. All the designs gives good performance. 7 CONCLUSION Finally by using HL gate as a 2:4 decoder based combinational circuits like 3:8 decoder, 1-bit comparator, Half adder/subtractor, Full adder/ subtractor, multiplexer and demultiplexer circuits are offered in this paper along with analysis report.by using the HL gate, all circuits will be deigned with low Q.C, less number of contant inputs and G.Os.Further,the needy circuits like 4:16 decoder, 8:1 multiplexer, code converters, Multipliers and ALU will implemented by using HL gate and R gate.this kind of design saves power and minimizes the amount of dissipated heat energy. 11 4513

Figure 19: Proposed Vs Ref [6]with respect tog.o s Figure 20: Proposed Vs Ref [6] with resspect to Q.C 12 4514

References [1] R Landauer, Irreversibility and heat generation in the computing process, IBM Journal of Research and Development, vol. 5, 1961, pp. 183-191. [2] C. H. Bennett, Logical reversibility of computations, IBM Journal of Research and Development, vol. 17, 1973, pp. 525-532. [3] T. Toffoli., Reversible Computing, Tech memo MIT/LCS/TM-151, MIT Lab for Computer Science 1980. [4] D. Maslov, G. W. Dueck, and D. M. Miller, Synthesis of Fredkin-Toffoli reversible networks IEEE Trans. VLSI Systems, vol.13, no.6, pp. 765-769, 2005. [5] E. Fredkin, and T. Toffoli, Conservative logic, International J. Theor. Physics, vol. 21, pp. 219-253, 1982.2014 International Conference on Signal Processing and Integrated Networks (SPIN) 353. [6] Gopi Chand Naguboina, K.Anusudha, Design and Synthesis of Combinational Circuits Using Reversible Decoder in Xilinx, IEEE International Conference on Computer, Communication, and Signal Processing (ICCCSP-2017). [7] Arvind Kumar and SumitGugnani, Synthesis of 4-to- 16 Decoder, International Conference in year 2013 NIT Kurukshetra, Vol. 1, 2013, pp. 2320-8945 [8] Ravish Aradhya HV, Chinmaye R, Muralidhara KN, Design, Optimization and Synthesis of Efficient Reversible Logic Binary Decoder, International Journal of Computer Applications, Vol. 46 No.6, 2012, pp. 0975 8887 [9] Lafifa Jamal and Hafiz Md. HasanBabu, Design and Implementation of a Reversible Central Processing Unit, IEEE Computer Society Annual Symposium on VLSI, Dhaka, Bangladesh, 2015 IEEE. 13 4515

[10] M. Shamsujjoha, and H. M. H. Babu, A Low Power Fault Tolerant Reversible Decoder Using MOS Transistor, 2013 26th InternationalConference on VLSI Design and the 12th International Conference on Embedded Systems, pp. 368 373, 2013. 14 4516

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