KINGS COLLEGE OF ENGINEERING PUNALKULAM. DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE : EC1401 SEM / YEAR : VII/ IV SUBJECT NAME : VLSI DESIGN UNIT I CMOS TECHNOLOGY 1. What is mean by Epitaxy? 2. What is isolation? 3. What are the steps involved in manufacturing of IC? 4. What is the special feature of Twin-Tub process? 5. What are the various process used in SOI process? 6. Draw the Isotropic etching process diagram. 7. What is siliside? 8. What is AOI? 9. Define fabrication process. 10. What do you mean by Isolation 1. Explain the silicon semiconductor technology with various processes that are involved in the sae. 2. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well CMOS process to fabricate the n-switches.
3. Write brief notes on (i) Twin-Tube process (8) (ii) Silicon On Insulator (SIO) process. (8) 4. How do you enhance the CMOS process and explain about an interconnect and a circuit element to do so. 5. Explain the following terms with neat diagram (i) Latchup (8) (ii) Latchup Prevention. (8) 6. List out the layout design rule. And draw the physical layout for one basic gate and two universal gates. UNIT II MOS TRANSISTOR THORY 1. Draw the graph of n-mos depletion mode. 2. Draw the diagram for the accumulation mode. 3. Draw the Dc transfer characteristics curve. 4. Define noise margin. 5. Define Rise Time. 6. Draw the symbol for tristate inverter. 7. Give the relation of RT with FT. 8. Differentiate the nmos from pmos. 9. What are all the factors can be extracted from the Vth equation. 10. Define the Power disipatiion All questions Sixteen Marks: 1. Explain the n MOS and p MOS enhancement transistor with its physical structure. 2. Derive and explain the (I) Threshold voltage equation, (8) (II) MOS DC equation. (8) 3. Explain that how the MOS transistor is to be analysed by the small scale models.
4. Explain the complimentary CMOS inverter DC characteristics. 5. Write short notes on (I) Noise Margin, (10) (II) Rise Time, (3) (III) Fall Time. (3) UNIT III SPECIFICATION USING VERILOG HDL 1. How do you declare the bus in the HDL? 2. Write the HDL coding for Modulo 2 Adder. 3. Give the duty cycle equation form the negative logic systems. 4. Define bit and byte. 5. What are the uses of UCF file? 6. Define FSM. 7. What do you mean by Data flow model? 8. Define Mealy network. 9. Define vector in verilog. 10. What is component in HDL? 1. Explain the process flow that is followed to develop a project by any HDL with example. 2. Differentiate the various modes to develop the project and explain them with an example. 3. Develop the project using HDL to realize the function of a ripple carry adder and draw its RTL. 4. Design and develop a project in HDL to compare x 5 x 4 x 3 x 2 x 1 x 0 with y 5 y 4 y 3 y 2 y 1 y 0. 5. Design a full adder by cascading two half adders and develop a project to realize it in model simulator 6.0. 6. Design and develop a HDL project in structural model to realize the priority encoder.
UNIT IV CMOS CHIP DESIGN 1. Which MOS can pass logic 1 and logic 0 strongly? 2. What is AOI logic function. 3. Give an example circuit for OAI221 gate. 4. What are the methods for programming the PALs? 5. What are all the types of programming PALs? 6. Define PLD. 7. List out the types of ASICs. 8. Draw the basic PLA. 9. Differentiate the PLA from the PAL. 10. What is manual routing? 1. Briefly explain the following terms (i) Design of switches with MOSFETs, (10) (ii) Transmission gate, (3) (iii) Muxs using TG. (3) 2. Draw the physical layout for the following Boolean expression a. y = (a +b) + c + de (8) b. x = (lmnop) + q (r s + rs ) (8) 3. List out the all types of ASICs and explain about any three types of the same with neat diagram. 4. Differenced the PALs from PLAs. And explain the 22V10 standard logic structure with the architecture. 5. Explain the methods used to programme the PALs with neat diagram. 6. What are all the uses of programmable interconnect? Explain it with the neat diagram. 7. Explain the reprogrammable gate array with the architecture and logic blocks.
8. Explain the following terms i. Fault Models, (8) ii. ATPG, (4) iii. Statistical Fault Analysis. (4) 9. List out all the methods of design strategies for test and explain any three methods. 10. (i) Design and Draw the logic circuit using CMOS and trisate switch for the logical relation x 1 x 2 + x 1 x 2. (8) (ii) Explain the design of an inverted 2x1 MUX. (8) 11. (i) Draw and explain the typical architecture of PAL. (8) (ii) Explain the Application Specific Integrated circuits Design Flow with architecture. (8) 12. What does programmable interconnect mean?. Explain the Actal interconnect with example. 1. What is schooling process? UNIT V CMOS TESTING 2. What are all the major classifications of Testing? 3. Draw the SC mode. 4. What is parallel simulation? 5. What is fault sampling? 6. What is meant by Ad-hoc testing? 7. Define ATPG. 8. Give the expression of IDDQ. 9. Define SFA. 10. Differentiate the System level g from the Chip level testing. 1. Explain the following terms (I) Fault Models, (II) ATPG, (4) (III) Statistical Fault Analysis. (4) (8)
2. List out all the methods of design strategies for test and explain any three methods. 3. With the help of IEEE1149 BSA and TAPA explain the system level test technique. 4. (i) How do you find IDDQ?. Explain the same. (8) (ii) Draw and explain the Data path test scheme for chip level test methods. (8) 5. Write short notes on need for CMOS testing. *****ALL THE BEST******