14 12 10 8 6 Fujitsu VP2000 IBM 3090S Pulsar 4 IBM 3090 IBM RY6 CDC Cyber 205 IBM 4381 IBM RY4 2 IBM 3081 Apache Fujitsu M380 IBM 370 Merced IBM 360 IBM 3033 Vacuum Pentium II(DSIP) 0 1950 1960 1970 1980 1990 2000 2010 NTT Fujitsu M-780 IBM RY5 Jayhawk(dual) IBM RY7 Prescott T-Rex Mckinley Squadrons IBM GP Pentium 4 10 9 8 7 6 5 4 3 2 1 Radio Receive for Mesh Maintenance 2-6 ma Typical Current Draw 1 sec Heartbeat 30 beats per sample Sampling and Radio Transmission 9-15 ma Low Power Sleep 0.030-0.050 ma Heartbeat 1-2 ma 0 200 220 240 260 280 300 Time (seconds) Digital Integrated Circuits EECS 312 http://ziyang.eecs.umich.edu/ dickrp/eecs312/ Teacher: Robert Dick Office: 2417-G EECS Email: dickrp@eecs.umich.edu Phone: 734 763 3329 Cellphone: 847 530 1824 GSI: Email: Myung-Chul Kim mckima@umich.edu HW engineers SW engineers Current (ma) IBM ES9000 Bipolar CMOS Power density (Watts/cm 2 ) Year of announcement IBM Z9
Review Design a non-trivial logic gate. What happens to inverter delay as the driving MOSFET widths are increased? What happens to inverter delay as the driven MOSFET widths are increased? What impact does non-instantaneous rise/fall time have on the propagation delay for the subsequent logic stage? 2 Robert Dick Digital Integrated Circuits
Lab 3 Input inverters. Implications of sizing on energy consumption. Derive and explain. 3 Robert Dick Digital Integrated Circuits
Short talks Speakers and topics 1 Katherine, Olga, and Matt: Atomic layer deposition. 2 Michael and Heesung: Impact of materials on devices and circuits. 3 Haishan and Guanyu: Optical interconnect. 4 Ike and Dan: ALU design alternatives. 5 Tyler and Megan: Subthreshold circuit applications. 6 Sui Yu, Zhenghong, and Wang Yi: FinFETs. First talk: 4 November, Thursday. Order? 4 Robert Dick Digital Integrated Circuits
Lecture plan 1. 2. 5 Robert Dick Digital Integrated Circuits
Dependence of delay on width (R) Fix R L C L and vary W. Eventually, self-loading dominates. 6 Robert Dick Digital Integrated Circuits
Inverter chain delay optimization Given Size (width) of first inverter in chain, Driven load, Transistors are minimal length, and W p /W n = 2 approximately balances t phl and t plh. Find Optimal number of inverters in chain and Optimal size (width) of each inverter to minimize chain delay. 7 Robert Dick Digital Integrated Circuits
Intuition Given two inverters (first fixed) and a large load (C L ), how should the second be sized to minimize delay? C G2 = C G1 (minimal)? C G2 > C L? C G2 = C L? Some other setting? Why? 8 Robert Dick Digital Integrated Circuits
Derivation I Let W = W n = W p /2 R = R p = R n T phl = T plh = 0.69RC L C i = 3 W i+1 W unit C unit t p = kr(c int + C L ) = krc int + krc L 9 Robert Dick Digital Integrated Circuits
Derivation II Consider the impact of scaling factor S. ( R t p = 0.69 S SC int t p0 : Intrinsic delay. ( 1 + C L t p = 0.69RC int ( 1 + C L t p = t p0 ( 1 + C L SC int Scaling doesn t impact intrinsic delay. Scaling does impact total delay. t p t p0 as S. Diminishing returns with increasing S. ) SC int SC int ) )) 10 Robert Dick Digital Integrated Circuits
Consider chain of inverters I Given that t p,chain = t p1 + t p2 + + t pn ( t pi RC 1 + C ) g,i+1 γc g,i N t p,chain = i=1 t p,chain = t p0 C g,n+1 = C L t pi N i=1 ( 1 + C ) g,i+1 γc g,i 11 Robert Dick Digital Integrated Circuits
Consider chain of inverters II and γ = C int C g 1 (technology-dependent constant). 12 Robert Dick Digital Integrated Circuits
Sketch of derivation For each i, find σt p,chain/σc g,i. Solve for σt p,chain/σc g,i = 0, i=1 N. Result is C g,i+1 C g,i = C g,i C g,i 1. Each stage size geometric mean of previous and next: C g,i = C g,i 1 C g,i+1. Constant factor relates sizing of all adjacent gate pairs. Each stage has same delay. 13 Robert Dick Digital Integrated Circuits
Sizing for optimal inverter chain delay N Optimal stage-wise sizing factor: CL C g,1. Minimum path delay: t p,chain = Nt p0 (1 + N CL C g,1 /γ ) 14 Robert Dick Digital Integrated Circuits
Example of inverter sizing Given C L = 16C 1. N = 4. Per-stage scaling factor: 4 16C 1 /C 1 = 2 15 Robert Dick Digital Integrated Circuits
Optimizing N I Let Φ = C L C g,1 t p,chain = Nt p0 (1 + t p,chain d dn = γ + N Φ ) N Φ γ N Φ ln (Φ) N 16 Robert Dick Digital Integrated Circuits
Optimizing N II Set this to zero. Let φ = N Φ 0 = γ + φ φ ln ( φ N) N 0 = γ φ + 1 ln ( φ N) 0 = γ φ N + 1 N ln (φ) N 0 = γ + 1 ln (φ) φ ln (φ) = γ φ + 1 φ = e γ/φ+1 17 Robert Dick Digital Integrated Circuits
Optimizing N III Hard to deal with this for γ 0. Consider implications for γ = 0. φ = e 18 Robert Dick Digital Integrated Circuits
Optimal stage sizing factor Optimal tapering factor for γ = 0: e 2.7. 3.6 for γ = 1. 19 Robert Dick Digital Integrated Circuits
t p,chain (Φ) Φ Unbuffered N = 2 Optimal N 10 11 8.3 8.3 100 101 22 16.5 1,000 1,001 65 24.8 10,000 10,001 202 33.1 20 Robert Dick Digital Integrated Circuits
Buffering example 21 Robert Dick Digital Integrated Circuits
Upcoming topics Interconnect. Alternative logic design styles. 22 Robert Dick Digital Integrated Circuits
Lecture plan 1. 2. 23 Robert Dick Digital Integrated Circuits
assignment 2 November, Tuesday: Rest of Lab 3. 2 November, Tuesday: Read Sections 4.4.1 4.4.4 and 5.4.3 in J. Rabaey, A. Chandrakasan, and B. Nikolic. Digital Integrated Circuits: A Design Perspective. Prentice-Hall, second edition, 2003. Don t put off the reading or you might be overloaded when more homework problems are assigned. 4 November, Thursday: First short talk. 24 Robert Dick Digital Integrated Circuits