Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Inverter Revised from Digital Integrated Circuits, Jan M. Rabaey el, 2003
Propagation Delay
CMOS Inverter Propagation Delay V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD 0.5 0.36 V in = V DD R on C L t
MOS transistor model for simulation G C GS C GD S D C SB C GB C DB B
Computing the Capacitances Consider each capacitor individually is almost impossible for manual analysis. What capacitors count in CL? V DD V DD M2 C db2 C g4 M4 V in C gd12 V out V out2 M1 C db1 C w C g3 M3 Interconnect Fanout Simplified Model V in V out C L
Computing the Capacitances NMOS and PMOS transistor are either in cutoff or saturation mode during at least the first half (50%) of the output transient. So, the only contributions to Cgd are the overlap capacitance, since channel capacitance occurs between either Gate-Body for transistors in cutoff region or Gate- Source for transistors in saturation region.
The Miller Effect The lumped capacitor model requires the floating Cgd1 capacitor be replaced by a capacitor to GND using Miller effect. V C gd1 V out V out V V in V 2C gd1 M1 V V in M1 A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value.
The Miller Effect Consider the situation that an impedance is connected between input and output of an amplifier The same current flows from (out) the top input terminal if an impedance Z in, Miller is connected across the input terminals The same current flows to (in) the top output terminal if an impedance Z out, Miller is connected across the output terminal This is know as Miller Effect Two important notes to apply Miller Effect: There should be a common terminal for input and output The gain in the Miller Effect is the gain after connecting feedback impedance Z f Graphs from Prentice Hall
Computing the Capacitances The capacitance between drain and bulk, Cdb1 and Cdb2, are due to the reverse-biased pnjunction. Such a capacitor is, unfortunately, quite nonlinear and depends heavily on the applied voltage. In Chapter 3 we replaced the nonlinear capacitor by a linear one with the same change in charge for the voltage range of interest. A multiplication factor, Keq, is introduced to relate the linearized capacitor to the value of the junction capacitance under zero-bias conditions (usually in the range of 0.6 to 0.9).
Junction Capacitance
Linearizing the Junction Capacitance Replace non-linear capacitance by large-signal equivalent linear capacitance which displaces equal charge over voltage swing of interest
9λ/2λ PMOS V DD ADp=45 λ 2 PDp=19 λ In Polysilicon NMOS 3λ/2λ Out Metal1 GND ADn=19 λ 2 PDn=15 λ
Junction Capacitance Ls (from Ch. 3) Channel-stop implant N A Side wall W Source N D Bottom x j Side wall Channel L S Substrate N A Junction capacitance per unit length No channel side Junction capacitance per unit area
Computation of all capacitors Intrinsic extrinsic Cdb will be slightly different (the pn junction reverse bias in L-to-H and H-to-L, why? voltage range)
Transient Response Cgd directly couples the steep input change before the circuit can even start to react to the changes at input (potential forward bias the pn junction) 3 2.5? V out (V) 2 1.5 1 t phl t plh t p = 0.69 C L (R eqn +R eqp )/2 0.5 0-0.5 0 0.5 1 1.5 2 2.5 t (sec) x 10-10
Low-to-High and High-to-Low delay It is desired to have identical propagation delays for both rising and falling inputs. Equal delay requires equal equivalent onresistance, thus equal current IDAST (neglecting the channel length modulation) This demands almost the same requirements for a Vm at VDD/2. Why?
Requirements for equal delay I I I DSAT Dn Dp k k k ' n ' p ' W L W ( ) L W ( ) L ( V n p V V DD DSATn DSATp V T ( V ( V ) V DD DD DSAT V V V Tn Tp 2 DSAT 2 V ) V ) 2 2 DSATn DSATp Assume V then k k ' p ' n V V DD DSATp DSATn V ( W ( W Tp / L) / L) V p n DSATp k k p n / 2 V V DSATp DSATn 1 This is exactly the formerly defined parameter r (last lecture)
Design for delay performance Keep capacitances small careful layout, e.g. to keep drain diffusion as small as possible Increase transistor sizes watch out for self-loading! When intrinsic capacitance starts to dominate the extrinsic ones Increase VDD (????)
Delay as a function of V DD 5.5 5 For fixed (W/L) t p (normalized) 4.5 4 3.5 3 2.5 2 1.5 Recall a range of low voltage is able to give even better voltage transfer characteristic 1 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4 V DD (V)
Device Sizing 3.8 x 10-11 3.6 (for fixed load and VDD) t p (sec) 3.4 3.2 3 2.8 2.6 2.4 2.2 Self-loading effect: Intrinsic capacitances dominate 2 2 4 6 8 10 12 14 W/L S
NMOS/PMOS ratio 5 x 10-11 4.5 tplh tphl t p (sec) 4 (Average) tp b= W p /W n Lp=L n 3.5 3 1 1.5 2 2.5 3 3.5 4 4.5 5 b Widening PMOS improves the L-H delay by increasing the charge current, but it also degrades the H-L by giving a larger parasitic capacitance. Considering average is more meaningful!!
Delay Definitions
Impact of Rise Time on Delay 0.35 0.3 t phl (nsec) 0.25 0.2 0.15 0 0.2 0.4 0.6 t rise (nsec) 0.8 1
Custom design process: An inverter design example
1. Schematic design
2. Layout design
Step 1: define Nwell (for PMOS)
Step 2: define pselect (for PMOS location)
Step 3: define active region (for PMOS)
Step 4: define poly (gate for PMOS)
Step 5: define contacts (for PMOS)
Step 6: define Vdd and connect source (of PMOS) to it
Step 7: make at least one Nwell contact
Step 8: create NMOS (repeat similar steps before except you do not need make Nwell)
step9: make input and output connections
2. DRC (Design Rule Check)
Correct error if there is any
After correction
3. LVS (Layout versus Schematic)
4. Extract Layout parasitics and post-layout simulation
CMOS Inverter N Well V DD V DD PMOS 2l PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND
Two Inverters Layout preference: Share power and ground Abut cells V DD Connect in Metal
Impact of Process Variations (DFM) 2.5 V out (V) 2 1.5 1 Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS 0.5 0 0 0.5 1 1.5 2 2.5 V in (V)
Inverter Sizing for delay
Inverter with Load W means the size is increased by a factor of W with respect to the minimum size 3W Delay W C int C L Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = Delay (Internal) + Delay (Load) = krw Cint(1+ CL /Cint)
Delay as function of size Delay = kr W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) RW = R unit / W ; C int = W C unit t p t (1 C /( WC p0 L unit )) t p0 = 0.69R unit C unit Intrinsic delay is fixed and independent of sizew Making W large yields better performance gain, eliminating the impact of external load and reducing the delay to intrinsic only. But smaller gain at penalty of silicon area if W is too large!
Delay Formula Delay ~ R W C int C L t p kr W C int 1 C / C t 1 f / L int p0 C int = C gin with 1 for modern technology (see page199 in book or Slid 14 for an example) Cgin : input gate capacitance C L = f C gin - effective fanout This formula maps the intrinsic capacitor and load capacitor as functions of a common capacitor, which is the gate capacitance of the minimum-size inverter
Single inverter versus inverter chain Gate sizing for an isolated gate is not really meaningful. Realistic chips always have a long chain of gates. So, a more relevant and realistic problem is to determine the optimal sizing for a chain of gates.
Inverter Chain In Out C L If C L is given: - How many stages are needed to minimize the delay? - How to size the inverters?
Apply to Inverter Chain (fixed N stages) Unit size (minimum size) inverter In Size? Size? Out 1 2 N C L t p = t p1 + t p2 + + t pn t t pj p ~ R unit C unit 1 C gin, j1 C gin, j C 1 C N N gin j t p j t, 1, p0, C gin, N 1 j1 i1 gin, j C L
Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin,2 C gin,n Minimize the delay, find N - 1 partial derivatives equated to 0 Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 Size of each stage is the geometric mean of two neighbors C gin, j gin, j1 gin, j1 - each stage has the same effective fanout - each stage has the same delay C C
Optimum Delay for fixed N stages When each stage is sized by f and has same effective fanout f: f N F C Effective fanout of each stage: L / Cgin,1 effective fanout of the overall circuit Minimum path delay t p N j1 t f N F C gin, j1 1 Nt p0(1 C gin j N N p, j t p0 F / i1, )
Example In C 1 1 f f 2 Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: f 3 8 2
Optimum Number of Stages For a given load C L and given input capacitance C in Find optimal sizing f t p C Nt L p0 t f t ln 1/ N p0 F / 1 p F C t p0 in ln f F N C ln in f with F 1 2 ln f N f ln f f ln ln F f 0 ln f For = 0, f = e, N = lnf f exp 1 f
Optimum Effective Fanout f Optimum f for given process defined by f 1 f exp f opt = 3.6 for =1
Impact of introducing buffers t p N Nt 1 F / f opt = 4 p0
Buffer Design N f t p 1 64 1 64 65 1 8 64 2 8 18 1 4 16 64 3 4 15 1 2.8 8 22.6 64 4 2.8 15.3
Intel Itanium Microprocessor 9-1 Mux 5-1 Mux a CARRYGEN g64 node1 ck1 SUMSEL REG sum sumb to Cache 9-1 Mux 2-1 Mux b SUMGEN + LU s0 s1 LU : Logical Unit 1000um Itanium has 6 integer execution units like this 58