ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

Similar documents
ECE 342 Electronic Circuits. 3. MOS Transistors

ECE 546 Lecture 10 MOS Transistors

MOS Transistor Properties Review

ECE 497 JS Lecture - 12 Device Technologies

Lecture 12: MOSFET Devices

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

Chapter 4 Field-Effect Transistors

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

Fig. 1 CMOS Transistor Circuits (a) Inverter Out = NOT In, (b) NOR-gate C = NOT (A or B)

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

Integrated Circuits & Systems

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

Lecture 11: J-FET and MOSFET

Practice 3: Semiconductors

Field-Effect (FET) transistors

ECE 342 Electronic Circuits. Lecture 34 CMOS Logic

6.012 Electronic Devices and Circuits Spring 2005

MOSFET: Introduction

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Lecture 4: CMOS Transistor Theory

MOS Transistor I-V Characteristics and Parasitics

Introduction and Background

EE105 - Fall 2005 Microelectronic Devices and Circuits

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

Lecture 3: CMOS Transistor Theory

MOSFET Physics: The Long Channel Approximation

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE 230 Lecture 31. THE MOS TRANSISTOR Model Simplifcations THE Bipolar Junction TRANSISTOR

MOS Transistor Theory

The Devices: MOS Transistors

! PN Junction. ! MOS Transistor Topology. ! Threshold. ! Operating Regions. " Resistive. " Saturation. " Subthreshold (next class)

Lecture 12: MOS Capacitors, transistors. Context

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Lecture 12 Digital Circuits (II) MOS INVERTER CIRCUITS

CMOS INVERTER. Last Lecture. Metrics for qualifying digital circuits. »Cost» Reliability» Speed (delay)»performance

Microelectronics Part 1: Main CMOS circuits design rules

ECE 342 Solid State Devices & Circuits 4. CMOS

Chapter 6: Field-Effect Transistors

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

3. Design a stick diagram for the PMOS logic shown below [16] Y = (A + B).C. 4. Design a layout diagram for the CMOS logic shown below [16]

EECS130 Integrated Circuit Devices

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

ECE315 / ECE515 Lecture-2 Date:

FIELD-EFFECT TRANSISTORS

MOS Capacitors ECE 2204

Device Models (PN Diode, MOSFET )

EE 560 MOS TRANSISTOR THEORY

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

Charge Storage in the MOS Structure. The Inverted MOS Capacitor (V GB > V Tn )

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

MOS Transistor Theory

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

The Devices. Jan M. Rabaey

ECE 415/515 ANALOG INTEGRATED CIRCUIT DESIGN

EE 230 Lecture 33. Nonlinear Circuits and Nonlinear Devices. Diode BJT MOSFET

Device Models (PN Diode, MOSFET )

Operation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

Section 12: Intro to Devices

Figure 1: MOSFET symbols.

Lecture 28 Field-Effect Transistors

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

DC and Transient Responses (i.e. delay) (some comments on power too!)

CMPEN 411 VLSI Digital Circuits. Lecture 04: CMOS Inverter (static view)

Quantitative MOSFET. Step 1. Connect the MOS capacitor results for the electron charge in the inversion layer Q N to the drain current.

Semiconductor Physics fall 2012 problems

EE105 - Fall 2006 Microelectronic Devices and Circuits. Some Administrative Issues

ECE-305: Fall 2017 MOS Capacitors and Transistors

Lecture 210 Physical Aspects of ICs (12/15/01) Page 210-1

Lecture 04 Review of MOSFET

The Physical Structure (NMOS)

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

ELEC 3908, Physical Electronics, Lecture 26. MOSFET Small Signal Modelling

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOS Capacitor with External Bias

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

Extensive reading materials on reserve, including

ENGR890 Digital VLSI Design Fall Lecture 4: CMOS Inverter (static view)

EE 434 Lecture 33. Logic Design

Lecture 11: MOS Transistor

CMOS Inverter (static view)

GEORGIA INSTITUTE OF TECHNOLOGY School of Electrical and Computer Engineering

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

Digital Integrated Circuits

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

Lecture 12 Circuits numériques (II)

Content. MIS Capacitor. Accumulation Depletion Inversion MOS CAPACITOR. A Cantoni Digital Switching

ECE-305: Spring 2016 MOSFET IV

ELEN0037 Microelectronic IC Design. Prof. Dr. Michael Kraft

Chapter 13 Small-Signal Modeling and Linear Amplification

EE 330 Lecture 16. Devices in Semiconductor Processes. MOS Transistors

Transcription:

ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1

NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to 100 m, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm. 2

NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type substrate MOS devices are smaller than BJTs MOS devices consume less power than BJTs 3

NMOS Transistor - Layout Top iew Cross Section 4

MOS Regions of Operation Resistive Triode DS T small Nonlinear T < ( ) DS T Active Saturation T DS T 5

MOS Transistor Operation As G increases from zero Holes in the p substrate are repelled from the gate area leaving negative ions behind A depletion region is created No current flows since no carriers are available As G increases The width of the depletion region and the potential at the oxide-silicon interface also increase When the interface potential reaches a sufficiently positive value, electrons flow in the channel. The transistor is turned on As G rises further The charge in the depletion region remains relatively constant The channel current continues to increase 6

MOS Triode Region - 1 W ID Cox T DS L DS T C ox t ox ox 3.9 o t ox C ox : gate oxide capacitance : electron mobility L: channel length W: channel width T : threshold voltage 7

MOS Triode Region - 1 FET is like a linear resistor with r ds 1 C W L n ox T 8

MOS Triode Region - 2 T DS T Charge distribution is nonuniform across channel Less charge induced in proximity of drain W 1 I C L 2 2 D n ox T DS DS 9

MOS Active (Saturation) Region Saturation occurs at pinch off when DS T DSP T DS T (saturation) W I C 2L 2 D n ox T 10

NMOS Circuit Symbols 11

NMOS Regions of Operation Cut off T I D 0 Triode T DS T W 1 I C L 2 2 D n ox T DS DS Saturation T DS T W I C 2L 2 D n ox T 12

NMOS Drain Current 13

NMOS I Characteristics characteristics for a device with k n (W/L) = 1.0 ma/ 2. 14

MOS Threshold oltage The value of G for which the channel is inverted is called the threshold voltage T (or t ). Characteristics of the threshold voltage Depends on equilibrium potential Controlled by inversion in channel Adjusted by implantation of dopants into the channel Can be positive or negative Influenced by the body effect 15

nmos Device Types Enhancement Mode Normally off & requires positive potential on gate Good at passing low voltages Cannot pass full DD (pinch off) Depletion Mode Normally on (negative threshold voltage) Channel is implanted with positive ions ( T ) Provides inverter with full output swings 16

Types of MOSFETS 17

PMOS Transistor 0 PMOS -100-200 =-1.0-300 -400-500 -600 =-1.0 =-1.5 =-2.0 =-2.5-700 -2.5-2 -1.5-1 -0.5 0 - All polarities are reversed from nmos - v, v DS and t are negative - Current i D enters source and leaves through drain - Hole mobility is lower low transconductance - nmos favored over pmos ds 18

PMOS Regions of Operation Cut off I D : drain current flowing from drain to source TP I D 0 Triode TP DS TP W 1 I C L 2 2 D p ox TP DS DS Saturation TP DS TP W I C 2L 2 D p ox TP 19

Cut off Triode SG TP PMOS Alternative Equations In positive quantities ( SG, DS, TP ) I D 0 SG TP SD SG TP Saturation SG TP SD SG TP W 1 I C L 2 2 D p ox SG TP SD SD W I C 2L 2 D p ox SG TP 20