CSE 140 Midterm 3 version A Tajana Simunic Rosing Spring 2015 Name of the person on your left : Name of the person on your right: 1. 20 points 2. 20 points 3. 20 points 4. 15 points 5. 15 points 6. 10 points Total (100 pts.) Do not start the exam until you are told. Write your name and PID at the top of every page. Write the names of people on your left and right on the first page. Turn off and put away all your electronics. This is a closed book, closed notes. You may only refer to one 8 ½ x 11 page of your handwritten notes. By turning in this exam for grading you are stating that you have followed the UCSD s academic honesty policies. Do not look at anyone else s exam or talk to
anyone but an exam proctor. If you have a question, raise your hand and an exam proctor will come to you. You have 80 minutes to finish the exam. When the time is finished, you must stop writing. Write your answers in the space provided. To get the most partial credit, clearly show all the steps of your work. Full credit may not be given for correct answers with no work shown.
Problem 1 RTL Design Design an 8 bit counter using RTL design method that performs the following functions: 1. When input E = 1, it counts even numbers (0, 2, 4, 6, ) and when E = 0, it counts odd numbers (1, 3, 5, 7,...). There is no need to handle overflow. 2. When input CLR = 1 and E=1, then it clears the output to 00000000 else if CLR=1 and E=0, it sets output to 00000001. If you were initially counting even(odd) numbers, and now want to change the type of counting, the output changes to the nearest greater odd (even) value. For example, If E changes from 1 to 0 when output is 120, the next output will be 121. a. Define all the remaining transitions in this counter s high level state machine.
b. Design the datapath for this RTL design. c. Connect datapath and controller, show all the signals. d. What is the critical path through this design that determines the maximum clock frequency?
Problem 2 Timing Draw the waveforms for the missing signals (X0, X1 and Y), in circuit shown below. T he gates have the following propagation delays (t pd ) : AND: 25ns, NOR: 25ns, XOR: 50ns, CMOS gates (input to output delay): 25ns. The D FF has a propagation delay (t pcq ) = 50ns, ignore setup and hold constraints. C lock cycle time T c is 200ns. Note: Initial values (X0 X1 Y = 100) are drawn in the graph below.
Problem 3 FSM Complete the following for the circuit in figure below: a. Is this a Mealy or a Moore machine? b. In the excitation table, complete the column corresponding to D1. Q1 Q0 A D1 D0 Y 000 1 0 001 0 0 010 0 0 011 1 1 100 1 0 101 0 1 110 0 0 111 1 1 c. Provide equations for X0, X2 and D1
X0 = X2 = D1 = d. Given the excitation table for D0 and Y, provide a circuit implementation for the two blocks Design me #1 and Design me #2. Draw your circuit in the boxes.
Problem 4 Modified ALU Design an ALU that takes two 4 bit numbers A and B as inputs, and generates output Z as follows: lf A and B are odd numbers then Z = A B. lf A and B are even numbers then Z = B A. lf A is an even number and B is an odd number then Z = A + B lf A is an odd number and B is an even number then Z = A B 1 Use at most one adder, a single 2x4 decoder, no more than two MUXs and a minimum number of other gates. Problem 5 Design of a new latch
The following figure has a new latch design. The output Out changes depending on inputs A and B. Please fill in the following excitation table. A(t) B(t) Out(t) Out(t+1) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 What does this new latch do?
Problem 6a Multiple Choice 1. In this figure, if the combinational circuit (CL) is just a wire, which of the following should be greater than the hold time of R1? a. The contamination delay of R1 b. The contamination delay of R2 c. The propagation delay of R1 d. The propagation delay of R2 e. The clock skew 2. What does this circuit represent? a. The sum of a full adder b. The carry out of a full adder c. The C output of a carry lookahead adder ( C = AB + C(A B) ) d. None of the above 3. What is the difference between HLSM and FSM? a. HLSM needs local registers b. Inputs & outputs can have multiple bits in HLSM c. The transitions can have complex conditions in HLSM d. FSM is a subset of HLSM e. All of the Above
Problem 6b True or False 1. Ripple carry adder is always slower than carry lookahead adder. 2. nmos passes 0 better, while pmos passes 1 better. 3. {AND, OR} is a universal gate. 4. In this K map, B D is an essential prime implicant. AB \ CD 0 0 0 1 1 1 1 0 00 1 0 0 1 01 1 1 1 0 11 0 1 1 1 10 1 0 0 1 5. If F(a,b,c) = (a c + ab), then F (a,b,c) = (ab + a c). 6. Mealy FSM usually has more states compared to an equivalent Moore one. 7. Minimum CPU clock frequency is defined with the hold constraint.
This page was intentionally left blank.