University of Pennsylvania Department of Electrical and System Engineering Circuit-Level Modeling, Design, and Optimization for Digital Systems ESE370, Fall 2017 Midterm 2 Monday, November 6 Point values for each problem are denoted in exam. Point breakdown within problems varies. Calculators allowed. No smartphones. Closed book = No text or notes allowed. V dd =1V, V thn = V thp = 250mV, µ n = µ p, R p0 = R n0 = R 0, unless otherwise specified in problem. Unless otherwise noted, inputs driven by R 0 drive with self load 2γC 0. 1 1 model_drive 1 1 A model for the input driver is: Name: Grade: Q1 Q2 Q3 Q4 Total mean: 83, stdev: 14 Answers 1
1. (10 points) Draw a ratioed gate for the function Z = A B + B C. Draw a stick drawing of the layout of your gate. Assume all transistors are minimum sized. For reference, an example of a layout stick drawing for a CMOS inverter is shown below. An represents a contact or via and the dashed line defines the n-well area. 2
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2. (40 points) Size the transistors in the following circuit to minimize switching energy while achieving 30τ worst-case delay. Report final delay and switching energy. Assume γ=0, V dd =1V, V thn = V thp = 300mV, C 0 = 4.5 10 17 F, and velocity saturated operation. Basic cell: Circuit from basic cell (Calculate delay from initial inverters driving circuit to circuit driving final output inverters): 4
(a) What is the delay if all of the transistors have W = 1? Delay 42 τ 10pts The critical path goes from the inputs through A(orB).Pin A.nand2 A.inv.Pout C.nand2 C.nand3 C.inv.Gout. Stage Delay A(orB).Pin R 0 2C 0 = 2τ A.nand2 2R 0 4C 0 = 8τ A.inv.Pout drive C.Pin R 0 2C 0 = 2τ C.nand2 2R 0 4C 0 = 8τ C.nand3 3R 0 2C 0 = 6τ C.inv.Gout drive W=8 R 0 16C 0 = 16τ 5
(b) Size design to achieve the 30τ target while minimizing switching energy: Cell Instance transistor A B C WP1 2 2 2 WP2 2 2 2 WP3 2 2 1 WP4 1 1 1 WP5 1 1 1 WP6 1 1 1 WP7 1 1 2 WN1 2 2 2 WN2 2 2 2 WN3 2 2 1 WN4 1 1 3 WN5 1 1 3 WN6 1 1 3 WN7 1 1 2 (c) Delay for sized design: Delay 30τ Stage Delay A(orB).Pin R 0 4C 0 = 4τ A.nand2 R 0 6C 0 = 6τ A.inv.Pout drive C.Pin R 0 /2 4C 0 = 2τ C.nand2 R 0 6C 0 = 6τ C.nand3 R 0 4C 0 = 4τ C.inv.Gout drive W=8 R 0 /2 16C 0 = 8τ 6
(d) Switching Energy for all 0 s input switches to all 1 s input: Switching Energy 98 2 C 0(V dd ) 2 2.2 10 15 J For this switching case, all transistor gates switch values with the load. 7
3. (30pts) A useful circuit in an analog-to-digital (ADC) converter is a thermometer to binary encoder. The truth table and logic function for a 2-bit ADC are given below, where the 3-bit thermometer code T 3 T 2 T 1 is encoded to a 2-bit binary output B 2 B 1. You can assume only the inputs included in the truth table are possible. All transistors W=L=1. Inputs Outputs T 3 T 2 T 1 B 2 B 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 1 1 Give answers in terms of τ and γ; γ = C diff /C gate. Assume all inputs arrive at the same time and are driven by R 0 drive with 2γC 0 self load. The load on each of the outputs is 4C 0. The 2-input multiplexer used in this problem is given as: 8
(a) Estimate the delay of for a simple implementation of the encoder for a 2-bit ADC using the 2-input pass transistor multiplexer given above. Delay for design: Delay (16 + 10γ)τ Stage Delay Drive S input (7 + 2γ)τ S inv (1 + 2γ)τ drive inv input 2(2 + 2γ)τ Drive B0 (4 + 2γ)τ 9
This can be extended to build an encoder for a 4-bit ADC, where the 15-bit thermometer code T 15 T 14...T 2 T 1 is encoded to a 4-bit binary output B 4 B 3 B 2 B 1. The abbreviated truth table is given here for completeness. You can assume only the inputs included in the truth table are possible. Inputs Outputs T 15 T 14 T 13... T 3 T 2 T 1 B 4 B 3 B 2 B 1 0 0 0... 0 0 0 0 0 0 0 0 0 0... 0 0 1 0 0 0 1 0 0 0... 0 1 1 0 0 1 0 0 0 0... 1 1 1 0 0 1 1............. 0 0 0... 1 1 1 1 1 0 0 0 0 1... 1 1 1 1 1 0 1 0 1 1... 1 1 1 1 1 1 0 1 1 1... 1 1 1 1 1 1 1 (b) Estimate the delay of for the below implementation of the encoder for a 4-bit ADC using the 2-input pass transistor multiplexer given above. 10
Delay for design: Delay (64 + 26γ)τ Stage Delay Drive B4 (2γ + 7 3 + 4)τ T4 to pre-b3 (2γ + 1)τ + (4γ + 4)τ Drive B3 (2γ + 3 3 + 4)τ stage1 out to pre-b2 (2γ + 1)τ + (4γ + 4)τ Drive B2 (2γ + 1 3 + 4)τ stage2 out to pre-b1 (2γ + 1)τ + (4γ + 4)τ Drive B1 (2γ + 4)τ 11
4. (20 pts) Short Answer Questions: Answer the questions briefly. Include diagrams and equations as needed. Be clear in your explanation and handwriting. A What is leakage energy of a CMOS gate? Describe one way to reduce the leakage energy of a CMOS gate. Leakage energy of a CMOS gate is when the gate is in steady state and only one PU or PD network is active at a time. The network that is off is operating in the subthreshold region. One way to reduce the leakage energy is to use gates with a higher threshold voltage, thereby decreasing the subthreshold current for the gates that are off. B What effect does increasing V dd have on delay? Explain your answer. Increasing V DD increases the drive current of the transistors thereby decreasing the delay. τ = CV τ CV τ C I V 2 V C What is an example of a layout Design Rule? Why are the rules necessary? Some design rules are minimum widths, spacings, and overlaps of layers. Also contact and via size rules. The rules are necessary to ensure functional operation of our devices and avoiding accidental shorts or opens in our design. 12
D What is the activity factor of an output? How does it affect energy consumption? The activity factor is the probability of a 0 1 transistion of an output. The activity factor effects switching energy: P dyn = a(c + C SC )V 2 f. E What is the Elmore delay of the special ladder case with N unit wire segments where each segment has R unit and C unit equivalent resistance and capacitance respectively? Draw a picture to explain your calculation. The Elmore delay of the special ladder case is N(N+1) R 2 unit C unit. For N large, N 2 R 2 unitc unit. 13