Fult Modeling EE5375 ADD II Prof. McDonld
Stuck At Fult Models l Modeling of physicl defects (fults) simplify to logicl fult l stuck high or low represents mny physicl defects esy to simulte technology independent l More dvnced models stuck open more representtive of wire defects ridging defects dely defects sutle deep su-micron defects
Fult Detection Test Vector T 0 0 0 definition of detection Z(t) ^ Zf(t) = 1 Vector T detects fult f Expected Output Z(t) = 0 Zf(t) = 1
Fult Detection - Totl Test Vector T 0 0 0 This test vector detects ll shown defects individully. Expected Output Z(t) = 0 Zf(t) = 1
Fult Detection c d Z = (A + B) C + D C Zf= (A + B) C + D 0 = (A + B) C 1 = Z ^ Zf = ((A + B) C + DC) ^ ((A + B) C ) 1 = DC T = { 0011, 0111, 1011, 1111} ll detect f
Fult Sensitiztion l Fult must e ctivted site of fult must opposite of stuck vlue l Fult pth must e sensitized ll other inputs to gtes long pth must e noncontrolling vlues. thus the error is propgted to output nd is mnifest referred to s error or fult-effect propgtion l If no test vector exists to ctivte nd sensitize the fult is undetectle.
Fult Sensitiztion 1 0 1 Fult Sensitiztion Vectors {1010,1110,0110} will sensitize this fult. 0->1 0->1 c 1 d 0 0 0->1 Fult Activtion ny vector XX1X will ctivte the fult
Fult Detectility nd Redundncy l Defect is undetectle if it doesn t chnge circuit function l Undetectle fults re due to redundncy l Redundncy is often useful provides fult tolernce cn e used to void glitching cn e used to crete pulses (self-timed circuits) l Must e hndled with cre during test
Fult detection nd self-timing l Pulse Genertor cretes pulse t rising edge of input pulse width is equl to propgtion dely of inverter l Difficult to test with logicl DC test Output is lwys zero in sttic sense Avoid in logic design
Fult detection nd redundncy circuit A circuit B voting circuit C l Fult Tolernt Circuits use redundncy l Must remove redundncy during test l otherwise possile for 2 circuits to e d nd still pss loss of fult tolernce reliility prolem if d circuits hve shorts nd power
redundncy nd hzrds BC A 00 0 1 0 0 01 1 0 11 10 1 1 0 1 c l l Cn dd redundncy to void sttic hzrds 011 to 111 should sty high ut glitch low without redundncy
Fult Equivlence nd Collpsing l 2(N+1) totl fults per N-input gte l Some fults re equivlent nd indistinguishle ll inputs stuck t 0 output stuck t 1 l Thus totl fults reduce to N+2 for most logicl gtes logicl gtes with controlling vlue (XOR is less reducile) l For Fult Anlysis, only consider the reduced cses
Fult Dominnce l If fult detection is importnt nd not loction (dignosis) then fults cn e further collpsed l Useful for reducing the numer of fults tht re trgeted reduces time for test pttern genertion reduces the numer of ptterns needed to e stored l F domintes G if vectors tht detect G lso detect F Tf Tg
Dominnce Collpsing y x z uncollpsed fults list y x z Equivlence fult collpsing Esy to implement going from output to inputs on complex circuit y x z Dominnce fult collpsing Isn t gurnteed to work with redundnt circuits, ut provides very good collpsing (see check point theorem lter)
Equivlence Collpsing y x z functionl equivlent nd indistinguishle even if ll test vectors re pplied. X Y Z Zf1 Zf2 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 vector proves detectility in oth cses, ut no vector distinguishes etween them.
Dominnce Collpsing y x X Y Z Zf1 Zf2 0 0 1 1 0d 0 1 1 1 0d 1 0 1 0d 0d 1 1 0 0 0 z One fult domintes the other so they cn e collpsed. Doing this mens tht you cn detect them oth ut won t e le to tell them prt unlike equivlence fult collpsing where you cn not distinguish the fults even with ll the vectors. vector proves detectility of oth ut lone cn not distinguish them (dignosis).
Structurl Equivlence l To detect if fults re equivlent, simplify circuit nd compre in oth cses. If the circuit is the sme, you hve structurl equivlence fults cn e functionl equivlent ut not structurlly equivlent c d c d
Structurl Equivlence l To detect if fults re equivlent, simplify circuit nd compre in oth cses. If the circuit is the sme, you hve structurl equivlence fults cn e functionl equivlent ut not structurlly equivlent c d c d
Structurl Equivlence l With reconvergence, some fults re still functionlly equivlent ut not structurl equivlent
Structurl Equivlence l With reconvergence, some fults re still functionlly equivlent ut not structurl equivlent
Three pproches for collpsing l Functionl equivlence requires full simultion t glol level l l prove equivlent y proving for ll vectors output is the sme requires full truth tle nlysis for 32 inputs, need 4G rows only technique tht gurntees minimum fult list Structurl cn e done t locl level esier for fnout of 1 gte output re SE to destintion input for gtes with controlling vlue, s--c is equl to output s--c^i retin one fult s representtive from ech group doesn t collpse completely ut gets low hnging fruit works even if reconvergence exists Checkpointing - y exploiting fult dominnce, only need to detect primry inputs of fn-out free circuits checkpoints of fnout circuits ssuming no redundncy
Structurl Equivlence s s
Structurl Equivlence s s
Structurl Equivlence s s
Structurl Equivlence s s
Structurl Equivlence s reduced to 10 fults s
Brnches stem fults re equivlent to multiple rnch fults however, we only consider single fults Brnches nd stems not equivlent or dominnt so they must e hnded seprtely. 1 1 1 1 1 1 1 0 1 Here is cse of stem fult detectle nd either rnch not detected y test vector 111 Alterntive cse in which one rnch is detected ut stem nd other rnch re not detected.
Circuits fnout free l With fult dominnce, possile to detect ll SSF y only detecting ll fults t PIs c d
Circuits fnout free - proof l If ll fults t input of gte re detected thn with fult equivlence nd dominnce the outputs re detected s well. c d functionl equivlence elimintes s0
Circuits fnout free - proof l If ll fults t input of gte re detected thn with fult equivlence nd dominnce the outputs re detected s well. c d functionl dominnce elimintes s1 in this cse Without fnout, process cn extend to primry output
Irredundnt Circuit l Detect ll SSF, if ll checkpoints re tested lterntive to structurl pproch c reduced to 10 fults like structurl cse efore ut generlly etter (s long s there is no redundncy) cn now use structurl pproch to reduce further c
Exmple from Book (4.8) uncollpsed 40 fults totl (42 if you count PO) Circuit is not fnout free ut it is irrudundnt. f c g j m d e h i k
Exmple from Book (4.8) structurl 40 fults totl (42 if you count PO) Book mentions 24 regulr nd 14 check point fults? f c g j m d e h i k
Exmple from Book (4.8) structurl 40 fults totl (42 if you count PO) f c g j m d e h i k
Exmple from Book (4.8) structurl 40 fults totl (42 if you count PO) f c g j m d e h i k
Exmple from Book (4.8) structurl 40 fults totl (42 if you count PO). f c g j m d e h i k
Exmple from Book (4.8) structurl 40 fults totl (42 if you count PO) reduced to 14 f c g j m d e h i k
Exmple from Book (4.8) Checkpoint 14 fults totl 10 t PIs nd 4 t rnch checkpoints f c g j m d e h i k
Exmple from Book (4.8) minimum fults 10 fults totl fter reducing checkpoint fults with further nlysis functionl equivlent functionl dominnce f functionl equivlent c g j m functionl equivlent h functionl dominnce i d e functionl equivlent k
Automtic Test Pttern Genertion l Automtic Test Pttern Genertion (ATPG) determine list of fults required to e detected generte list of test vectors tht detect ll or percentge l Mny lgorithms ctivte nd then sensitize defects rndom genertion nd then determine wht is detected hyrid, multi pss pproch l Limited to comintionl logic scn testing reduces sequentil circuits to comintionl ATPG genertes input vectors nd expect vectors