ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna
Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cut-off " Depletion " Inversion " Threshold Voltage 2
CMOS Layers! Standard n-well Process " Active (Diffusion) (Drain/Source regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMOS bulk region) " n Select (used with active to create n-type diffusion) " p Select (used with active to create p-type diffusion) 3
Example: NAND Gate (Horizontal) 4
Standard Cells! Lay out gates so that heights match " Rows of adjacent cells " Standardized sizes! Motivation: automated place and route " EDA tools convert HDL to layout 5
Standard Cell Area inv nand3 All cells uniform height Cell area Width of channel determined by routing 6
Standard Cell Layout Example http://www.laytools.com/images/standardcells.jpg 7
Standard Cell Layout Example http://www.laytools.com/images/standardcells.jpg 8
CMOS Layers! Standard n-well Process " Active (Diffusion) (Drain/Source regions) " Polysilicon (Gate Terminals) " Metal 1, Metal 2, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal 2 to metal 1) " nwell (PMOS bulk region) " n Select (used with active to create n-type diffusion) " p Select (used with active to create p-type diffusion) 9
CMOS Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias 10
Interconnect Cross Section ITRS 2007 11
Local Interconnect ITRS 2007 12
CMOS Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs 13
CMOS Poly-Poly Capacitors W L 14
Resistors 15
CMOS Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! Devices " Multiple thresholds (High and low V t ) " High-k gate dielectrics " FinFET 16
High-K dielectric SiO 2 Dielectric Poly gate MOSFET High-K Dielectric Metal gate MOSFET Dielectric constant=3.9 Dielectric constant=20 17
High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P133 168, 2002 18
22nm 3D FinFET Transistor High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf 19
CMOS Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! Devices " Multiple thresholds (High and low V t ) " High-k gate dielectrics " FinFET! Silicon on insulator process (SOI) " Fabricate on insulator for high speed/low leakage 20
SOI Technology! SOI-based devices differ from conventional silicon built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide of sapphire 21
Semiconductor Physics 22
Silicon Lattice! Cartoon two-dimensional view 23
Energy State View Energy Valance Band all states filled 24
Energy State View Conduction Band all states empty Energy Valance Band all states filled 25
Energy State View Conduction Band all states empty Energy Band Gap Valance Band all states filled 26
Band Gap and Conduction Insulator E c Metal E c E v 8ev OR E v E v E c Semiconductor 1.1ev E c E v 27
Doping! Add impurities to Silicon Lattice " Replace a Si atom at a lattice site with another! E.g. add a Group 15 element " E.g. P (Phosphorus) 28
Doping with P (n-type)! End up with extra electrons " Donor electrons! Not tightly bound to atom " Low energy to displace " Easy for these electrons to move 29
Doped Band Gaps! Addition of donor electrons makes more metallic " Easier to conduct 0.045ev 1.1ev Semiconductor E c E D E v 30
Doping with B (p-type)! End up with electron vacancies -- Holes " Acceptor electron sites! Easy for electrons to shift into these sites " Low energy to displace " Easy for the electrons to move " Movement of an electron best viewed as movement of hole 31
Doped Band Gaps! Addition of acceptor sites makes more metallic " Easier to conduct Semiconductor E c 0.045ev 1.1ev E A E v 32
MOSFETs! Donor doping " Excess electrons " Negative or N-type material " NFET (active regions)! Acceptor doping " Excess holes " Positive or P-type material " PFET (active regions) 33
MOS Physics - nmos MOS capacitor
Two-Terminal MOS Structure 2 GATE Si Oxide interface n+ n+ 35
Two-Terminal MOS Structure 2 GATE L W Si Oxide interface n+ n+ 36
Two-Terminal MOS Structure 2 GATE Si Oxide interface n+ n+! Equilibrium (Mass action law) " Product of hole and electron densities is constant at equilibrium " n 0 p 0 =n i 2 n i =1.45x10 10 cm -3 37
Two-Terminal MOS Structure 2 GATE Si Oxide interface n+ n+! n 0 p 0 =n i 2 n i =1.45x10 10 cm -3! Let (p-type) substrate be uniformly doped with concentration N A 38
Two-Terminal MOS Structure 2 GATE Si Oxide interface n+ n+! n 0 p 0 =n i 2 n i =1.45x10 10 cm -3! Let (p-type) substrate be uniformly doped with concentration N A " p p0 =N A # n p0 =n i2 /N A 39
Two-Terminal MOS Structure 2 GATE Si Oxide interface n+ n+! n 0 p 0 =n i 2 n i =1.45x10 10 cm -3! Let (p-type) substrate be uniformly doped with concentration N A " p p0 =N A # n p0 =n i2 /N A If N-type doped substrate: n n0 =N D # p n0 =n i2 /N D 40
Semiconductor Band Gap Free space Electron affinity of silicon Conduction band E i = E C E V 2 Intrinsic Fermi level Fermi level Valence band 41
P-type Doped Semiconductor Band Gap Free space Conduction band Intrinsic Fermi level Fermi level Valence band! qφ and E are in units of energy = electron-volts (ev); where 1 ev = 1.6 x 10-19 J.! 1 ev corresponds to energy acquired by a free electron that is accelerated by an electric potential of one volt.! Φ and V corresponds to potential difference in volts. 42
P-type Doped Semiconductor Band Gap Free space Conduction band Intrinsic Fermi level Fermi level Valence band Fermi potential: Φ Fp = E F E i q Φ Fp = kt q ln n i N A 43
MOS Capacitor Energy Bands 44
MOS System Band Diagram! Three components put in physical contact " Fermi levels must line up 45
Band Diagram Demo http://demonstrations.wolfram.com/appliedvoltageonanidealmoscapacitor/ 46
MOS Capacitor with External Bias! Three Regions of Operation (w/ V B =0): " Accumulation Region V G < 0 " Depletion Region V G > 0, small " Inversion Region V G V T, large 47
Accumulation Region! Holes " Accumulate at the silicon-oxide interface! Electrons " Near surface repelled into silicon bulk! Interface accumulated with mobile carriers (holes) 48
Accumulation Region Energy Bands Accumulation V G < 0 Si surface Band bending due to V G < 0 E Fm qv G = E Fp E Fm qφ S qφ(x) qφ Fp E Fp 0 x 49
Depletion Region! Holes " Near silicon-oxide interface repelled into silicon bulk! Electrons " Left behind at interface t ox - - - - -! Interface depleted of mobile carriers (holes) 50
Depletion Region Energy Bands Depletion V G > 0 (small) Si surface Band bending due to V G > 0 qφ(x) qv G = E Fp E Fm qφ S qφ Fp E Fp E Fm x d 0 x 51
Depletion Region Φ Fp = Φ F = kt q ln n i N A < 0 t ox 26 mv at room T - - - - Φ Φ S Φ Fp Surface potential Bulk potential 52
Depletion Region Φ Fp = Φ F = kt q ln n i N A < 0 t ox 26 mv at room T - - - - Φ Φ S Φ Fp Surface potential Bulk potential dq = qn A dx dφ = x dq ε Si Mobile hole charge density (per unit area) in thin layer below surface Potential required to displace dq by distance x dφ = q N A x ε Si dx 53
Depletion Region t ox Φ Fp = Φ F = kt q ln n i N A < 0 26 mv at room T - - - - Φ Φ S Φ Fp Surface potential Bulk potential Φ Fp dφ = Φ S x d 0 q N A x ε Si dx = q N 2 A x d 2ε Si = Φ Fp Φ S x d = 2ε Si Φ Fp Φ S q N A 54
Depletion Region Φ Fp = Φ F = kt q ln n i N A < 0 t ox 26 mv at room T - - - - Φ Φ S Φ Fp Surface potential Bulk potential Q = qn A x d Q = qn A 2ε Si Φ Fp Φ S = 2qN A ε Si Φ Fp Φ S q N A 55
Inversion Region! Holes " Repelled deeper into silicon bulk! Electrons " Attracted to silicon-oxide interface t ox V G V T - -- - - - -! Inversion condition " When Φ S = Φ F " Density of mobile electrons at surface = density of mobile carriers in bulk 56
Inversion Region Energy Bands Inversion V G V T0 > 0 Si surface qφ Fp qv G = E Fp E Fm qφ S E Fp E Fm 0 x dm x 57
Inversion Region! Inversion condition " When Φ S = Φ F " Density of mobile electrons at surface = density of mobile carriers in bulk t ox V G V T - -- - - - - 58
Inversion Region! Inversion condition " When Φ S = Φ F " Density of mobile electrons at surface = density of mobile carriers in bulk t ox V G V T - -- - - - - x dm = 2ε Si Φ Fp Φ S q N A = 2ε Si 2Φ Fp q N A Q = 2qN A ε Si Φ Fp Φ S = 2qN A ε Si 2Φ Fp 59
Band Diagram Demo http://demonstrations.wolfram.com/appliedvoltageonanidealmoscapacitor/ 60
MOS Capacitor with External Bias! Three Regions of Operation: " Accumulation Region V G < 0 (Cut-off) " Depletion Region V G > 0, small (Subthreshold) " Inversion Region V G V T, large (Above Threshold) V G V T - - - - - - - - - - Cut-off/Subthreshold Above threshold 61
2-terminal MOS Cap # 3-terminal nmos VS V G V D - - - - - - - - - depletion region - - - - 62
nmos = MOS cap + source/drain V SB = 0 V S V G V D - - - - - - - - - - - 63
Threshold Voltage! For V SB =0, the threshold voltage is denoted as V T0 or V T0n,p " Φ GC : Work function difference between gate and channel " Metal Gate: Φ GC =Φ F (substrate) Φ M " Poly Gate: Φ GC =Φ F (substrate) Φ F (gate) " Q OX : Fixed positive charge density at interface " Q OX = qn OX C/cm 2 " C OX : Gate oxide capacitance per unit area " C OX =ε OX /t ox " Φ GC : Bulk fermi potential V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox " Q B0 : Depletion region charge density at inversion " Q B0 = 2qN A ε Si 2Φ F 64
Threshold Voltage! For V SB =0, the threshold voltage is denoted as V T0 or V T0n,p " Φ GC : Work function difference between gate and channel " Metal Gate: Φ GC =Φ F (substrate) Φ M " Poly Gate: Φ GC =Φ F (substrate) Φ F (gate) " Q OX : Fixed positive charge density at interface " Q OX = qn OX C/cm 2 " C OX : Gate oxide capacitance per unit area " C OX =ε OX /t ox " Φ GC : Bulk fermi potential V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox " Q B0 : Depletion region charge density at inversion " Q B0 = 2qN A ε Si 2Φ F 65
Threshold Voltage for V SB = 0 for V SB!= 0 V T =V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox V T = Φ GC Q ox C ox 2Φ F Q B C ox V T = Φ GC Q ox C ox 2Φ F Q B0 C ox Q B Q B0 C ox V T =V T 0 Q B Q B0 C ox 66
Threshold Voltage for V SB = 0 for V SB!= 0 V T =V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox V T = Φ GC Q ox C ox 2Φ F Q B C ox V T = Φ GC Q ox C ox 2Φ F Q B0 C ox Q B Q B0 C ox γ V T =V T 0 Q B Q B0 C ox Q = 2qN A ε Si Φ F Φ S Q Q B B0 = 2qN Aε Si ( 2Φ F V SB 2Φ ) F C ox C ox V T = V T 0 +γ ( 2Φ F V SB 2Φ ) F 67
Threshold Voltage for V SB = 0 for V SB!= 0 V T =V T 0 = Φ GC Q ox C ox 2Φ F Q B0 C ox V T = Φ GC Q ox C ox 2Φ F Q B C ox V T = Φ GC Q ox C ox 2Φ F Q B0 C ox Q B Q B0 C ox V T =V T 0 Q B Q B0 C ox Q = 2qN A ε Si Φ F Φ S Q Q B B0 = 2qN Aε Si ( 2Φ F V SB 2Φ ) F C ox C ox V T = V T 0 +γ ( 2Φ F V SB 2Φ ) F Examples 3.2 and 3.3 in text (pp 105-107) 68
Threshold Voltage! Be careful with signs! N-channel P-channel ϕ F negative positive Q B0,Q B negative positive ϒ positive negative V SB 0 0 V T0 positive (V T0n ) negative (V T0p ) 69
Threshold Voltage 70
Threshold Voltage V SB 71
Big Idea! 3 operating regions " Cut-off " Depletion " Inversion! Threshold voltage " Defined by onset of inversion " Doping and V SB change V T 72
Admin! HW 2 due Friday, 2/1 " Submit in canvas 73