Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. SOIC D SUFFIX CASE 5A HC86G AWLYWW Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with JEDEC Standard No. A Requirements ESD Performance: HBM 2000 ; Machine Model 200 Chip Complexity: 56 FETs or Equivalent Gates These are Pb Free Devices TSSOP DT SUFFIX CASE 948G HC86 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W = Work Week G or = Pb Free Package HC 86 ALYW (Note: Microdot may be in either location) Semiconductor Components Industries, LLC, 200 March, 200 Rev. Publication Order Number: /D
PIN ASSIGNMENT LOGIC DIAGRAM A B 2 3 B4 A B 2 3 Y Y A2 B2 3 4 5 2 0 A4 Y4 B3 A2 B2 4 5 6 Y2 Y2 GND 6 9 8 A3 Y3 A3 B3 9 0 8 Y3 FUNCTION TABLE Inputs A B L L L H H L H H Output Y L H H L 2 A4 3 B4 Y = A B = AB + AB PIN = PIN = GND Y4 2
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter alue Unit DC Supply (Referenced to GND) 0.5 to +.0 in DC Input (Referenced to GND) 0.5 to + 0.5 out DC Output (Referenced to GND) 0.5 to + 0.5 I in DC Input Current, per Pin ±20 ma I out DC Output Current, per Pin ±25 ma I CC DC Supply Current, and GND Pins ±50 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package 500 450 mw T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds C (SOIC or TSSOP Package) 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating SOIC Package: mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply (Referenced to GND) in, out DC Input, Output (Referenced to 0 GND) T A Operating Temperature, All Package Types 55 + 25 C t r, t f Input Rise and Fall Time = 0 000 ns (Figure ) = = 0 0 500 400 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. 3
DC ELECTRICAL CHARACTERISTICS (s Referenced to GND) Symbol Parameter Test Conditions IH IL OH OL Minimum High Level Input Maximum Low Level Input Minimum High Level Output Maximum Low Level Output out = 0. or 0. out = 0. or 0. I out 2.4 ma I out 4.0 ma I out 5.2 ma I out 2.4 ma I out 4.0 ma I out 5.2 ma () Guaranteed Limit 55 to 25 C 85 C 25 C.5 2. 3.5 4.2 0.5 0.9.35.8.9 4.4 5.9 2.48 3.98 5.48 0. 0. 0. 0.26 0.26 0.26.5 2. 3.5 4.2 0.5 0.9.35.8.9 4.4 5.9 2.34 3.84 5.34 0. 0. 0. 0.33 0.33 0.33.5 2. 3.5 4.2 0.5 0.9.35.8.9 4.4 5.9 2.20 5.20 0. 0. 0. 0.40 0.40 0.40 I in Maximum Input Leakage Current in = or GND ±0. ±.0 ±.0 A I CC Maximum Quiescent Supply Current (per Package) in = or GND I out = 0 A Unit 20 40 A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t, = t f = 6 ns) Symbol t PLH, t PHL t TLH, t THL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures and 2) Maximum Output Transition Time, Any Output (Figures and 2) () Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance 0 0 0 pf NOTES:. For propagation delays with loads other than 50 pf, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 00 80 20 5 30 5 3 25 90 25 2 95 40 9 6 50 0 3 26 0 55 22 9 Typical @ 25 C, = 5.0 C PD Power Dissipation Capacitance (Per Gate)* 33 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 CC f + I CC. For load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). Unit ns ns 4
t r t f INPUT A OR B 90% 50% 0% GND TEST POINT t PLH OUTPUT Y 90% 50% 0% t PHL DEICE UNDER TEST OUTPUT C L * t TLH Figure. Switching Waveforms t THL *Includes all probe and jig capacitance Figure 2. Test Circuit A Y B Figure 3. Expanded Logic Diagram (/4 of Device) 5
PACKAGE DIMENSIONS SOIC CASE 5A 03 ISSUE H T SEATING PLANE G A 8 D PL B K P PL C 0.25 (0.00) M T B S A S 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A 8.55 8.5 0.33 0.344 B 3.80 4.00 0.50 0.5 C.35.5 0.054 0.068 D 0.35 0.49 0.0 0.09 M J F 0.40.25 0.06 0.049 G.2 BSC 0.050 BSC J 0.9 0.25 0.008 0.009 K 0.0 0.25 0.004 0.009 M 0 0 P 5.80 6.20 0.228 0.244 R 0.25 0.50 0.00 0.09 SOLDERING FOOTPRINT* X 0.58 X.04 X.52.2 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
PACKAGE DIMENSIONS TSSOP CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C X K REF 0.0 (0.004) M T U S S N 8 0.25 (0.00) M B U A G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ SECTION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, 982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A 4.90 5.0 0.93 0.200 B 4.30 0 0.69 0. C.20 0.04 D 0.05 0.5 0.002 0.006 F 0.50 0.5 0.020 0.030 G 0.65 BSC 0.026 BSC H 0.50 0.60 0.020 0.024 J 0.09 0.20 0.004 0.008 J 0.09 0.6 0.004 0.006 K 0.9 0.30 0.00 0.02 K 0.9 0.25 0.00 0.00 L 6.40 BSC 0.252 BSC M 0 8 0 8 SOLDERING FOOTPRINT*.06 0.65 PITCH X 0.36 X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.