ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems Today! VLSI Scaling Trends/Disciplines! Effects! Alternatives (cheating) Lec 12: October 4, 2017 Scaling 2 Scaling! Premise: features scale uniformly " everything gets better in a predictable manner! Parameters: # λ (lambda) -- Mead and Conway (Day14) # F -- Half pitch ITRS (F=2λ) # S scale factor Rabaey # F =S F ITRS Roadmap! International Technology Roadmap for Semiconductors " Try to predict where industry going! ITRS 2.0 started in 2015 with new focus " System Integration, Heterogeneous Integration, Heterogeneous Components, Outside System Connectiviy, More Moore, Beyond CMOS and Factory Integartion.! http://www.itrs2.net/ 3 4 Microprocessor Trans Count 1971-2015 8006 4004 Curve shows transistor count doubling every two years 80286 Mot 68000 Mot 6800 8080 8086 Zilog Z80 MOS 6502 80386 80186 80486 Pentium Kenneth R. Laker, University of Pennsylvania, updated 20Jan15 Pentium 4 6-Core i7 i7 2-Core Itanium 2 AMD K10 AMD K7 Pentium III Pentium II AMD K5 16-Core SPARC T3 AMD K8 10-Core Xenon IBM 4-Core z196 IBM 8-Core POWER7 4-Core Itanium Tukwilla AMD 6-Core Opteron 4-Core i7 2400 2015: Oracle SPARC M7, 20 nm CMOS, 32-Core, 10B 3-D FinFET transistors. 2015 5 Trend Minimum Feature Size vs. Year 100 µm 10 µm 1 µm 0.1 µm 10 nm 1 nm Process Node/ Minimum Feature 0.18 µm in 1999 Transition Region Quantum Devices Integrated Circuit History ITRS Roadmap NOT SO Distant Future 0.1 nm Atomic Dimensions Year 1960 1980 2000 2020 2040 Minimum Feature Measure = line/gate conductor width or half-pitch (adjacent 1 st metal layer lines or adjacent transistor gates) 6 1
Scaling Intel Cost Scaling Moore s Law Impact on Intel ucomputers Min Feature Size 2BT µp (Intel Itanium Tukwila) 4-Core chip (65 nm) introduced Q1 2010. 3BT mp (Intel Itanium Poulson) 8-Core chip (32 nm) to be introduced 2012. Serial data links operating at 10 Gbits/sec. Introduces 22 nm Tri-gate Transistor Tech. Increased reuse of logic IP, i.e. designs and cores. http://www.anandtech.com/show/8367/intels-14nm-technologyin-detail 7 Complexity - # transistors Double every Two Years 0.032um 2009 0.022um 2011 2010 YEAR 8 More Moore $ Scaling 22nm 3D FinFET Transistor! Geometrical Scaling " continued shrinking of horizontal and vertical physical feature sizes! Equivalent Scaling " 3-dimensional device structure improvements and new materials that affect the electrical performance of the chip even if no geometrical scaling! Design Equivalent Scaling " design technologies that enable high performance, low power, high reliability, low cost, and high design productivity even if neither geometrical nor equivalent scaling can be used High-k gate dielectric Tri-Gate transistors with multiple fins connected together increases total drive strength for higher performance 9 http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-details_presentation.pdf 10 More-than-Moore Semiconductor System Integration More Than Moore's Law 10 10 10 10 More-than-Moore, International Road Map (IRC) White Paper, 2011. International Technology Road Map for Semiconductors 11 Transistors/cm 2 10 9 10 8 10 7 10 6 10 5 10 4 10 3 10 2 10 SOP law for system integration. As components shrink and boards all but disappear, component density will double every year or so. Multichip Module 10 9 10 8 10 7 10 6 10 5 Systemin-package 10 4 System- 10 3 (SIP) on-package (SOP) 10 2 1970 1980 1990 2000 2010 2020 R. Tummala, Moore's Law Meets Its Match, IEEE Spectrum, June, 2006 10 Components/cm 2 12 2
Improvement Trends for VLSI SoCs Enabled by Geometrical and Equivalent Scaling Societal Needs! TRENDS:! Higher Integration level " exponentially increased number of components/ transistors per chip/package.! Performance Scaling " combination of Geometrical (shrinking of dimensions) and Equivalent (innovation) Scaling.! System implementation " SoC + increased use of SiP - > SOP! CONSEQUENCES:! Higher Speed " CPU clock rate at multiple GHz + parallel processing.! Increased Compactness & less weight " increasing system integration.! Lower Power " Decreasing energy requirement per function.! Lower Cost " Decreasing cost per function. 13 14 More Moore $ Scaling! Examples: " Design-for-variability " Low power design (sleep modes, clock gating, multi- Vdd, etc.) " Multi-core SOC architectures Preclass 1! Scaling from 32nm $ 22nm? " Scaling minimum gate length " And pitch distance 15 16 Half Pitch (= Pitch/2) Definition MOS Transistor Scaling - (1974 to present) Metal Pitch Poly Pitch S=0.7 per technology node [0.5x per 2 nodes] (Typical DRAM) (Typical MPU/ASIC) Pitch Gate Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng 17 Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng 18 3
Scaling Calculator Node Cycle Time: 0.7x 0.7x 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x N N+1 N+2 Log Half-Pitch 1994 NTRS -.7x/ 3yrs Actual -.7x/2yrs Scaling! Channel Length (L)! Channel Width (W)! Oxide Thickness (T ox )! Doping (N a )! Voltage (V) Linear Time Source: 2001 ITRS - Exec. Summary, ORTC Figure, Andrew Kahng 19 20 Full Scaling (Ideal Scaling)! Channel Length (L) S! Channel Width (W) S! Oxide Thickness (T ox ) S! Doping (N a ) 1/S! Voltage (V) S Effects on Physical Properties and Specs?! Area! Capacitance! Resistance! Threshold (V th )! Current (I d )! Gate Delay (τ gd )! Wire Delay (τ wire )! Power 21 22 Area Capacitance! λ % λs! Area impact?! Α = L W! Α % ΑS 2! 32nm % 22nm! 50% area! 2 transistor capacity for same area L! Capacitance per unit area scaling? " C ox = ε SiO 2 /T ox " T ox % S T ox " C ox % C ox /S S=0.7 W S=0.7 23 24 4
Capacitance! Gate Capacitance scaling? # C gate = A C ox # Α % Α S 2 # C ox % C ox /S # C gate % S C gate Resistance! Resistance scaling?! R=ρL/(W*t)! W$ S W! L, t remain similar (not scaled)! R $ R/S 25 26 Threshold Voltage! V TH % S V TH Current! Which Voltages matters here? (V gs,v ds,v th )! Transistor charging looks like voltage-controlled current source! Saturation Current scaling? I d =(µc OX /2)(W/L)(V gs -V TH ) 2 V gs =V$ S V V TH $ S V TH W$ S W L$ S L C ox $ C ox /S 27 28 Current! Which Voltages matters here? (V gs,v ds,v th )! Transistor charging looks like voltage-controlled current source! Saturation Current scaling? I d =(µc OX /2)(W/L)(V gs -V TH ) 2 V gs =V$ S V V TH $ S V TH W$ S W L$ S L C ox $ C ox /S I d =(µc OX /2S)(SW/SL)(SV gs -SV TH ) 2 29 Current! Which Voltages matters here? (V gs,v ds,v th )! Transistor charging looks like voltage-controlled current source! Saturation Current scaling? I d =(µc OX /2)(W/L)(V gs -V TH ) 2 V gs =V$ S V V TH $ S V TH W$ S W L$ S L C ox $ C ox /S I d $ S I d 30 5
Current! Velocity Saturation Current scaling? V gs =V$ S V V TH $ S V TH L$ S L W$ S W C ox $ C ox /S Current! Velocity Saturation Current scaling? V gs =V$ S V V TH $ S V TH L$ S L W$ S W C ox $ C ox /S V DSAT Lν sat µ n V DSAT $ S V DSAT 31 32 Current Gate Delay! Velocity Saturation Current scaling? V gs =V$ S V V TH $ S V TH L$ S L W$ S W C ox $ C ox /S V DSAT $ S V DSAT I d $ S I d V DSAT Lν sat µ n % I DS ν sat C OX W V GS V TH V ( DSAT ' * & 2 ) # Gate Delay scaling? # τ gd =Q/I=(CV)/I # V$ S V # I d $ S I d Note: I ds modeled as current source; V is changing with scale factor 33 34 Gate Delay Wire Delay # Gate Delay scaling? # τ gd =Q/I=(CV)/I # V$ S V # I d $ S I d Note: I ds modeled as current source; V is changing with scale factor # Wire delay scaling? # τ wire =R C # R $ R/S # τ wire $ τ wire! assuming (logical) wire lengths remain constant... # τ gd $ S τ gd 35 36 6
Power Dissipation (Dynamic)! Capacitive (Dis)charging scaling?! P=(1/2)CV 2 f! V$ S V Power Dissipation (Dynamic)! Capacitive (Dis)charging scaling?! P=(1/2)CV 2 f! Increase Frequency?! V$ S V! τ gd $ S τ gd! P$ S 3 P! P$ S 3 P! So: f $ f/s! P $ S 2 P 37 38 Effects?! Area S 2! Capacitance S! Resistance 1/S! Threshold (V th ) S! Current (I d ) S! Gate Delay (τ gd ) S! Wire Delay (τ wire ) 1 S=0.7! Power S 3, S 2 (w/ freq scaling) Power Density! P% S 2 P (increased frequency)! P% S 3 P (same frequency)! A % S 2 A! Power Density: P/A two cases? " P/A % P/A increase freq. " P/A % S P/A same freq. 39 40 Cheating! Don t like some of the implications! High resistance wires! Higher capacitance! Atomic-scale dimensions!. Quantum tunneling! Need for more wiring! Not scale speed fast enough Improving Resistance! R=ρL/(W t)! W$ S W! L, t similar! R $ R/S 41 42 7
Improving Resistance! R=ρL/(W t)! W$ S W! L, t similar! R $ R/S Capacitance and Leakage! Capacitance per unit area " C ox = ε SiO 2 /T ox " T ox % S T ox " C ox % C ox /S What might we do? Didn t scale t quite as fast $ now taller than wide. Decrease ρ (copper) introduced 1997 http://www.ibm.com/ibm100/us/en/icons/copperchip/ 43 What s wrong with t ox = 1.2nm? source: Borkar/Micro 2004 44 Capacitance and Leakage! Capacitance per unit area " C ox = ε SiO 2 /T ox " T ox % S T ox " C ox % C ox /S What might we do? Reduce dielectric constant, ε, and increase thickness to mimic t ox scaling. 45 ITRS 2009 Table PIDS3B Low Operating Power Technology Requirements Grey cells delineate one of two time periods: either before initial production ramp has started for ultrathin body fully depleted (UTB FD) SOI or multi-gate (MG) MOSFETs, or beyond when planar bulk or UTB FD MOSFETs have reached the limits of practical scaling (see the text and the table notes for further discussion). Year of Production 2009 2010 2011 2012 2013 2014 2017 2017 2017 2018 2019 2020 2021 2022 2023 2024 MPU/ASIC Metal 1 (M1) ½ Pitch (nm) (contacted) 54 45 38 32 27 24 21 18.9 16.9 15 13.4 11.9 10.6 9.5 8.4 7.5 Lg: Physical Lgate for High Performance logic (nm) 29 27 24 22 20 18 17 15.3 14 12.8 11.7 10.7 9.7 8.9 8.1 7.4 L g : Physical Lgate for Low OperatingPower (LOP) logic (nm) [1] 32 29 27 24 22 18 17 15.3 14 12.8 11.7 10.7 9.7 8.9 8.1 7.4 EOT: Equivalent Oxide Thickness (nm) [2] Extended planar bulk 1 0.9 0.9 0.85 0.8 UTB FD 0.9 0.85 0.8 0.75 0.7 MG 0.8 0.8 0.75 0.73 0.7 0.7 0.65 0.65 0.6 0.6 Gate poly depletion (nm) [3] Bulk 0.27 0.27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Channel doping (E18 /cm3) [4] Extended Planar Bulk 3 3.7 4.5 5 5.5 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Junction depth or body Thickness (nm) [5] Extended Planar Bulk (junction) 14 13 11.5 10 9 UTB FD (body) 7 6.2 6 5.1 4.7 MG (body) 8 7.6 7 6.4 5.8 5.4 4.8 4.4 4.2 4 EOT elec : Electrical Equivalent Oxide Thickness (nm) [6] Extended Planar Bulk 1.64 1.53 1.23 1.18 1.14 UTB FD 1.3 1.25 1.2 1.15 1.1 MG 1.2 1.2 1.15 1.13 1.1 1.1 1.05 1.05 1 1 46 High-K dielectric Survey Intel NYT Announcement! Intel Says Chips Will Run Faster, Using Less Power " NYT 1/27/07, John Markov " Claim: most significant change in the materials used to manufacture silicon chips since Intel pioneered the modern integratedcircuit transistor more than four decades ago " Intel s advance was in part in finding a new insulator composed of an alloy of hafnium will replace the use of silicon dioxide. Wong/IBM J. of R&D, V46N2/3P133 168, 2002 47 48 8
Wire Layers = More Wiring Gate Delay # τ gd =Q/I=(CV)/I # V$ S V # I d =(µc OX /2)(W/L)(V gs -V TH ) 2 How might we accelerate? # I d $ S I d # τ gd $ S τ gd 49 50 Improving Gate Delay More But Power Dissipation (Dynamic) # τ gd =Q/I=(CV)/I # V$ V # I d =(µc OX /2S)(SW/SL)(V gs -V TH ) 2 # I d $ I d /S # τ gd $ S 2 τ gd How might we accelerate? Don t scale V!! Capacitive (Dis)charging # P=(1/2)CV 2 f # V$ V # P$ S P 51 52 But Power Dissipation (Dynamic) And Power Density! Capacitive (Dis)charging # P=(1/2)CV 2 f # V$ V # P$ S P! Increase Frequency? # f $ f/s 2 # P $ P/S! P$ P/S (increase frequency)! Α $ S 2 Α! What happens to power density? If don t scale V, power dissipation doesn t scale down! 53 54 9
And Power Density Historical Voltage Scaling! P$ P/S (increase frequency)! Α $ S 2 Α! What happens to power density?! P/A $ (1/S 3 )P! Power Density Increases this is where some companies have gotten into trouble 55 http://software.intel.com/en-us/articles/gigascale-integration-challenges-and-opportunities/! Frequency impact?! Power Density impact? 56! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d 57 58! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! f $ (U/S2 ) f Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100 59 60 10
! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! f $ (U/S 2 ) f Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100 What are U and S? 61! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! f $ (U/S 2 ) f Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100 Cheating factors: S=1/100 U=1/10 How much faster are gates? 62 Power Density Impact! I d =(µc OX /2S)(SW/SL)(UV gs -UV TH ) 2! I d $ U 2 /S I d! τ gd $ (SU/(U 2 /S)) τ gd! τ gd $ (S 2 /U) τ gd! f $ (U/S2 ) f f cheat /f ideal =10 Ideal scale factors: S=1/100 U=1/100 τ=1/100 f ideal =100 Cheating factors: S=1/100 U=1/10 τ=1/1000 f cheat =1000! P = 1/2CV 2 f! P $ S U 2 (U/S 2 ) = U 3 /S! P/A = (U 3 /S) / S 2 = U 3 /S 3 63 64 Power Density Impact! P = 1/2CV 2 f! P $ S U 2 (U/S 2 ) = U 3 /S! P/A = (U 3 /S) / S 2 = U 3 /S 3! U=1/10 S=1/100! P/A $ 1000 (P/A) Power Density Impact! P = 1/2CV 2 f! P $ S U 2 (U/S 2 ) = U 3 /S! P/A = (U 3 /S) / S 2 = U 3 /S 3! U=1/10 S=1/100! P/A $ 1000 (P/A)! Compare with ideal scaling:! P/A $ (1/S 3 )P (ideal scaling)! P/A $ 1,000,000 (P/A) (ideal scaling) 65 66 11
uproc Clock Frequency up Power Density MHz Watts The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 http://www.nap.edu/catalog.php?record_id=12980 67 The Future of Computing Performance: Game Over or Next Level? National Academy Press, 2011 http://www.nap.edu/catalog.php?record_id=12980 68 Conventional Scaling! Ends in your lifetime! Perhaps already: " "Basically, this is the end of scaling. " May 2005, Bernard Meyerson, V.P. and chief technologist for IBM's systems and technology group ITRS 2.0 Report 2015! After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors. 69 70 BUT BUT Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf Source:https://newsroom.intel.com/newsroom/wp-content/uploads/sites/11/2017/09/mark-bohr-on-continuing-moores-law.pdf 71 72 12
Big Ideas! Moderately predictable VLSI Scaling " unprecedented capacities/capability growth for engineered systems " change " be prepared to exploit " account for in comparing across time " but not for much longer Admin! HW5 " More transistor practice " Hard prepares you for design project 1 " Due Wednesday! Midterm " Grades and solutions posted " Pick up from me after class 73 74 13