T02 Tutorial Slides for Week 6

Similar documents
Slides for Lecture 16

Slides for Lecture 10

Slides for Lecture 19

Slide Set 3. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

Slide Set 6. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary

EE40 Lec 15. Logic Synthesis and Sequential Logic Circuits

211: Computer Architecture Summer 2016

Lecture 6: Manipulation of Algebraic Functions, Boolean Algebra, Karnaugh Maps

Logic Design I (17.341) Fall Lecture Outline

MC9211 Computer Organization

Logic Design Combinational Circuits. Digital Computer Design

ELC224C. Karnaugh Maps

Boolean algebra. Examples of these individual laws of Boolean, rules and theorems for Boolean algebra are given in the following table.

EEE130 Digital Electronics I Lecture #4

ENG2410 Digital Design Combinational Logic Circuits

Boolean Algebra and Digital Logic 2009, University of Colombo School of Computing

UNIT 5 KARNAUGH MAPS Spring 2011

Review. EECS Components and Design Techniques for Digital Systems. Lec 06 Minimizing Boolean Logic 9/ Review: Canonical Forms

Total Time = 90 Minutes, Total Marks = 50. Total /50 /10 /18

The Karnaugh Map COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

CS/COE0447: Computer Organization and Assembly Language

Simplification of Boolean Functions. Dept. of CSE, IEM, Kolkata

CSE140: Components and Design Techniques for Digital Systems. Logic minimization algorithm summary. Instructor: Mohsen Imani UC San Diego

Computer Organization I. Lecture 13: Design of Combinational Logic Circuits

COSC3330 Computer Architecture Lecture 2. Combinational Logic

CSE 140 Midterm I - Solution

This form sometimes used in logic circuit, example:

Additional Gates COE 202. Digital Logic Design. Dr. Muhamed Mudawar King Fahd University of Petroleum and Minerals

Unit 2 Session - 6 Combinational Logic Circuits

Combinational Logic. By : Ali Mustafa

DIGITAL CIRCUIT LOGIC BOOLEAN ALGEBRA

CHAPTER 7 MULTI-LEVEL GATE CIRCUITS NAND AND NOR GATES

Chapter 7 Logic Circuits

Optimizations and Tradeoffs. Combinational Logic Optimization

Number System conversions

mith College Computer Science CSC270 Spring 16 Circuits and Systems Lecture Notes Week 2 Dominique Thiébaut

COSC 243. Introduction to Logic And Combinatorial Logic. Lecture 4 - Introduction to Logic and Combinatorial Logic. COSC 243 (Computer Architecture)

Simplifying Logic Circuits with Karnaugh Maps

Digital Logic & Computer Design CS Professor Dan Moldovan Spring Copyright 2007 Elsevier 2-<101>

Digital Logic & Computer Design CS Professor Dan Moldovan Spring 2010

1 Boolean Algebra Simplification

ENGG 1203 Tutorial - 2 Recall Lab 2 - e.g. 4 input XOR. Parity checking (for interest) Recall : Simplification methods. Recall : Time Delay

CHAPTER 7. Solutions for Exercises

Chapter 1: Logic systems

EXPERIMENT #4: SIMPLIFICATION OF BOOLEAN FUNCTIONS

Review Getting the truth table

Ex: Boolean expression for majority function F = A'BC + AB'C + ABC ' + ABC.

Digital Logic Design. Combinational Logic

Logic Design. Chapter 2: Introduction to Logic Circuits

Chapter 3 Combinational Logic Design

Lecture 7: Karnaugh Map, Don t Cares

CHAPTER III BOOLEAN ALGEBRA

CMSC 313 Lecture 17. Focus Groups. Announcement: in-class lab Thu 10/30 Homework 3 Questions Circuits for Addition Midterm Exam returned

CHAPTER 5 KARNAUGH MAPS

Chapter 2 Combinational Logic Circuits

Lecture 5: NAND, NOR and XOR Gates, Simplification of Algebraic Expressions

Combinational Logic. Review of Combinational Logic 1

Digital Logic Design ABC. Representing Logic Operations. Dr. Kenneth Wong. Determining output level from a diagram. Laws of Boolean Algebra

Z = F(X) Combinational circuit. A combinational circuit can be specified either by a truth table. Truth Table

Chapter 2. Digital Logic Basics

WEEK 3.1 MORE ON KARNAUGH MAPS

Boolean Algebra & Logic Gates. By : Ali Mustafa

ELCT201: DIGITAL LOGIC DESIGN

Karnaugh Maps (K-Maps)

Fundamentals of Computer Systems

Floating Point Representation and Digital Logic. Lecture 11 CS301

CMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)

CSC258: Computer Organization. Digital Logic: Transistors and Gates

Circuits & Boolean algebra.

Chap 2. Combinational Logic Circuits

CS 121 Digital Logic Design. Chapter 2. Teacher Assistant. Hanin Abdulrahman

Chapter 2 Combinational logic

UNIVERSITI TENAGA NASIONAL. College of Information Technology

CHAPTER III BOOLEAN ALGEBRA

Fundamentals of Computer Systems

UNIT 4 MINTERM AND MAXTERM EXPANSIONS

Chapter 4 BOOLEAN ALGEBRA AND THEOREMS, MINI TERMS AND MAX TERMS

CPE100: Digital Logic Design I

Gate-Level Minimization

INTRO TO I & CT. (Boolean Algebra and Logic Simplification.) Lecture # By: Department of CS & IT.

Chapter 2 Combinational Logic Circuits

Boolean Algebra. Philipp Koehn. 9 September 2016

CPE100: Digital Logic Design I

Lecture 6: Gate Level Minimization Syed M. Mahmud, Ph.D ECE Department Wayne State University

Week-I. Combinational Logic & Circuits

EECS150 - Digital Design Lecture 19 - Combinational Logic Circuits : A Deep Dive

KUMARAGURU COLLEGE OF TECHNOLOGY COIMBATORE

Vidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution

COS 140: Foundations of Computer Science

CPE100: Digital Logic Design I

CSE 140: Components and Design Techniques for Digital Systems

CSCI 2150 Intro to State Machines

EE40 Midterm Review Prof. Nathan Cheung

BOOLEAN ALGEBRA. Introduction. 1854: Logical algebra was published by George Boole known today as Boolean Algebra

Lecture 4: Four Input K-Maps

Review for B33DV2-Digital Design. Digital Design

CHAPTER1: Digital Logic Circuits Combination Circuits

Digital Logic: Boolean Algebra and Gates. Textbook Chapter 3

Lecture (02) NAND and NOR Gates

Transcription:

T02 Tutorial Slides for Week 6 ENEL 353: Digital Circuits Fall 2017 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 17 October, 2017

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 2/11 Topics for today Bubble-pushing and De Morgan s Theorem. Tristate buffers and X and Z values for circuit nodes. K-map exercises.

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 3/11 Exercise 1: Bubble pushing A B C D E F Find an SOP expression for F by bubble-pushing. Find the same expression by algebraic manipulation, including use of De Morgan s Theorem.

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 4/11 Exercise 2: Two-level NAND logic Use bubble-pushing to find an SOP expression to describe this circuit: Ā C B A B C This is just an example of a general fact about two-level NAND logic. What is that fact? A related fact: In CMOS technology, a NAND gate tends to be smaller and to switch faster than an AND or OR gate with the same number of inputs. F

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 5/11 Exercise 3: Tristate buffers Complete the table. In each row, give the state of Y as one of 0, 1, X (for unknown/illegal value), or Z (for floating/ high-impedance). Give brief reasons for each of your six answers. A B E 1 E 2 Y A B E 1 E 2 Y 0 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 1 1 1 1 1

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 6/11 Exercise 4 Simplify F = A B C + A BC + AB C + ABC using a K-map. Repeat the simplification using Boolean algebra, particularly the Combining Theorem: DĒ + DE = D.

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 7/11 Exercise 5 Draw a K-map for F (A,B,C) = A + ĀB. Review: A prime implicant is a rectangle of 1, 2, 4, or 8 1-cells that can t be doubled in size without collecting some 0-cells. Circle the prime implicants of F.

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 8/11 Exercise 5, continued Review: An implicant is any rectangle of 1, 2, 4, or 8 1-cells. Equivalently, the implicants of F are all the products that appear in all of the valid SOP expressions for F. How many implicants does F have that are not prime implicants? (The definitions of prime implicant and implicant on this slide and the previous one apply to functions with 2 4 input variables. Things are more complicated with 5 or more variables.)

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 9/11 Exercise 6 Draw a K-map for G(A,B,C,D) = ĀCD + B CD + AC + Ā BC D + AD + BC D. Review: A distinguished 1-cell is a 1-cell that is covered by only one prime implicant. More review: An essential prime implicant is a prime implicant that covers at least one distinguished 1-cell. Find the essential prime implicants of G. Do the essential prime implicants of G give us a minimal SOP expression for G?

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 10/11 Essential versus non-essential It s important to understand that in discussion of K-maps, non-essential does not mean the same thing as unnecessary or not useful. A minimal SOP expression for a function F must use all of the essential PI s. However, in some but not all K-map problems, one or more non-essential PI s must be used to complete the cover of all the 1-cells.

ENEL 353 F17 T02 Tutorial Slides for Week 6 slide 11/11 Exercise 7 Draw K-maps for the two functions of a 1-bit full adder. Use the K-maps to find minimal SOP expressions for the two functions. A B C IN C OUT S 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1