The PSP compact MOSFET model An update

The PSP compact MOSFET model An update Gert-Jan Smit, Andries Scholten, D.B.M. Klaassen NXP Semiconductors Ronald van Langevelde Philips Research Europe Gennady Gildenblat, Weimin Wu, Xin Li, Amit Jha, Hailing Wang* Arizona State University; *now at IBM

Affiliations founded by Philips Semiconductors http://pspmodel.asu.edu http://www.nxp.com/philips_models/mos_models/psp/ 2

Outline History & overview DC verification on 65nm technology Symmetry and distortion Non-quasi static effects Summary & references 3

Outline History & overview DC verification on 65nm technology Symmetry and distortion Non-quasi static effects Summary & references 4

History April 2005: First PSP version (100.0) released. Created from MOS Model 11 (Philips) SP (Penn State) December 2005: CMC elects PSP as next generation compact MOSFET model (i.e. successor of BSIM3/4) June 2006: First CMC-standardized version (PSP 102.0) was released Future: PSP extended to complete family of models Bulk CMOS Varactor PD-SOI FD-SOI FinFETs 5

Model overview PSP is a surface potential based compact MOSFET model, suitable for digital, analog and RF design non-uniform lateral/vertical doping field-dependent mobility velocity saturation conductance effects (CLM, DIBL, etc.) series-resistance short-channel effects (incl. RSCE) narrow-width effects gate poly-depletion quantum-mechanical corrections overlap capacitances (ψ s -based) impact ionization current gate leakage current gate-induced drain/source leakage (GIDL, GISL) junction diode I-V and C-V (forward and reverse) diode reverse breakdown noise (1/f, thermal, induced gate and shot noise) non-quasi-static effects gate and bulk resistances STI stress effect See also MOS-AK 2005 6

Update PSP 102.0 Changes PSP 100.0 102.0 Binning Improved Gummel symmetry (modified CLM-model and V B -clamping) Replaced lateral gradient factor More flexible geometry scaling Improved mobility model (CS, FETA, scaling) Improved forward bulk-bias behavior BSIM-like instance parameters for JUNCAP2 (AS, AD, PS, PD) Several minor improvements, bug fixes, and maintenance October 2006: PSP 102.1 includes first C-implementation of NQS-model Partly based on useful feedback by Jazz, Infineon, Freescale, STm, RFMD, Analog Devices, 7

Outline History & overview DC verification on 65nm technology Symmetry and distortion Non-quasi static effects Summary & references 8

Long channel (65nm technology) I D (ma) 1.0 0.8 0.6 0.4 0.2 Drain current and output conductance W/L = 10/1µm, V GS = 0 1V 0.0 0.0 0.2 0.4 0.6 0.8 1.0 V DS (V) g DS (A/V) 10-2 10-3 10-4 10-5 10-6 10-7 measurement PSP 10-8 10-9 0.0 0.2 0.4 0.6 0.8 1.0 V DS (V) 9

Short channel (65nm technology) 8 Drain current and output conductance W/L = 10/0.04µm (poly length = 40nm), V GS = 0 1V 10-1 measurement PSP I D (ma) 6 4 2 0 0.0 0.2 0.4 0.6 0.8 1.0 V DS (V) g DS (A/V) 10-2 10-3 10-4 10-5 10-6 10-7 0.0 0.2 0.4 0.6 0.8 1.0 V DS (V) 10

Gate current (65nm technology) Gate current W/L = 10/1µm, V DS = 0 1V I G (A) 10-6 10-7 10-8 measurement PSP 10-9 10-10 -1.0-0.5 0.0 0.5 1.0 V GS (V) PSP model has been verified to successfully describe various 90nm, 65nm and 45nm processes 11

R2R-circuit Benchmark test for quality of integral along channel Ideal long channel model 0.15 V DB W I DS = µ q L V SB inv dv rel. error (%) 0.10 0.05 6 3 2 rel. error = 2 n 1 I I n fs I fs 0.00 1 10-1 10 0 10 1 10 2 I fs ( µ A) 12

Outline History & overview DC verification on 65nm technology Symmetry and distortion Non-quasi static effects Summary & references 13

Gummel symmetry (i) CMOS devices are symmetric w.r.t. source/drain Imposed on the model by applying source/drain interchange V DS 0 : I DS (V D,V G,V S,V B ) = I + DS (V D,V G,V S,V B ) V DS < 0 : I DS (V D,V G,V S,V B ) = I + DS (V S,V G,V D,V B ) Guaranteeing a smooth connection at V DS =0 is nontrivial 14

Gummel symmetry (ii) Why is Gummel symmetry nontrivial to achieve? 0.6 0.5 0.4 I D (ma) 0.3 0.2 0.1 0.0 0.0 0.5 1.0 1.5 2.0 V DS (V) velocity saturation V DSAT calculation V DS V DSAT transition channel length modulation (CLM). 15

Gummel symmetry (iii) Symmetry test I D (V X ) smooth at V X =0? V G gate oxide source drain -V X V B V X 16

Gummel symmetry (iv) 3 I D / V 3 X 2 1 0-1 -2-3 improved CLM model (PSP102) -2.50-2.75-4 -0.3-0.2-0.1 0.0 0.1 0.2 0.3 V X (V) 3 I D / V 3 X -3.00-3.25-3.50 old model (PSP < 101) -0.10-0.05 0.00 0.05 0.10 V X (V) 17

Distortion (i) Gummel symmetry is important for RF-CMOS circuit design (distortion) PSP gives excellent description up to at least 3 rd order derivatives 10-1 g DS3 NMOS 10/0.12 g DS i (A/V i ) 10-2 10-3 g DS1 g DS2 0.0 0.3 0.6 0.9 V DS (V) 18

Distortion (ii) Two-tone intermodulation distortion simulation (1.8 and 1.9 GHz) V GS =1V, V DS =V SB =0V, W/L=5/0.3µm NMOS, 90nm technology) P out (dbm) -50-100 theoretical slope PSP simulation 50Ω P out (dbm) -50-100 50Ω theoretical slope BSIM4 simulation -150-150 -60-50 -40-30 -20-10 P in (dbm) -60-50 -40-30 -20-10 P in (dbm) 19

Outline History & overview DC verification on 65nm technology Symmetry and distortion Non-quasi static effects Summary & references 20

PSP NQS model (i) Non-quasi static effects: it takes time for charge to move trough the channel distributed effect memory effect continuity equation: dq/dt di/dx S Gate D Previously: channel segmentation (still good benchmark!) PSP: spline collocation method (adopted from SP model) No parameter fitting! 21

PSP NQS model (ii) Same physics as segmentation model, but much faster: relative simulation time 14 12 10 8 6 4 2 0 0 2 4 6 8 10 no. collocation points segmentation 3x faster! spline collocation method QS reference 22

PSP NQS model (iii) current continuity equation + spline approximation system of (coupled) ordinary differential equations dq dt ( Q, K Q ) k f, k 1 = Q k : charge densities along channel N implemented as sub-circuits, solved by circuit simulator: example: (N = 2) V 1 = Q 1 V 2 = Q 2 C C f ( Q, ) 1 1 Q2 C C f ( Q, ) 2 1 Q2 23

PSP NQS model (iii) Does model preserve basic physics? NQS model sanity check Important for varactor modeling! Basic NQS physics strong inversion V DS =0 f 0 R in = 12 1 g DS R in 1 = 12 g no parameter fitting! PSP-NQS DS SWNQS=9 24

PSP NQS model (v) 10 0 Y-parameter measurements NMOS W/L=120/3µm, V DS = 1.5V, V GS = 0.5, 1.0, 1.5V 10-1 measurement PSP quasi-static PSP NQS 10-1 10-2 Re( Y 11) (S) 10-2 Re( Y 21) (S) 10-3 10-3 10-4 10-4 10 0 10 1 10 2 f (GHz) 10-5 10 0 10 1 10 2 f (GHz) 25

PSP NQS model (vi) 10 4 Y-parameter measurements NMOS W/L=120/3µm, V DS = 1.5V, V GS = 0.5, 1.0, 1.5V 10 4 measurement PSP quasi-static PSP NQS C GG (ff) 10 3 10 2 C DG (ff) 10 3 10 2 10 1 10 0 10 1 10 2 f (GHz) 10 1 10 0 10 1 10 2 f (GHz) 26

Killer NOR circuit (i) 27

Killer NOR circuit (ii) 1.5 V(A) in1 V(B) in2 V(Q) out 1.0 1 V (V) 0.5 V (V) 0 0.0-1 V(X) QS V(X) NQS -0.5 0 50 100 150 200 t (ns) -2 0 50 100 150 200 t (ns) 28

Outline History & overview DC verification on 65nm technology Symmetry and distortion Non-quasi static effects Summary & references 29

Summary Affiliation change: Philips NXP Penn State Arizona State PSP is the new CMC industrial standard MOSFET model PSP has an excellent description of distortion PSP has a unique physics based NQS-extension 30

References website http://pspmodel.asu.edu PSP general TED 53(9), p. 1979 (2006) Chapter 2 of Transistor Level Modeling for Analog/RF IC Design, W. Grabinski, B. Nauwelaers and D. Schreurs (Eds.), Springer-SBM, February 2006 PSP NQS TED 53(9), p. 2035 (2006) JUNCAP2 TED 53(9), p. 2098 (2006) FinFETs IEDM 2006 31