Supporting information Design, Modeling and Fabrication of CVD Grown MoS 2 Circuits with E-Mode FETs for Large-Area Electronics Lili Yu 1*, Dina El-Damak 1*, Ujwal Radhakrishna 1, Xi Ling 1, Ahmad Zubair 1, Yuxuan Lin 1, Yuhao Zhang 1, Meng-Hsi Chuang 2, Yi-Hsien Lee 2, Dimitri Antoniadis 1, Jing Kong 1, Anantha Chandrakasan 1 and Tomas Palacios 1 1 MIT, 77 Massachusetts Avenue, Cambridge MA 02139, USA. Tel: +1 (617) 955-9645, 2 Materials Science and Engineering, National Tsing-Hua University, Hsinchu, 30013. Taiwan *D. El-Damak and L. Yu contributed equally to this work. Corresponding authors: L.Yu (liliyu@mit.edu, fax: +1 (617) 258-7393) and D. El- Damak(deldamak@mit.edu) S1
1. CVD growth of MoS 2 Figure S1 (a) A schematic illustration of the MoS 2 CVD system (top) and the temperature profile used for a typical growth. (b) Optical micrograph showes good uniformity and a high coverage approaching 100%. High resolution TEM and its diffraction pattern indicate the highly ordered lattice structure of CVDgrown MoS 2. AFM confirms the uniformity and atomic flattness (inset) of monolayer MoS 2. Large-area single layer MoS 2 was grown on 300 nm SiO 2 /Si substrate for large-scale electronics. The growth of MoS 2 monolayers was initiated with the seeding of PTAS on substrate surfaces. A high solubility of PTAS in deionized (DI) water enables a uniform distribution of the seeds on the hydrophilic substrate surfaces. Uniform but small PTAS are precipitated on the surfaces after drying the water. The treated substrates are mounted up-side down in a growth furnace, the schematic set-up of which is shown in Figure S1. The MoO 3 powders (0.03g) and S powders (0.01g) were placed in different crucibles. The optimized distance of MoO 3 and S crucible is 18 cm. During growth, the furnace was heated to the growth temperature of 650 C and Ar gas flow passed through the furnace at a flow rate of 10sccm. The sulfur vapor is carried by the Ar gas flow and the MoO 3 powders were evaporated and reduced by the S vapor to form MO 3-x vapor. The MO 3-x arrives at the substrate surface and reacts with the S vapor to form MoS 2. With the seeding of PTAS, the synthesis of MoS 2 favors layer growth and forms a continuous single layer MoS 2 of size a few cm with a limited furnace size (Figure S1 b).. There is a discontinuous area full of isolated triangles because of reduced reactants for a geometry of crucible. The triangular shape of MoS 2 monolayers is a direct consequence of the crystal structure of MoS 2. The domain size of this sample is 20 µm on average. S2
2. Energy Band diagram of MoS 2 Device. Figure S2, (a) Energy band of separated part in MoS2 transistors. (b) Band diagram of MoS 2 transistor along vertical direction with and without gate bias. Figure S2 (a) shows the separate energy diagrams of metal, insulator and semiconductor. When they are put together, the Fermi level of semiconductor and metal layer reach equilibrium with the help of potential drop across the oxide capacitor as well as the space charge layer. Unlike normal 3D semiconductor, in the case of MoS 2, its thickness is only 0.65nm, thus there is negligible potential drop in the vertical direction. In the design, the metal has larger work function than MoS 2. When semiconductor and metal are in contact, body charge depletion happens in the 3D configuration, while in 2D MoS 2, Fermi level is directly shifted away from conductive band, forming positive charge on the surface. When positive voltage applied on the gate, the potential is shared by gate oxide and surface potential to shift the semiconductor Fermi level. Both potential drop will cause changes of charge density. 1 Where, V gs is the gate voltage, V ox is the voltage drop across the gate dielectric, V ch is the voltage drop over the semiconductor channel. DOS is the density of state, as a function of energy. is the fermi distribution of the charge. The charge in the channel, is determined by the Fermi level 1/1exp / 2 is the Fermi level of MoS 2 when it is isolated. g is the degeneracy factor and is the effective mass for MoS 2 and it is 0.57 for electrons. Since the devices we studied are always n type, the formula can be simplified as: S3
1exp Since the large density of state in MoS 2, it is hard to reach degenerate doping level, thus exp ln It is clear that increase with and then saturates at critical voltage V cr as increase. More detailed discussion is available in reference 1. For 300 nm SiO 2 gate oxide, when is larger than 1.86e9 cm -2, stay at constant value around 0.698V. Thus the device enters accumulation region and it is fully on; We can define and the device can be described using sheet charge approximation. Please note that everything discussed here is based on flat band assumption. The Fermi level difference between the metal and the fixed charge within the dielectric layer will shift. In this work we use Pd as gate metal to get high and optimized gate first process to reduce, to get enhancement mode device. When is below V t, MoS 2 transistor is in subthreshold region and the channel charge changes with gate voltage as described above, while when is larger than V t, MoS 2 transistor work in a similar way as silicon device in both linear and saturation regions. It should be noted that an MoS 2 FET from a circuit design perspective is similar to Si NMOS FET in a sense that it has three main regions of operations subthreshold, linear and saturation. However it should be noted that in a regular silicon NMOS FET, the threshold voltage (device is fully on) is defined as the gate voltage at which the surface layer inverts from p-type to n-type. However, in Mos 2 FET, the channel is originally n-type and applying a positive voltage across the gate increases the electrons doping (accumulation of charge). S4
3. Statistic distribution of device subthreshold swing Figure S3. Subthreshold swing (SS) vs. channel length of single layer MoS 2 FET using gate-first process. The small SS values confirm the excellent quality and interface of the dielectric S5
4. MoS 2 Device Compact Model. Key model equations:,, ;, 2 1, (1),, /,, / / regime) (2),,,, μ (3) (,, /, in mobility,,,,,, (4), Equations 1. (1) - (3) The key transport and charge equations of the MVS core- FET model that capture currents and charges in the channel region are given. Here v sat is saturation velocity, µis mobility, Φ t is thermal voltage, C g is gate capacitance, n is subthreshold factor. (4) The key Schottky source-drain contact resistance showing a high resistance at low lateral fields while showing saturation at high fields. Here Vsat,sc is the saturation voltage for the contact resistance saturation, k activates gate-length dependence. ; Table S1: Key parameters for transport and charge fitted to MoS 2 FETs Parameters Values Notes Extracted parameters L g (µm) 2.0 Channel length W (µm) 100 Number of fingers Gate width C g (F/cm 2 ) 3.0e-7 Areal gate capacitance R C (ohm-mm) 6.0 Contact resistance (cm 2 /Vs) 35 Low-field mobility V t0 (V) 2.1 Threshold voltage for V d~0v Electrostatic fitting parameters (V/V) 0.0081 Drain-induced-barrier-lowering SS [V/Dec] 0.490 Sub-threshold swing C of (F/cm 2 ) 3.0e-11 Fringing gate capacitance Transport fitting parameters S6
v sat (cm/s) 1.8e6 Saturation velocity 3 Lateral-field saturation parameter 5. Parameterized Layout Cell Figure S4. Illustration of parametric layout cell in commercial IC design environment. Reference (1) Ma, N. and Jena, D., 2D Materials, 2015. 2, 015003. S7