How a single defect can affect silicon nano-devices. Ted Thorbeck

Similar documents
Lecture 6: 2D FET Electrostatics

A final review session will be offered on Thursday, May 10 from 10AM to 12noon in 521 Cory (the Hogan Room).

Lecture 12: MOS Capacitors, transistors. Context

Scaling Issues in Planar FET: Dual Gate FET and FinFETs

MOS Capacitors ECE 2204

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

Classification of Solids

L ECE 4211 UConn F. Jain Scaling Laws for NanoFETs Chapter 10 Logic Gate Scaling

Single ion implantation for nanoelectronics and the application to biological systems. Iwao Ohdomari Waseda University Tokyo, Japan

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Quantum Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

ECE-305: Fall 2017 MOS Capacitors and Transistors

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ECE 340 Lecture 39 : MOS Capacitor II

ECE-305: Fall 2017 Metal Oxide Semiconductor Devices

Surfaces, Interfaces, and Layered Devices

MOS CAPACITOR AND MOSFET

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

Section 12: Intro to Devices

Multiple Gate CMOS and Beyond

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

Semiconductor Physics fall 2012 problems

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

MOSFET: Introduction

Lecture 3: Heterostructures, Quasielectric Fields, and Quantum Structures

Choice of V t and Gate Doping Type

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

Semiconductor Physics Problems 2015

Gate Carrier Injection and NC-Non- Volatile Memories

Nanoelectronics 08. Atsufumi Hirohata Department of Electronics. Quick Review over the Last Lecture E = 2m 0 a 2 ξ 2.

ECE 342 Electronic Circuits. Lecture 6 MOS Transistors

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

Stretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa

Electrostatics of Nanowire Transistors

single-electron electron tunneling (SET)

MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University

Formation of unintentional dots in small Si nanostructures

Section 12: Intro to Devices

Lecture 11: MOS Transistor

Advanced Flash and Nano-Floating Gate Memories

Single Electron Transistor (SET)

an introduction to Semiconductor Devices

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

Integrated Circuits & Systems

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented.

Digital Electronics Part II - Circuits

Current mechanisms Exam January 27, 2012

Lecture 5: CMOS Transistor Theory

CMOS Scaling. Two motivations to scale down. Faster transistors, both digital and analog. To pack more functionality per area. Lower the cost!

GaN based transistors

Modeling and Computation of Gate Tunneling Current through Ultra Thin Gate Oxides in Double Gate MOSFETs with Ultra Thin Body Silicon Channel

EE410 vs. Advanced CMOS Structures

MOSFET SCALING ECE 663

N ano scale l S il ii lco i n B ased N o nvo lat l i atl ie l M em ory r Chungwoo Kim, Ph.D.

Lecture 20: Semiconductor Structures Kittel Ch 17, p , extra material in the class notes

A Multi-Gate CMOS Compact Model BSIMMG

ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems

New Tools for the Direct Characterisation of FinFETS

Nanoelectronics. Topics

Electronics with 2D Crystals: Scaling extender, or harbinger of new functions?

Surfaces, Interfaces, and Layered Devices

Journal of Electron Devices, Vol. 18, 2013, pp JED [ISSN: ]

Gold Nanoparticles Floating Gate MISFET for Non-Volatile Memory Applications

Simulation of Intrinsic Parameter Fluctuations in Decananometer and Nanometer-Scale MOSFETs

Graphene photodetectors with ultra-broadband and high responsivity at room temperature

Lecture 3: CMOS Transistor Theory

Electronic transport in low dimensional systems

Application of High-κ Gate Dielectrics and Metal Gate Electrodes to enable Silicon and Non-Silicon Logic Nanotechnology

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

Indium arsenide quantum wire trigate metal oxide semiconductor field effect transistor

Low Frequency Noise in MoS 2 Negative Capacitance Field-effect Transistor

Silicon-based Quantum Computation. Thomas Schenkel

COTS BTS Testing and Improved Reliability Test Methods

Simple and accurate modeling of the 3D structural variations in FinFETs

23.0 Review Introduction

Quantum Information Processing with Semiconductor Quantum Dots

Device 3D. 3D Device Simulator. Nano Scale Devices. Fin FET

ECE 342 Electronic Circuits. 3. MOS Transistors

ELEC 4700 Assignment #2

! Previously: simple models (0 and 1 st order) " Comfortable with basic functions and circuits. ! This week and next (4 lectures)

Chapter 3 Basics Semiconductor Devices and Processing

Emerging Research Devices: A Study of CNTFET and SET as a replacement for SiMOSFET

Collaborative project*

Extensive reading materials on reserve, including

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

Universal Mobility-Field Curves For Electrons In Polysilicon Inversion Layer

Quantum Information Processing with Semiconductor Quantum Dots. slides courtesy of Lieven Vandersypen, TU Delft

Transport through Andreev Bound States in a Superconductor-Quantum Dot-Graphene System

Lecture 9. Strained-Si Technology I: Device Physics

The Intrinsic Silicon

III-V CMOS: What have we learned from HEMTs? J. A. del Alamo, D.-H. Kim 1, T.-W. Kim, D. Jin, and D. A. Antoniadis

!""#$%&'("')*+,%*-'$(,".,#-#,%'+,/' /.&$0#%#'/(1+,%&'.,',+,(&$+2#'3*24'5.' 6758!9&!

EECS130 Integrated Circuit Devices

Observation of ionic Coulomb blockade in nanopores

Silicon Nanowires for Single Electron. Transistor Fabrication

ABSTRACT. Department of Physics. a narrow ( 100 nm) metal-oxide-semiconductor field-effect transistor (MOSFET).

MOS Transistor Theory MOSFET Symbols Current Characteristics of MOSFET. MOS Symbols and Characteristics. nmos Enhancement Transistor

Transcription:

How a single defect can affect silicon nano-devices Ted Thorbeck tedt@nist.gov

The Big Idea As MOS-FETs continue to shrink, single atomic scale defects are beginning to affect device performance Gate Source Drain

Outline The impact of a single atom on a MOSFET Locating a single atom in a transistor The potential for a single atom

Review of MOS-FETs I Gate M etal Heavily n-doped Source and Drain Source Drain e - - - e e- e - - e- - h + h + h + h + h + - - e h + e- - - - - - h + h + e- - - e h + h + h + - e- h + h + h + h + h + h h + + h + h + h + Lightly p-doped channel h + O xide S emiconductor

I (na) Review of MOS-FETs II Typical MOS-FET Curv 300 K 3 2 1 Gate Positive 0-1.5-1 -0.5 0 0.5 1 Gate Negative V Gate (V) S Electrons Invert e - D S Holes Accumulate h + h + h h + + h + h + h + h h + + h + h + h + h + h + h + D Threshold Voltage (V T )

Not just shrinking. Planar to 3D Strain Gate Gate Source Drain e - Source High-κ dielectrics Gate Hafnium Oxide Silicon Dioxide Source 3 nm Drain

Atomic Scale Defects Gate Leakage to gate Source 3 nm Drain - - e e- e - e- - e- - e - - e - - e- e e- - - - e e - - - - e- - - e - e- Dopant Trap Random Dopants change V T

Threshold Voltage 25 devices studied, ΔV T 1 V I 10 nm ~ 10s of dopants ΔV T M Pierre, et al. Single-donor ionization energies in a nanoscale CMOS channel, Nature Nano, 2010-1 0 1 V G

Ordered Dopant Dopant Arrays Heavily n-doped Source and Drain Source Drain N Std. Dev. = 0.3 V Shinada, et al. Nature (2005) N Std. Dev. = 0.1 V Random V T Ordered V T

Outline The impact of a single atom on a MOSFET Locating a single atom in a transistor The potential for a single atom

Looking for a single atom Annular dark-field scanning-tem Need to chop up device to look at it K. Van Benthem, et al. Three-dimensional imaging of individual hafnium atoms inside a semiconductor Applied Physics Letters, 87 03104 (2005)

The Basic Idea: Cryogenic Temperatures E E F E C Dip: Quantum Dot Peaks: Tunnel Junction z Source Dopant Drain 12

The Basic Idea: Coulomb Blockade E Gate E F E C Source Drain ev SD 1 mev I V G e C G e C CG 10 19 10aF V 0.01V G V G 13

Nanowire ~20 nm x 20 nm x 500 nm Surrounded by 20 nm SiO 2 Upper Gate Heavily doped Poly A. Fujiwara, et al. APL 88, 053121 (2006) Lower Gates Heavily doped Poly 10 40 nm long 3 independent gates 14

Poly Upper Gate Poly Lower Gate Silicon Dioxide Crystalline Silicon Positive voltage on upper gate inverts wire Upper Gate LGS LGC LGD e - e e- - e- e - e e- - e - Source Drain T = 4.4 K V SD = 2 mv V LGS,C,D = 0

g ( S) Poly Upper Gate Poly Lower Gate Silicon Dioxide Crystalline Silicon Peaks correspond to transport through QDs Negative voltages on lower gates form tunnel barriers 10 0 10-1 10-2 10-3 T = 40 mk V UG = 1 V V LGC,D = 0 LGD -0.8-0.7-0.6-0.5-0.4 V (V) LGD Upper Gate LGS LGC LGD e - e e - - e- e - e - e - Source Drain

Measure current while scanning V UG and V LGD Periodic Coulomb blockade oscillations 0.94 10-3 I (na) 10-2 0.9 0.86 V UG (V) 0.82 Device 1: T =39 mk V SD = 1 mv V LGS,C = 0 17

2 flavors of QDs A: few periods, more strongly coupled to LGD B: many periods, more strongly coupled to UG B A Device 1: T =39 mk V SD = 1 mv V LGS,C = 0 18

Measure Gate Capacitances LGD (af) UG (af) Ratio LGD/UG LGC (af) Dev. 1: Dot A 2.3 + 0.3-1.3 1.3 + 0.2-0.6 1.71 ± 0.02 < 0.1 Dev. 1: Dot B 3.2 ± 0.2 7.9 ± 0.3 0.41 ± 0.01 < 0.1 19

Locate the Dot UG LGC LGD Si Wire Simulated ½ device in FASTCAP 20

Measure gate capacitances Simulate capacitances to 1 nm slices of wire Locate the Dot UG Integrate between z 1 and z 2 z 2 dc C sim = dz dz z 1 For what z 1 and z 2 does C sim = C meas for all gates LGC Si Wire LGD LGD (af) UG (af) Ratio LGD/UG LGC (af) Dev. 1: Dot B 3.2 ± 0.2 7.9 ± 0.3 0.41 ± 0.01 < 0.1 21

UG Location of Dots LGC LGD -50-20 0 20 95 50 Location in nm Si Wire A B z 1 = -40 ± 3 z 1 = 17 ± 1 z 2 = -19 ± 3 Between LGD and UG z 2 = 87 ± 2 LGD A B 22

Dopant Location? UG We see same QDs in multiple devices -The cause appears systematic -Strain from temperature change and oxide growth LGC LGD -Could help make faster finfets A B Si Wire E F E C Dopants? Deduced conduction band modulation 23

Finding a Dopant Very similar technique has been used to located individual dopants and interface traps Nathaniel Bishop, et al; Triangulating tunneling resonances in a point contact Arxiv 1107.5104 (2011)

Outline The impact of a single atom on a MOSFET Locating a single atom in a transistor The potential for a single atom

Ultimate Transistor? Gate Source Drain Dopant Similar to: Cheng Cen, et al. Oxide Nanoelectronics on Demand Science 323, 1026 (2009) Martin Fueschsle, et al. Spectroscopy of few-electron single-crystal silicon quantum dots Nature Nano, 5, 502 (2010)

Beyond the transistor World looks different on the atomic-scale Quantum regime This is a problem for current transistors Tunneling to the gate Could this quantumness become useful

Quantum Search Classical Computer: To search x100 boxes takes x100 as long Quantum Computer: To search x100 boxes takes x10 as long Number of Boxes Old Computer New Computer Quantum Computer 10 10 μs 10 ns 10 ns 1000 1000 μs 1000 ns 100 ns

Conclusions MOSFETs are reaching the point where the placement of a single atom can affect device performance New tools allow the location of a single atom to be determined within a MOSFET The quantum nature of a single atom could one day allow for much more powerful devices

Collaborators Neil Zimmerman Panu Koppinen Michael Stewart Ted Thorbeck (tedt@nist.gov)