EE40 Lec 20 MOS Circuits eading: Chap. 12 of Hambley Supplement reading on MOS Circuits http://www.inst.eecs.berkeley.edu/~ee40/fa09/handouts/ee40_mos_circuit.pdf Slide 1
Bias circuits OUTLINE Smallsignal equivalent circuits Examples: Common source amplifier Source follower Common gate amplifier igital Gates CMOS Slide 2
Bias Circuits Use load line to find Quiescent operating point. emember no current flow through the gate. Fixedplus SelfBias CKT 1 V G v in 2 S Slide 3
Steps for MOSFET Circuit Analysis 1) Look at C case to find Q point Use load line technique All capacitors are open circuit, Inductors are short circuit etermine Qpoint, get g m and r d for small signal AC model 2) AC Small signal analysis C source is ac ground (because there is no AC signal variation). All capacitors are approximated as short circuit (unless otherwise specified). Slide 4
Example: Common Source Amplifier v(t) v in C 1 V G C v L o 2 S C Slide 5
Step 1: find Q point v(t) 2 VG V 1 2 V V I GS G S V I ( ) V S S v in C 1 V G V S C 2 S C Not connected for C component v L o Not connected for C component Slide 6
Load line to determine Q Point by graphical method Loadline to determine V GSQ I V G V S GS I V G V S GS I V V S 0 Loadline to determine V S SQ V GSQ I V 0 V S S From load lines, we get I and hence g m and r d Slide 7
Load line to determine Q Point by analytical method Solve V GSQ assume saturation region first I I Q Q V G K(V V S GSQ GSQ V ) t 2 I Q is known, then solve V SQ V I ( ) Q S V SQ Check V SQ value is consistent with saturation region ( i.e. V S > V GSQ V t ) From load lines, we get I and hence g m and r d Slide 8
etermination of g m and r d graphically Example: Q point is known to be V GS 2.5V, V S 6V r or i v r d S (2.9 2.3) ma (14 2) V 1 3 d 20kΩ 0.05 10 Siemens Slide 9
etermination of g m and r d by Analytical Models In Saturation egion i g m 1/ r d K(v i v GS GS i v S V ) t 2 2K(v λ i GS Q V ) t 2 K i Q KP W K 2 L λ channel mod ulation factor In Triode egion i g m 1/ r K[2(v d i v GS i v S GS 2Kv V )v t SQ K[2(v S GSQ v 2 S t ] V ) 2v SQ ] Slide 10
Small Signal Model Inverting v v, v 0 v v v g in s gs in L ( g v ) o m gs L A v in v g v o L m in L v 1 2 i in in 1 2 Slide 11 For output impedance out : 1. Turn off all independent sources. 2. Take away load impedance L v 0, v 0, g v 0 in gs m gs out r d r d
Example: Source Follower 1 C V G C v(t) v in 2 S v L o Slide 12
Step 1: find Q point 2 VG V 1 2 V V I GS G S V I V S S 1 C V G C v(t) v in 2 S v L o Slide 13
Small Signal Model Noninverting, Voltage Gain <1 in high Current gain can be high L v v v v gs in o 1 1 1 d S L o m gs L v v (1 g ) A in gs m L v in 1 r g v vo gm L v 1 g in m L v 1 2 i in in 1 2 For output impedance out : 1. Turn off all independent sources. 2. Take away L 3. Add V x and find i x, 0, r ( ) d s vx 1, ( ) v v v v v x s g gs x i g v v g rd s s 1 out g r out is small s x m x x s m Slide 14 1 1 m d s
Example: Common Gate Amplifier C V G v L o v(t) v in C S V SS Slide 15
Step 1: find Q point V 0 I V GS S SS V V I ( ) V SS S S C V G v L o v(t) v in C S V SS Slide 16
Load line The only difference in all three circuits are the intercepts at the axes. Again from load lines, we get I and hence g m and r d Slide 17
Small Signal Model Noninverting v v A i L gs 1 1 1 L in o m gs L o v m L vin vgs ( g v ) in m gs in v g v v g v 1 i g in 1 in m s s For output impedance out : 1. Turn off all independent sources. 2. Take away L 3. Add V x and find i x s s vx ix gmvgs Slide 18 v g v, but g 1 v 0 gs m gs m gs out
Logic Gates : PullUp and Pullown PMOS or esistor NMOS or esistor Slide 19
Inverter NOT Gate V in V out Ideal Transfer Characteristics V out V/2 V V in Slide 20
NMOS Inverter: esistor PullUp Circuit: VoltageTransfer Characteristic v OUT i i A v IN F v S v OUT v IN 0 V T v IN / 0 v GS v in V T increasing v GS v IN > V T v S A F 0 1 1 0 Slide 21
NMOS NAN Gate Output is low only if both inputs are high A F B Truth Table A B F 0 0 1 0 1 1 1 0 1 1 1 0 Slide 22
NMOS NO Gate Output is low if either input is high F A B Truth Table A B F 0 0 1 0 1 0 1 0 0 1 1 0 Slide 23
isadvantages of NMOS Logic Gates Large values of are required in order to achieve a low value of V LOW keep power consumption low Large resistors are needed, but these take up a lot of space. Slide 24
CMOS Inverter: Intuitive Perspective CICUIT SWITCH MOELS G S p V IN G S V OUT n V OUT V OL 0 V V OUT V OH Low static power consumption, since one MOSFET is always off in steady state V IN Slide 25 V IN 0 V
The CMOS Inverter: Current Flow V OUT N: sat P: sat i N: off P: lin C V IN G I S V OUT N: sat P: lin A B E G S N: lin P: sat 0 0 N: lin P: off V IN Slide 26
Power issipation: irectpath Current G S v IN : V T v IN i v OUT 0 I peak V T G S i: 0 t sc Energy consumed per switching period: time E t dp sc V I peak Slide 27
CMOS NAN Gate A A B F A B F 0 0 1 0 1 1 1 0 1 1 1 0 Notice that the pullup network is related to the pulldown network by emorgan s Theorem! NMOS, Pulldown PMOS, Pullup B Slide 28
B A B A CMOS NO Gate V A B F 0 0 1 0 1 0 1 0 0 1 1 0 F Notice that the pullup network is related to the pulldown network by emorgan s Theorem! NMOS, Pulldown PMOS, Pullup Slide 29
Multiple Input NO Gate Slide 30
Features of CMOS igital Circuits The output is always connected to or GN in steady state Full logic swing; large noise margins Logic levels are not dependent upon the relative sizes of the devices ( ratioless ) There is no direct path between and GN in steady state no static power dissipation Slide 31