Power LE_UX# LG Evaluation System: Mainboard Revision: P Reference I: 00 # Video out LG Subsystem _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I[..0] LE_UX# _N[..0] SM[..0] I/O ISP_LK I[..0] ISP_[..0] ISP_LK I[..0] ISP_[..0] ISP_LK I[..0] ISP_[..0] HOST_SPI[..0] PWM_O[..0] SPI[..0] SPIO_I SOUN[..0] ISP_TRL[..0] TSIG[..0] LG_JTG[..0] HOST_SPI[..0] PWM_O[..0] SPI[..0] SPIO_I SOUN[..0] ISP_TRL[..0] TSIG[..0] LG_JTG[..0] HOST_SPI[..0] PWM_O[..0] SPI[..0] SPIO_I SOUN[..0] ISP_TRL[..0] TSIG[..0] LG_JTG[..0] Reference I: 00 # Reference I: 00 # Top # LG Evaluation System: Mainboard Hierarchy Part References +---# LG main top +---# Power xx +---# Video out xx +---# LG subsystem xx +---# IO +---# Stepper motors xx +---# Extension xx oeker Stieg - ukrug LGeval Mainboard Size ocument Number R ev 00-00 P ate: Monday, May 0, 00 Sheet o f
V0 P Layout: see application notes in data sheet! 00 00n 0 0u MSH- 0 0 R00 00 MRM0LT U00 0k R0 0k R0 NP P label: P label: UX P label:.v P label:.0v Place capacitors directly power input and output! V VIN 0 0u L00 00 0 0u 00n 00 0 00n 00 OOST SW VIN VIN VIN VIN LT0 F V PG RUN/SS RUN/SS PG R0 k 0 0 0 0p n n R0 V R0 V R0 V0 R0 SW L0 00 0 OOST F R0 k 0 GN V 0 0p 0 TLMT00 0 TLM00 0 TLM00 0 TLM00 00n 0u 0 00n 00 LT0EFE-PF 0 R0 0k MSH- MRM0LT LE_UX# LE_UX# R k VIN. V... V V V R 0k V V0 R k U0 V SW00 S000 SENSE TPS0 SENSE SENSE GN V MR 0 00n 00n TPS0-GN 00n VIN F00 SM00F L0 X00 00n 00 0 SMJ 00n 00 00n 00 KL-SMT-00- oeker Stieg - ukrug LGeval Mainboard: Power Size ocument Number R ev 00-00 P ate: Monday, May 0, 00 Sheet o f
I[..0] I[..0] I0 I I _SL I _S V RN00 0kx RN0 0kx VI0_KEN onsider SIL P layout application note! R00 VO0_E VO0_H SYN VO0_VSYN VI0_TL VI0_TL VI0_TL VI0_HTPLG VI0_P VI0_ISEL I _S I _SL V 0 U00 V E HSYN VSYN TL//K TL//K TL//K EGE/HTPLG P MSEN V ISEL/RST ESL/S SEL/SL GN VO0_0 VO0_ VO0_ VO0_ VO0_ VO0_ VO0_LK_VI VO0_ VO0_ VO0_G VO0_G VO0_G 0 0 PGN PV EXT_SWING GN TX- TX+ V TX0- TX0+ GN TX- TX+ V TX- TX+ GN GN 0 IK+ IK- 0 PV SIL PanelLink Transmitter VI0_PLLV GN 0 0 KEN RESERVE V Place filter network directly to U00 power pins! L00 LMPG00SN 00 0 0 0u 00n n VO0_G GN_VI VO0_G VO0_G VO0_G VO0_R VO0_R VO0_R VO0_R VO0_R VO0_R VO0_R VI0_KEN R0 NP V V VI0_HTPLG 0 00n V0 L0 LMPG00SN 00n VO0_VSYN L0 LMPG00SN 00 ZXV 0 0 00n 0u 0 p R0 VO0_TXM VO0_TXP I _SL I _S VO0_TXM VO0_TXP VO0_TX0M VO0_TX0P VO0_TXP VO0_TXM X00 VIS0T-00S 0 0 R0 R0 R0 R0 R VI0_TL VI0_TL VI0_TL I addresses of SIL read: 0x, write: 0x0 V GN_VI VI0_PLLV L0 LMPG00SN SiIT 0u R0 0 0 VO0_TXM VO0_TXP 00n VO0_TX0M VO0_TX0P 00n VO0_TXM VO0_TXP Place filter network directly to U00 power pins! VO0_TXM VO0_TXP n GN_VI 0 n Place capacitors directly to U00 power pins! 0 00n 0 0u V RN0 0kx PW TRL LETRL L_ VO0_RE R0 VO0_GREEN R0 VO0_LUE R0 VO0_H SYN L0 LMPG00SN 0 p p p p V 00n 0u 0u ISP_LK ISP_[..0] ISP_LK ISP_[..0] ISP_0 ISP_ ISP_ ISP_ ISP_ ISP_ ISP_ ISP_ ISP_ ISP_ ISP_0 ISP_ ISP_ ISP_ ISP_ ISP_ V L0 LMPG00SN Place filter network directly to U0 power pins! 0u VO0_RG0 VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG0 VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG 0 00n 00n VO0_0 VO0_ VO0_ VO0_ VO0_ VO0_ VO0_ VO0_ VO0_G VO0_G VO0_G VO0_G VO0_G VO0_G VO0_G 0 0 n U0 0 G0 G G G G G G G V V V 0 onsider V layout rules! GN GN GN GN GN GN GN GN 0 V Video GN_RGO IOR IOG IO IOR# IOG# IO# GN_RGO R R R R VO0_RE VO0_GREEN VO0_LUE R R u U0 ONTROL V RESIN SENSE TL T GN TLI L_ V 00n PW TRL LETRL VO0_E VO0_VSYN VO0_H SYN VO0_LK_L VO0_R VO0_R VO0_R VO0_R VO0_R VO0_R VO0_R VO0_G VO0_G VO0_G VO0_G VO0_G VO0_G VO0_G VO0_0 VO0_ VO0_ VO0_ VO0_ VO0_ VO0_ VO0_ L_ X0 0 0 0 X0 S--T ISP_ ISP_ ISP_ ISP_ ISP_0 ISP_ ISP_ ISP_ ISP_ ISP_ ISP_ VO0_H SYN VO0_VSYN VO0_E V R VO0_RG VO0_RG VO0_RG VO0_RG VO0_RG0 VO0_RG VO0_RG VO0_RG VO0_LK_RG 0kx RN0 VO0_R VO0_R VO0_R VO0_R VO0_R VO0_R VO0_R RG_LNK RG_PSVE# R0 R R R R R R R SYN# LNK LOK PSVE# VJSTZ0 R R R R0 NP NP??? OMP RSET 0 00n R R L0 00n R LMPG00SN 00n NP GN_RGO GN_RGO Place R,R,R,R directly to the corresponding U0 pins! U0 ISP_LK R R REF LKOUT IT0 VO0_LK_VI LK LK VO0_LK_RG Zero elay LK V lock uffer R R GN LK IT0-GI R R VO0_LK_RG R R VO0_LK_L V 00n 0u V R0 0k R 0k 0p NP VO0_0 VO0_ VO0_ VO0_ VO0_G VO0_G VO0_G VO0_R VO0_R VO0_R VO0_H SYN VO0_E I _SL 0 0 0 0 FTSH-0-0-L-V-EJ-P RG digital output #0 00n 0u VO0_ VO0_ VO0_ VO0_ VO0_G VO0_G VO0_G VO0_G VO0_R VO0_R VO0_R VO0_R VO0_VSYN VO0_LK_RG I _S V oeker Stieg - ukrug LGeval Mainboard: video out Size ocument Number Rev 00-00 P Monday, May 0, 00 ate: Sheet o f
ISP_ VO0_G ISP_ VO0_G ISP_ ISP_ VO0_R ISP_0 VO0_R ISP_ VO0_R ISP_ VO0_ ISP_ VO0_ ISP_ VO0_ ISP_ VO0_ ISP_ VO0_G ISP_ VO0_G ISP_ VO0_G ISP_ VO0_G ISP_ VO0_R ISP_ VO0_R ISP_ VO0_R ISP_ VO0_R GPIO SM_P0 GPIO I0 I_SL GPIO I_S LG_TO GPIO SM_M LG_TK HOST_I GPIO0 SM_P HOST_XS LG_JTG LG_TI PWM_O SM_M HOST_O HOST_SPI PWM_O0 SM_P SM_M HOST_SK HOST_SPI0 PWM_O SM_P SM_M PWM_O PWM_O SM_P SM_M LG_JTG LG_TMS PWM_O PWM_O PWM_O SM_P PWM_O PWM_O PWM_O VO0_ SM SM_P SM SM_M PWM_O SM SM_P SM SM_M VO0_G VO0_G VO0_G VO0_G VO0_R VO0_R VO0_R VO0_R ISP_VSYN VO0_ VO0_ VO0_ SM SM_P SM SM_M ISP_TRL[..0] EV SYN SM SM_P SM SM_M PWM_O[..0] SM SM_P SM SM_M SOUN[..0] FSEL SM SM_P0 SM SM_M0 EHSYN SOUN LG_JTG0 LG_TRST_N _N0 _N I_S I I_SL I0 I[..0] SPIO_I _N ISP_LK _N TSIG TSIG TSIG TSIG TSIG TSIG SM[..0] SPI0_SK SM0 SM_P _N ISP_LK SM SM_M SM SM_P SM SM_M SM SM_P SM0 SM_M _N SM SM_P SM SM_M SM SM_P SM SM_M SM SM_M0 SM0 SM_P0 SPI0_O HOST_SPI HOST_XS HOST_SPI0 HOST_SK HOST_SPI[..0] _N HOST_SPI HOST_I HOST_SPI HOST_O PWM_O TSIG TSIG TSIG _N TSIG TSIG TSIG TSIG0 PWM_O SPI0_XS TSIG TSIG TSIG TSIG0 TSIG TSIG[..0] PWM_O0 PWM_O SPI SPI0_XS SPI0 SPI0_SK SPI[..0] SPI SPI0_O _LRM_0 GPIO GPIO GPIO GPIO PWM_O PWM_O LG_JTG LG_TO LG_JTG LG_TK ISP_TRL FSEL ISP_TRL EV SYN PWM_O ISP_TRL0 EHSYN SOUN0 SG PWM_O0 PWM_O PWM_O PWM_O PWM_O PWM_O PWM_O SM_M0 GPIO ISP_[..0] ISP_ ISP_HSYN GPIO LG_JTG[..0] ISP_ ISP_VSYN GPIO ISP_0 VO0_0 ISP_ VO0_ ISP_ VO0_ ISP_ VO0_ ISP_ ISP_0 VO0_G _N _N0 _N[..0] _N _N _N _N _N _N _LRM_0 _N ISP_E ISP_E ISP_ SPIO_I ISP_TRL[..0] PWM_O[..0] SOUN[..0] I[..0] SM[..0] HOST_SPI[..0] TSIG[..0] LG_JTG[..0] _N[..0] ISP_[..0] ISP_LK SPI[..0] SPIO_I V_RSS V_RSS V0 V0 V0 V0 VIN V Size ocument Number R ev ate: Sheet o f 00-00 P LGeval Mainboard: LG Subsystem oeker Stieg - ukrug Monday, May 0, 00 TGX HOST_INT FPG_PROG# + 0 EEEHP 0 00n 00 X00 QSH-00-0-L---K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00n + 0 EEEHVP 0 0u 0 0u 0 0u n 00 0u 0 00n 0 00n X0 QSH-00-0-L---K 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00n 0 0u
HOST_SPI[..0] I[..0] HOST_SPI[..0] I[..0] SM_RG_SEL0 SM_RG_SEL SM_RG_SEL GPIO GPIO GPIO Stepper Motors HOST_SPI[..0] HOST_SPI[..0] PWM_O[..0] SPI[..0] SPIO_I SM[..0] SM_RG_SEL[..0] PWM_O[..0] SM_L0 SM_L SM_L SM_L[..0] SPI[..0] SPIO_I SM[..0] PWM_O PWM_O PWM_O SM_RG_SEL[..0] SM_L[..0] SPI[..0] SPIO_I SM[..0] Reference I: 00 # GPIO0 GPIO GPIO GPIO GPIO GPIO[..0] PWM_O[..0] PWM_O0 PWM_O PWM_O PWM_O PWM_O PWM_O PWM_O PWM_O PWM_O PWM_O PWM_O0 PWM_O PWM_O Extension I[..0] PWM_O[..0] GPIO[..0] _N[..0] SOUN[..0] ISP_TRL[..0] TSIG[..0] LE_UX# LG_JTG[..0] Reference I: 00 # I[..0] PWM_O[..0] GPIO[..0] _N[..0] SOUN[..0] ISP_TRL[..0] TSIG[..0] LE_UX# LG_JTG[..0] _N[..0] SOUN[..0] ISP_TRL[..0] TSIG[..0] LE_UX# LG_JTG[..0] PWM_O[..0] oeker Stieg - ukrug LGeval Mainboard: I/O Size ocument Number R ev 00-00 P ate: Monday, May 0, 00 Sheet o f
V IN SPI[..0] SPIO_I SM[..0] SM_L[..0] SM_RG_SEL[..0] SPI[..0] SM[..0] SM_L[..0] SM_RG_SEL[..0] SPI0 SPI SPI SM0 SM SM SM SM SM SM SM SM SM SM0 SM SM SM SM SM SM SM SM SM SM0 SM SM SM SM_L0 SM_L SM_L SPI0_SK SPI0_XS SPI0_O SPI0_I SM_P SM_P SM_M SM_M SM_P SM_P SM_M SM_M SM_P SM_P SM_M SM_M SM_P SM_P SM_M SM_M SM_P SM_P SM_M SM_M SM_P0 SM_P0 SM_M0 SM_M0 SM0_N_LUE SM0_N0_RE SM0_N0_GREEN SM_M SM_P SM_M0 SM_P0 SM_N0_RE SM_N0_GREEN SM_M SM_P SM_M SM_P SM_N0_RE SM_N0_GREEN SM_M SM_P SM_M SM_P R X00 0 SSM-0-L-V-L-P VRG0 0 X0 0 SSM-0-L-V-L-P X0 0 SSM-0-L-V-L-P SM0_N0_LUE SM_M SM_P SM_M0 SM_P0 SM_N0_LUE SM_M SM_P SM_M SM_P SM_N0_LUE SM_M SM_P SM_M SM_P /R RG LE / /K /KR /G /KG VRG0 00 00n VRG 0 00n VRG 0 00n VRG0 R0 R V V 0 R00 00n 0k V 0 00n SM0_N_RE SM0_N_GREEN V SM_RG_SEL0 SPI0_XS SM_RG_SEL SM_RG_SEL SPI_I SPI0_SK SPI0_O SM_L0 U00 LXM U00 LXM U00 0 LXM U00 LXM U0 LXM U0 LXM U0 0 LXM U0 LXM U0 SPI_XS0 SPI_XS SPI_XS SPI0_I SPI_SK0 SPI_SK SPI_SK SPI_O PW M_LE0 00 HSMK-00 R0 k 0 0 HSMK-00 R0 k 0 Each group to be placed in a circle with 0mm diameter for instrument backlight! 0 HSMK-00 R0 k 0 0 HSMK-00 R k 0 0 HSMK-00 R0 k 0 SM_L0 0 HSMK-00 R k 0 0 HSMK-00 R0 k 0 R0 k 0 HSMK-00 R k 0 0 0 HSMK-00 HSMK-00 R0 R0 k 0 k 0 T00 MMT0 R0 0k V IN 0 HSMK-00 HSMK-00 R R k 0 k 0 VRG SM_RG_SEL0 SM_RG_SEL SM_RG_SEL VRG SM0_N_LUE R0 0 VRG LTG /R RG LE / /K LTG /KR /G /KG R R VRG SM0_N_RE SM0_N_GREEN 0 00n SM_L SM_L LXM U0 LXM U0 0 LXM U0 LXM PW M_LE PW M_LE SM_L R k R 0k T0 MMT0 V IN /R RG /KR LE / /G R SM_N_RE /R RG LE / /KR /G R SM_N_RE V0 V SM_N_LUE SM_N_LUE R R 0 0 /K LTG /R RG /KR LE / /G /K /KG /KG R R0 R0 SM_N_GREEN SM_N_RE SM_N_GREEN SM_N_LUE R R 0 0 /K LTG /R RG LE / /K /KG /KR /G /KG R R R SM_N_GREEN 0 00n U0 IN Out LT GN SENSE/J GN GN SHN YP LTS R 0k R k 0 n 0 0u 0 00n HSMK-00 R k 0 HSMK-00 R k 0 HSMK-00 R k 0 HSMK-00 R k 0 0 HSMK-00 R k 0 HSMK-00 R k 0 LTG LTG V0 V0 V0 SM_L R k T0 MMT0 0 R 0k n 00n 0u L00 000 n 00n 0u L0 000 n 00n 0u L0 000 V VRG0 V VRG V VRG 00n U0 V V LP SW F T0 0 00n U0 V V LP SW F T0 00n U0 V V LP SW F T0 R 00n 00n k 0 VIO RT R SM0_N0_RE 0u 00n R 00n 00n k 0 VIO RT R SM_N0_RE 0u 0 00n R 00n 00n k 0 VIO RT R SM_N0_RE 0u 00n SPI_SK0 SK G SM0_N0_GREEN SPI_SK SK G SM_N0_GREEN SPI_SK SK G SM_N0_GREEN SPI_I SO SM0_N0_LUE SPI_I SO SM_N0_LUE SPI_I SO SM_N0_LUE SPI_O SI SPI_O SI SPI_O SI SPI_XS0 PW M_LE0 SS PWM_LE GN_ GN_RG GN_OOST GN GN GN R G SM0_N_RE SM0_N_GREEN SM0_N_LUE SPI_XS PW M_LE SS PWM_LE GN_ GN_RG GN_OOST GN GN GN R G SM_N_RE SM_N_GREEN SM_N_LUE SPI_XS PW M_LE SS PWM_LE GN_ GN_RG GN_OOST GN GN GN R G SM_N_RE SM_N_GREEN SM_N_LUE LPISQ 0 LPISQ 0 LPISQ 0 oeker Stieg - ukrug LGeval Mainboard: I/O: stepper motors Size ocument Number Rev 00-00 P Monday, May 0, 00 ate: Sheet o f
ISP_TRL[..0] ISP_TRL[..0] E HSYN EVSYN F SEL ISP_TRL0 ISP_TRL ISP_TRL TSIG[..0] TSIG[..0] I[..0] HOST_SPI[..0] _N[..0] I[..0] HO ST_SPI[..0] _N[..0] I0 I HOST_SPI0 HOST_SPI HOST_SPI HOST_SPI _N0 _N _N _N _N _N _N _N _N I _SL I _S HOST_SK HOST_XS HOST_O H OST_I _LRM_0 PW M_O LG P SW 0 S000 PW M_O PW M_O PW M_O PW M_O PW M_O LG P V RN0 0kx SW 0 S000 TSIG0 TSIG TSIG TSIG TSIG TSIG TSIG TSIG TSIG TSIG TSIG0 TSIG PW M_O0 PW M_O PW M_O PW M_O PW M_O PW M_O PW M_O PW M_O PW M_O PW M_O PW M_O0 PW M_O PW M_O PW M_O[..0] PW M_O[..0] LG_JTG[..0] LG_JTG[..0] SOUN [..0] SOUN[..0] LG_JTG0 LG_TRST_N LG_JTG LG_TMS LG_JTG LG_TK LG_JTG LG_TI LG_JTG LG_TO P Label! PW M_O LG P SW 0 S000 PW M_O LG P SW 0 S000 SG SO UN0 SO UN G PIO0 G PIO G PIO G PIO G PIO GPIO [..0] GPIO[..0] PW M_O LE_UX# LE_UX# V V V0 00 00n V V X0 LG_TRST_N LG_TMS LG_TK LG_TI LG_TO 0 TSM-0-0-L-V--P PW M_O PW M_O PW M_O PW M_O PW M_O PW M_O X00 0 0 PW M_O0 PW M_O PW M_O PW M_O PW M_O PW M_O0 PW M_O 0 00n G PIO0 G PIO G PIO EVSYN SG X0 0 TSM-0-0-L-V--P G PIO G PIO E HSYN F SEL 0 00n FTSH-0-0-L-V--P V V H OST_I HOST_O R0 R0 R0 R0 NP NP I _SL I _S HOST_SK HOST_XS _N _N _N _N X0 0 TSM-0-0-L-V--P X0 0 _N0 _N _N _N _LRM_0 0 00n TSIG0 TSIG TSIG TSIG TSIG TSIG0 X0 0 0 FTSH-0-0-L-V--P TSIG TSIG TSIG TSIG TSIG TSIG TSM-0-0-L-V--P oeker Stieg - ukrug LGeval Mainboard: I/O: extension Size ocument Number Rev 00-00 P Monday, May 0, 00 ate: Sheet o f