EE4-Fall 2008 Digital Integrated Circuits Lecture VTCs and Delay Lecture # Announcements No lab today, Mon., Tues. Labs restart next week Midterm # Tues. Oct. 7 th, 6:30-8:00pm in 05 Northgate Exam is open notes, book, calculators, etc. Midterm review session: Monday am- 2pm, Kroeber 55 2 Lecture # 2
Class Material Last lecture MOS capacitance Today s lecture Using the MOS models: VTCs and Delay Reading (5.-5.3, 5.4.2) 3 Lecture # 3 CMOS Inverter VTC 4 Lecture # 4
The CMOS Inverter V DD W p = βw n V in W n 5 Lecture # 5 PMOS Load Lines For DC VTC, I Dn = I Dp Graphically, looking for intersections of NMOS and PMOS IV characteristics To put IV curves on the same plot, PMOS IV is flipped since V DSp = V DD Also, V GSp = V dd -V in I I Dn V in = 2.5 V in =.5 V in = 0 V in =.5 I Dp I Dn V in= 0 V in =.5 (=V DSn ) V DSp 6 Lecture # 6
CMOS Inverter Load Characteristics I Dn V in = 0 V in = 2.5 PMOS V in = 0.5 V in = 2 NMOS V in =.5 V in = V in =.5 V in = V in = 2 V in =.5 V in = V in = 0.5 V in = 2.5 V in = 0 7 Lecture # 7 CMOS Inverter VTC NMOS off PMOS res 0.5.5 2 2.5 NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off 0.5.5 2 2.5 V in 8 Lecture # 8
CMOS Inverter VTC NMOS off PMOS res 0.5.5 2 2.5 NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat NMOS res PMOS off 0.5.5 2 2.5 V in 9 Lecture # 9 Switching Threshold as a Function of Transistor Ratio.8.7.6.5 I ( V ) = I ( V ) dn M dp M V (V) M.4.3.2. 0.9 0.8 0 0 0 W /W p n 0 0 Lecture #
Switching Threshold as a Function of Transistor Ratio.8.7.6 V (V) M.5.4.3.2. 0.9 * * ( ) ( ) k V V V = k V V V V n D, VSATn M Tn p D, VSATp DD M Tp Solving for V V M M yields: ( Tp ) V + r V V k V W = with r = = + r k V Wυ * * Tn DD p VSATp pυsatp n VSATn n satn 0.8 0 0 0 W /W p n Lecture # Determining V IH and V IL V OH V M V in V OL V IL V IH A simplified approach 2 2 Lecture #
Gain as a function of VDD 2.5 0.2 2 0.5 (V).5 (V) 0. 0.5 0 0 0.5.5 2 2.5 V (V) in 0.05 Gain=- 0 0 0.05 0. 0.5 0.2 V (V) in 3 3 Lecture # Impact of Sizing 2.5 (V) 2.5 Wider NMOS Wider PMOS Symmetrical 0.5 0 0 0.5.5 2 2.5 V in (V) 4 4 Lecture #
Impact of Process Variations 2.5 (V) 2.5 Fast NMOS Slow PMOS Nominal Fast PMOS Slow NMOS 0.5 0 0 0.5.5 2 2.5 V in (V) 5 5 Lecture # CMOS Switching Delay 6 6 Lecture #
MOS Transistor as a Switch Discharging a capacitor We modeled this with: R C i i = i D D = D ( v ) DS dv C dt DS C t p = ln (2) RC 7 7 Lecture # MOS Transistor as a Switch Saw that real transistors aren t exactly resistors Look more like current sources in saturation Two questions: Which region of IV curve determines delay? How can that match up with the RC model? 8 8 Lecture #
Transistor Driving a Capacitor With a step input: V DD V DD/2 I D V GS = V DD V VSAT V DD /2 V DD V DS Transistor is in (velocity) saturation during entire transition from V DD to V DD /2 9 9 Lecture # Switching Delay In saturation, transistor basically acts like a current source: V OUT V OUT I DSAT C V DD V DD /2 t p t V OUT = V DD -(I DSAT /C)t t p = C(V DD /2)/I DSAT 20 20 Lecture #
Switching Delay (with Output Conductance) Including output conductance: V OUT I DSAT /(λi DSAT ) C OUT -t ( C λi DSAT ) ( DD + ) e V = V λ - λ For small λ: t p + CV ( DD 2) ( λv ) I DD DSAT 2 2 Lecture # RC Model Transistor current not linear on V OUT how is the RC model going to work? Look at waveforms: Voltage looks like a ramp for RC too V OUT 2.5 2.3 2..9.7.5 NMOS.3. RC 0.9 0 0.2 0.4 0.6 0.8 t/τ 22 22 Lecture #
Finding Req Match the delay of the RC model with the actual delay: p CV ( DD 2) ( + λv ) I DD t = t DSAT p, RC = ln( 2 ) ReqC ( VDD 2) Req = ln( 2)( + λv ) DD I DSAT Often just: R eq VDD 2ln2 I ( ) DSAT Note that the book uses a different method and gets 0.75 V DD /I DSAT instead of ~0.72 V DD /I DSAT. Why did we do it this way vs. the book s method? 23 23 Lecture # The Book s s Method 24 24 Lecture #
The Transistor as a Switch 7 x 05 6 5 R eq (Ohm) 4 3 2 0 0.5.5 2 2.5 V (V) DD 25 25 Lecture # The Transistor as a Switch 26 26 Lecture #