Lecture 4: CMOS review & Dynamic Logic Reading: ch5, ch6 Overview CMOS basics Power and energy in CMOS Dynamic logic 1
CMOS Properties Full rail-to-rail swing high noise margins Logic levels not dependent upon the relative device sizes ratioless Always a path to VDD or GND in steady state low output impedance ~ kω Extremely high input resistance nearly zero steady-state input current No direct path steady state between power and ground no static power dissipation (but leakage) Propagation delay: function of load capacitance and resistance of transistors D ~ f(c,r) CMOS CMOS is the dominant circuit family due to: No static power consumption Ease of design Robust to variations and noise Etc
The CMOS Inverter: A First Glance V DD V in V out C L First DC analysis, then transient analysis CMOS Inverter N Well V DD V DD PMOS l PMOS Contacts In Out In Out Metal 1 NMOS Polysilicon NMOS GND 3
Two Inverters Share power and ground Abut cells V DD Connect in Metal CMOS Inverter First-Order DC Analysis V DD V DD V out R p V out V OL = 0 V OH = V DD V M = f(r n, R p ) R n V in = V DD V in = 0 4
CMOS Inverter VTC V out NMOS off PMOS res 0.5 1 1.5.5 NMOS sat PMOS res NMOS sat PMOS sat NMOS res PMOS sat Noise Margins? NMOS res PMOS off 0.5 1 1.5.5 V in CMOS Inverter: Transient Response C L : C diff, C wire, C g V DD V DD R p t phl = f(r on.c L ) = 0.69 R on C L V out V out C L R n C L -ln(0.5) V in = 0 (a) Low-to-high V in = V DD (b) High-to-low How do is R on calculated? 5
Fast gate Transient response t p = f(r on, C L ) C L : : C diff, C wire, C g Fast gate Lower C L : small size, short wire, smaller gate input cap (area) Smaller R on (bigger size or width): increase W/L ratio It is nonlinear depend on gate operation (lin, sat, etc ) CMOS Performance Analysis Propagation delay: t 0.69R C t 0.69R C phl eqn L plh eqp L Average the large signal resistance at endpoints of voltage transition of concern (0-50%) At 0% V/I is Vdd/Idsat At 50% V/I is (Vdd/)/(a*Idsat) where a<1 6
M V (V) Switching Threshold as a function of Transistor Ratio 1.8 1.7 1.6 1.5 1.4 1.3 1. V M rvdd 1 r 1.1 1 0.9 0.8 10 0 10 1 W p /W n Determining V IH and V IL V out V OH V M V in V OL V IL V IH A simplified approach 7
V out (V) V out (V) V out (V) Impact of Process Variations.5.5 1.5 1 0.5 V out (V) 1.5 1 0.5 Good NMOS Bad PMOS Nominal Good PMOS Bad NMOS 0 0 0.5 1 1.5.5 V (V) in 0 0 0.5 1 1.5.5 V in (V) What is good device - Smaller oxide thickness, smaller length - Higher width, smaller threshold, etc Gain as a function of VDD (Vdd scaling).5 0. 0.15 Subthreshold 1.5 1 0.1 0.5 0 0 0.5 1 1.5.5 V (V) in 0.05 Gain=-1 Lowering VDD - Slower - Sensitive to variations - Sensitive to external noise 0 0 0.05 0.1 0.15 0. V (V) in kt T ( 5 mv ) q Thermal noise 8
CMOS Inverter Propagation Delay Approach 1 V DD t phl = C L V swing / I av V out ~ C L I av C L k n V DD V in = V DD CMOS Inverter Propagation Delay Approach V DD t phl = f(r on.c L ) = 0.69 R on C L V out V out ln(0.5) R on C L 1 V DD 0.5 0.36 V in = V DD R on C L t 9
CMOS Inverters V DD PMOS In Out 1. m m =l Metal1 Polysilicon NMOS GND Capacitance (C L ) 10
Miller Effect A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground, whose value is two times the original value. C C W gd GD0 MOS Capacitances Gate to channel cap Drain to bulk and source to bulk (junction) cap Overlap cap, C gd0 and C gs0 W, L, AD, PD, AS, PS x j W Bottom Side wall L S Channel-stop implant A 1 N Side wall Source N D Substrate N A Channel Capacitance parameters for book s 0.5μm process 11
V out (V) A first-order RC network R v out v in C t p = ln () t = 0.69 RC = 0.69 R eq C L Transient Response 3.5? If a 0.9, then R eq =0.8*Vdd/Idsat 1.5 t p = 0.69 C L (R eqn +R eqp )/ 1 t plh t phl 0.5 0-0.5 0 0.5 1 1.5.5 t (sec) x 10-10 1
t p (normalized) Delay as a function of V DD 5.5 5 4.5 4 3.5 3.5 1.5 t phl CL 0.5 ( W / L ) k V ' n n DSATn t 0.69* R * C phl eq L 0.69*(0.8* V / I )* C dd dsat L 1 0.8 1 1. 1.4 1.6 1.8..4 V (V) DD Design for Performance (Speed) Keep capacitances small (reduce C L ) Compact layout, good placement (short wires) Keep drain diffusion areas as small as possible Increase transistor sizes to match load Increase W/L ratio Watch out for self-loading! Increase C L and C gate Increase V DD (????) Not usually possible due to reliability and power penalties t P C kv ~ L n DD t P CV I ~ L DD 13
t p (sec) t p (sec) NMOS/PMOS ratio 5 x 10-11 4.5 4 tplh tphl tp PMOS size up Improve t plh Larger cap Degrade t phl 3.5 t P ( tplh tphl ) b = W p /W n 3 1 1.5.5 3 3.5 4 4.5 5 b b Cw opt r(1 ) 1.9 C C dn1 gn Device Sizing 3.8 x 10-11 3.6 (for fixed load) C C C L int ext 3.4 3. 3.8.6.4. t 0.69 R ( C C ) p eq int ext C Cext 0.69 ReqC (1 ) t (1 ) C ext int p0 Cint 4 6 8 10 1 14 S int C int : self-loading C diff, C gd C ext : fanout + C w Self-loading effect: Intrinsic capacitances dominate 14
Inverter Chain One INV Sizing delay but, input cap. In Out C L If C L is given: - How many stages (N) are needed to minimize the delay? - How to size (f) the inverters? May need some additional constraints. Inverter Delay Minimum length devices, L=0.5mm Assume that for W P = W N =W same pull-up and pull-down currents approx. equal resistances R N = R P approx. equal rise t plh and fall t phl delays Analyze as an RC network 1 1 WP WN RP Runit Runit RN RW W unit W unit W W Delay (D): t phl = (ln ) R N C L t plh = (ln ) R P C L W Load for the next stage: Cgin 3 Cunit W unit 15
Inverter with Load Delay R W C L R W Load (C L ) t p = k R W C L k is a constant, equal to 0.69 Assumptions: no load zero delay W unit = 1 Inverter with Load C P = C unit W Delay W C int C L D int C N = C unit Load Delay = kr W (C int + C L ) = kr W C int + kr W C L = kr W C int (1+ C L /C int ) = Delay (Internal) + Delay (Load) 16
Delay Formula Delay ~ R W C int C L t p kr W C int 1 C / C t 1 f / L int p0 C int = C gin with 1 ; intrinsic output capacitance C L =C ext (=fanout + C W ) f = C L /C gin : effective fanout R = R unit /W ; C int =WC unit t p0 = 0.69R unit C unit intrinsic or unloaded delay Apply to Inverter Chain In t P Out 1 N C L t p = t p1 + t p + + t pn t p t pj ~ R unit C unit Cgin, j1 1 Cgin, j N C 1 i C N gin, j1 t p j t, p0, C gin, N 1 j1 1 gin, j C L 17
Optimal Tapering for Given N Delay equation has N - 1 unknowns, C gin, C gin,n Minimize the delay, find N - 1 partial derivatives Result: C gin,j+1 /C gin,j = C gin,j /C gin,j-1 f j =f j+1 Size of each stage is the geometric mean of two neighbors C C C gin, j gin, j1 gin, j1 - each stage has the same effective fanout (f=c out /C in ) - each stage has the same delay (t pi = t pi+1 ) Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: N CL f F F is the overall eff. fanout C gin,1 Effective fanout of each stage: f N F Minimum path delay, where N is # of stages t p Nt p0 1 N F / 18
Example In C 1 1 f f Out C L = 8 C 1 C L /C 1 has to be evenly distributed across N = 3 stages: F f C L C 1 3 8 8 Optimum Number of Stages For a given load, C L and given input capacitance C in Find optimal sizing f t p Nt t C f p0 p L F C t ln F 1/ N p0 f F / 1 t p0 For = 0, f = e, N = lnf in f N C in ln F with N ln f ln f ln F ln f 1 f 0 ln f f ln f exp 1 f 19
Normalized delay Optimum Effective Fanout ( f ) Optimum f for given process defined by f exp 1 f f opt = 3.6 for =1 Impact of Self-Loading on tp No Self-Loading, =0 C L =fan-out With Self-Loading =1 u/ln(u) 60.0 40.0 N=ln(F) f=e=.7188 x=10,000 x=1000 0.0 x=100 x=10 0.0 1.0 3.0 5.0 7.0 u f f opt =4 0
Normalized delay: function of F t p Nt p0 1 N F / f opt Buffer Design (γ = 1) N f t p 1 64 1 64 65 1 8 64 8 18 1 4 16 64 3 4 15 1.8 8.6 64 4.8 15.3 1
Fast Complex Gates: Design Techniques Isolating fan-in from fan-out using buffer insertion Logic Effort more detail in later time Straightforward (back of envelope) technique to estimate delay of CMOS circuit Ivan E. Sutherland, Robert F. Sproull, and David F. Harris (1999). Logical Effort: Designing Fast CMOS Circuits. Morgan Kaufmann. ISBN 1558605576. http://books.google.com/books?id=hgvwzqmqyp0c&pg=p P1&ots=OA5TMYJeFS&dq=logical+effort+cmos&sig=rxgvRW 0PaIe8oMLSGr5gQ8B0des#v=onepage&q=& http://en.wikipedia.org/wiki/logical_effort
Input Pattern Effects on Delay Delay is dependent on the pattern of inputs Low to high transition Both inputs go low Delay is 0.69*R p /C L One input goes low Delya is 0.69*R p C L High to low transition Both inputs go high Delay is 0.69*R n C L Transistor Sizing 3
Sizing a Complex CMOS gate Fast Complex Gates: Design Techniques Transistor ordering Delay determined by time to discharge C L, C 1, and C Delay determined by time to discharge C L, 4
Power and Energy in CMOS Power and Energy Figures of Merit (FOM) Power consumption in Watts Determines battery life in hours Ex) Laptop battery rated at 65W-hr Peak power Determines power and ground wiring requirements Sets packaging limits (plastic vs. ceramic) Energy in units of Joules Energy = power * time (E=Pt) Joules = Watts * seconds Lower energy means less power to perform a computation at the same frequency 5
Where Does Power Go in CMOS? Almost zero static power consumption!!! (except leakage) Dynamic power consumption Charging and discharging of capacitors Short-circuit currents During switching transients, currents flows between Vdd and GND Not dominants (@low Vdd) typically assumed to be ~10% of dynamic power Static power consumption (leakage) Due to non-ideal switches Leaking diodes and transistors Dynamic Static Becoming important @ short L and lower V t Dynamic Power Dissipation Vdd Vin Vout L H C L L H CV L DD H L Energy/transition = E N + E P = C L * V dd Power = E/t = Energy/transition * f = C L * V dd * f Not a function of transistor sizes! NO! C L is function of device size Need to reduce C L, V dd, and f to reduce power. 6
Switching Activity, α sw Let f sw = α sw *f clock, since we usually know clock frequency of a design (e.g., 3 GHz core Duo) 0 < α sw <1 For α sw = 0, the circuit never switches so no dynamic power is consumed For α sw = 1, the node switches as often as the clock (the circuit cannot switch more often than this) so f sw = f clock More cases somewhere in between Lower α sw lower power α sw = 0.5 (5%) Low Energy-Power Design Techniques Switching activity: Design, architecture Supply Voltage: Voltage scaling P CV f dyn DD Capacitance: Wire, gate size, Fan-out Frequency Clock speed Does not dependent(directly) on size Does not dependent on switching delay No switching no P dyn consumption 7
Fundamental Tradeoff: Power vs. Delay t P C kv ~ L n DD P CV f dyn DD Short Circuit Currents Vdd Vin I SC Vout C L 0.15 IVDD (ma) 0.10 0.05 0.0 1.0.0 3.0 V in (V) 4.0 5.0 Non-ideal T rise, T fall When both tr. on Imax depends on saturation current 8
Dynamic Short Circuit Power During input switching, both NMOS and PMOS are ON for a small amount of a time Some current is lost meaning it s not use to charge/discharge the capacitor, but flows to the other supply rail t sc : Duration of input signal I peaktsc I peaktsc E V V t V I P t V I f C V f dp DD DD sc DD peak dp sc DD peak sc DD I peak : size, ratio between input and output slopes (C L ) Impact of C L on short-circuit current 9
How to keep Short-Circuit Currents Low? Short circuit current goes to zero if t fall >> t rise, but can t do this for cascade logic, so... Minimizing Short-Circuit Power 8 7 6 5 Vdd =3.3 P norm 4 3 Vdd =.5 1 Vdd =1.5 0 0 1 3 4 5 t /t sin sout Less important in deep submicron tech. V DD 1 30
Leakage (Static Power Consumption) Ideally, no static current But, not completely OFF Vdd No switching Pstatic VDDIoff 0 Vout Drain Junction Leakage Sub-Threshold Current = V dd Leakage becomes important in modern CMOS Wasted energy Sub-Threshold should be Current avoided Dominant as much Factor as possible More complicated Sub-threshold current one of most compelling issues in low-energy circuit design! Reverse-Biased Diode (Junction)Leakage GATE p + p+ N Reverse Leakage Current + - V dd I DL = J S A Temperature!!! S = JS 1-5pA/mm = 10-100 pa/mm for a 1.mm at 5 CMOS for technology 0.5mm CMOS JS doubles for every 9! double 60x with at 85 every 90.6-6nA/um o C increase in temperature ~6mW (1mil. Gates) 31
Subthreshold Leakage Component I sub =I off Subthreshold Swing (S s ): mv/decade Note log scale on y-axis Off-current (I off ) defined as how much current a device conducts when V gs = 0V [and V ds =V dd ] Leakage control is critical for low-voltage operation (low V DD low V t ) Example Calculation I A m off V / 10 / *10 th S m m s Subthreshold swing (S s ) is around 80-100mV/decade Let V th be 0.3V and S s = 100mV/decade I off = 10nA/um Assume 10 7 inverters in a design (not a good design ) with W n = 1um Total I off = 10 7 *10nA = 100mA = 0.1A P static = V*100mA = 0.W 3
Power in CMOS Principles for Power Reduction P P P P C V f V I tot dyn dp stat L DD DD leak Prime choice: Reduce voltage! (V) Recent years have seen an acceleration in supply voltage reduction Design at very low voltages still open question (0.6 0.9 V by 010!) 45nm tech. still use 1.0V or 1.V Reduce switching activity (α) Reduce physical capacitance (C L ) Device Sizing: for F=0 f opt (energy)=3.53, f opt (performance)=4.47 Reduce leakage current (I leak ) 33
Delay, Energy, and Power Metrics Power-Delay Product (PDP) Average energy consumed per power switching event CV L PDP Pavt p CLVDD fmaxt p Energy-Delay Product (EDP) CV EDP PDP t P t t DD L DD p av p p Summary of Power in CMOS Power reduction is as important as increasing speed in IC design today Three major components of power in CMOS Dynamic: charging capacitors dominant Short-circuit: small, typically ignore Static: subthreshold leakage, growing fast P P P P C V f V I tot dyn dp stat L DD DD leak 34
Summary and Next time CMOS is the dominant circuit family due to: No static power consumption Ease of design Robust to variations and noise Inverter propagation delay Dynamic power consumption Leakage is becoming important Short channel length (L=45nm, 3nm, nm ) Low V t Next time: Combinational Logic design in CMOS Static vs. Dynamic Logical effort t C L P ~ kv n DD P CV f dyn DD 35