- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis
Important! Labs start next week You must show up in one of the lab sessions next week If you don t show up you will be dropped from the class» Unless you let me know that you still want to be in the class Homework will be posted later today. Due next Thursday, February 6. Design Rules Jan M. Rabaey
3D Perspective Polysilicon Aluminum Design Rules Interface between designer and process engineer Guidelines for constructing process masks Unit dimension: Minimum line width» scalable design rules: lambda parameter» absolute dimensions (micron rules) 3
CMOS Process Layers Layer Well (p,n) Active Area (n+,p+) Select (p+,n+) Polysilicon Metal Metal Contact To Poly Contact To Diffusion Via Color Yellow Green Green Red Blue Magenta Black Black Black Representation Layers in 0.5 µm CMOS process 4
Intra-Layer Design Rules Same Potential Different Potential Well Active Select 0 3 0 or 6 3 9 Contact or Via Hole Polysilicon Metal Metal 3 3 4 3 Transistor Layout Transistor 3 5 5
Vias and Contacts Metal to Active Contact Via Metal to Poly Contact 4 5 3 Select Layer 3 Select 3 3 5 Substrate Well 6
CMOS Inverter Layout GND In V DD A A Out (a) Layout A A n p-substrate Field n + p + Oxide (b) Cross-Section along A-A Layout Editor 7
Design Rule Checker poly_not_fet to all_diff minimum spacing = 0.4 um. Sticks Diagram V DD 3 In Out Dimensionless layout entities Only topology is important Final layout generated by compaction program GND Stick diagram of inverter 8
CMOS Inverter MOS Transistor Jan M. Rabaey What is a Transistor? A MOS Transistor A Switch! V GS V GS V T S Ron D 9
NMOS and PMOS NMOS Transistor PMOS Transistor V GS >0 G V GS <0 G S D S D The CMOS Inverter: A First Glance V DD V in V out C L 0
CMOS Inverter N Well V DD V DD PMOS λ PMOS Contacts In Out In Out Metal NMOS Polysilicon NMOS GND Two Inverters Share power and ground Abut cells V DD Connect in Metal
Switch Model of CMOS Transistor V GS R on V GS < V T V GS > V T CMOS Inverter First-Order DC Analysis V DD V DD V out R p V out V OL = 0 V OH = V DD V M = f(r n, R p ) R n V in 5 V DD V in 5 0
CMOS Inverter: Transient Response V DD V DD R p t phl = f(r on.c L ) = 0.69 R on C L V out V out C L C L R n V in 5 0 (a) Low-to-high V in 5 V DD (b) High-to-low CMOS Properties Full rail-to-rail swing Symmetrical VTC Propagation delay function of load capacitance and resistance of transistors No static power dissipation Direct path current during switching 3
The MOS Transistor Polysilicon Aluminum MOS Transistors - Types and Symbols D D G G S NMOS Enhancement D S NMOS Depletion D G G B PMOS Enhancement S S NMOS with Bulk Contact 4
Threshold Voltage: Concept S V GS + G D n + n + n-channel p-substrate Depletion region B The Threshold Voltage Threshold Fermi potential φ F is approximately - 0.6V for p-type substrates γ the body factor V T0 is approximately 0.45V for our process 5
The Body Effect 0.9 0.85 0.8 0.75 0.7 V T (V) 0.65 0.6 0.55 0.5 0.45 0.4 -.5 - -.5 - -0.5 0 V (V) BS The Drain Current Charge in the channel is controlled by the gate voltage: Drain current is proportional to charge and velocity: 6
The Drain Current Combining velocity and charge: Integrating over the channel: Transconductance: Transistor in Linear Linear (Resistive) mode S V GS G V DS D I D n + V(x) + n + L x p-substrate B MOS transistor and its bias conditions 7
Transistor in Saturation V GS G V DS > V GS - V T S D n+ - V GS - V T + n+ Pinch-off Saturation For V GD < V T, the drain current saturates ID kn = W L ( V V ) GS T Including channel-length modulation ID kn W = GS T L ( V V ) ( + λv ) DS 8
Modes of Operation Cutoff: V GS < V T I D = 0 V T < V GS ; V GS V T > V DS Resistive: k I = n D Saturation: W L ( V V ) GS V DS T VDS V T < V GS ; V GS V T < V DS ID kn = W L ( V V ) GS T Current-Voltage Relations A Good Ol Transistor -4 x 0 6 VGS=.5 V I D (A) 5 4 3 Resistive Saturation VGS=.0 V V DS = V GS -V T VGS=.5 V Quadratic Relationship VGS=.0 V 0 0 0.5.5.5 V DS (V) 9
A model for manual analysis Current-Voltage Relations The Deep-Submicron Era -4.5 x 0 Early Saturation VGS=.5 V I D (A).5 VGS=.0 V VGS=.5 V Linear Relationship 0.5 VGS=.0 V 0 0 0.5.5.5 V DS (V) 0
Velocity Saturation υ n (m/s) υ sat = 0 5 Constant velocity Constant mobility (slope = µ) ξ c =.5 ξ (V/µm) Velocity Saturation I D Long-channel device V GS = V DD Short-channel device V DSAT V GS -V T V DS
I D versus V GS 6 x 0-4.5 x 0-4 5 4 quadratic.5 linear I D (A) 3 I D (A) 0 0 0.5.5.5 V GS (V) Long Channel 0.5 quadratic 0 0 0.5.5.5 V GS (V) Short Channel I D versus V DS I D (A) 6 x 0-4 5 4 3 VGS=.5 V Resistive Saturation VGS=.0 V V DS = V GS -V T VGS=.5 V I D (A) -4.5 x 0.5 VGS=.5 V VGS=.0 V VGS=.5 V VGS=.0 V 0.5 VGS=.0 V 0 0 0.5.5.5 V DS (V) Long Channel 0 0 0.5.5.5 V DS (V) Short Channel
Including Velocity Saturation Approximate velocity: And integrate current again: In deep submicron, there are four regions of operation: () cutoff, () resistive, (3) saturation and (4) velocity saturation Regions of Operation Long Channel Short Channel 3
An Unified Model for Manual Analysis G S D B Regions of Operation -4 x 0.5 V DS =V DSAT.5 Linear Velocity Saturated I D (A) 0.5 V DSAT =V GT V DS =V GT Saturated 0 0 0.5.5.5 V (V) DS 4
A PMOS Transistor 0 x 0-4 VGS = -.0V -0. VGS = -.5V -0.4 I D (A) -0.6 VGS = -.0V Assume all variables negative! -0.8 VGS = -.5V - -.5 - -.5 - -0.5 0 V DS (V) Transistor Model for Manual Analysis 5
The Transistor as a Switch V GS V T S Ron I D D V GS = V DD R mid R 0 V DD / V DD V DS The Transistor as a Switch 7 x 05 6 5 R eq (Ohm) 4 3 0 0.5.5.5 V (V) DD 6
The Transistor as a Switch Future Perspectives 5 nm MOS transistor (Folded Channel) 7