In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Similar documents
74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

74HC2G08-Q100; 74HCT2G08-Q100

74HC3G04; 74HCT3G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Triple inverter

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74HC2G02; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. 4. Marking. Dual 2-input NOR gate

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

Triple inverting Schmitt trigger

2-input EXCLUSIVE-OR gate

74AHC2G126; 74AHCT2G126

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

74AHC1G14; 74AHCT1G14

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC2G125; 74HCT2G125

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74AHC2G241; 74AHCT2G241

74HC1G14; 74HCT1G14. The standard output currents are half of those of the 74HC14 and 74HCT14.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC30-Q100; 74HCT30-Q100

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

Dual buffer/line driver; 3-state

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

Dual buffer/line driver; 3-state

74HC132-Q100; 74HCT132-Q100

The 74LV08 provides a quad 2-input AND function.

74HC1G32-Q100; 74HCT1G32-Q100

74HC2G14; 74HCT2G14. Dual inverting Schmitt trigger

74HC1G02-Q100; 74HCT1G02-Q100

74AHC1G00; 74AHCT1G00

Low-power dual Schmitt trigger inverter

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger

74HC153-Q100; 74HCT153-Q100

Triple inverting Schmitt trigger with 5 V tolerant input

7-stage binary ripple counter

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

The 74LVC1G02 provides the single 2-input NOR function.

74HC10; 74HCT General description. 2. Features and benefits. 3. Ordering information. Triple 3-input NAND gate

74HC151-Q100; 74HCT151-Q100

The 74AXP1G04 is a single inverting buffer.

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

NXP 74HC_HCT1G00 2-input NAND gate datasheet

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

The 74LV08 provides a quad 2-input AND function.

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74HC280; 74HCT bit odd/even parity generator/checker

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

2-input single supply translating NAND gate

Low-power configurable multiple function gate

74HC03-Q100; 74HCT03-Q100

74HC1G125; 74HCT1G125

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

4-bit magnitude comparator

Low-power configurable multiple function gate

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

Low-power buffer with voltage-level translator

The 74AUP2G34 provides two low-power, low-voltage buffers.

Single Schmitt trigger buffer

74HC153; 74HCT General description. 2. Features and benefits. Dual 4-input multiplexer

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC174; 74HCT174. Hex D-type flip-flop with reset; positive-edge trigger

74HC32-Q100; 74HCT32-Q100

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

74LVC14A-Q100. Hex inverting Schmitt trigger with 5 V tolerant input

74HC08-Q100; 74HCT08-Q100

The 74LVC1G11 provides a single 3-input AND gate.

Dual inverting Schmitt trigger with 5 V tolerant input

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

The 74LVC2G32 provides a 2-input OR gate function.

The 74LV32 provides a quad 2-input OR function.

74AHC1G126; 74AHCT1G126

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Low-power 2-input NAND Schmitt trigger

Single supply translating buffer/line driver; 3-state

Bus buffer/line driver; 3-state

HEF40175B. 1. General description. 2. Features and benefits. 3. Applications. 4. Ordering information. Quad D-type flip-flop

3-to-8 line decoder, demultiplexer with address latches

The 74LVC10A provides three 3-input NAND functions.

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74HC541; 74HCT541. Octal buffer/line driver; 3-state

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

Dual supply configurable multiple function gate

Low-power Schmitt trigger inverter

74AHC14-Q100; 74AHCT14-Q100

74LVC1G17-Q100. Single Schmitt trigger buffer

74AHC1G125; 74AHCT1G125

Low-power triple buffer with open-drain output

74HC365; 74HCT365. Hex buffer/line driver; 3-state

The 74LVC1G11 provides a single 3-input AND gate.

Single dual-supply translating 2-input OR with strobe

Transcription:

Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - NXP N.V. (year). ll rights reserved or Koninklijke Philips Electronics N.V. (year). ll rights reserved Should be replaced with: - Nexperia B.V. (year). ll rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia

Rev. 5 9 December 2013 Product data sheet 1. General description The is a triple inverter with Schmitt-trigger inputs. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of V CC. Schmitt trigger inputs transform slowly changing input signals into sharply defined jitter-free output signals. 2. Features and benefits 3. pplications Wide supply voltage range from 2.0 V to 6.0 V Complies with JEDEC standard no. 7 Input levels: For 74HC3G14: CMOS level For 74HCT3G14: TTL level High noise immunity Low power dissipation Balanced propagation delays Unlimited input rise and fall times Multiple package options ESD protection: HBM JESD22-114E exceeds 2000 V MM JESD22-115- exceeds 200 V Specified from 40 C to+85 C and 40 C to+125 C Wave and pulse shaper for highly noisy environments stable multivibrators Monostable multivibrators

4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74HC3G14DP 40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads; SOT505-2 74HCT3G14DP 74HC3G14DC 40 C to +125 C VSSOP8 body width 3 mm; lead length 0.5 mm plastic very thin shrink small outline package; 8 leads; SOT765-1 74HCT3G14DC 74HC3G14GD 40 C to +125 C XSON8 body width 2.3 mm plastic extremely thin small outline package; no leads; SOT996-2 74HCT3G14GD 8 terminals; body 3 2 0.5 mm 5. Marking Table 2. Marking Type number Marking code [1] 74HC3G14DP H14 74HCT3G14DP T14 74HC3G14DC H14 74HCT3G14DC T14 74HC3G14GD H14 74HCT3G14GD T14 [1] The pin 1 indicator is located on the lower left corner of the device, below the marking code. 6. Functional diagram 1 1Y 3Y 3 2 2Y Y 001aah728 001aah729 mna025 Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Logic diagram (one Schmitt trigger) Product data sheet Rev. 5 9 December 2013 2 of 21

7. Pinning information 7.1 Pinning 74HC3G14 74HCT3G14 74HC3G14 74HCT3G14 1 3Y 1 2 8 7 V CC 1Y 1 1 8 V CC 2 3 6 3 3Y 2 2 3 7 6 1Y 3 GND 4 5 2Y GND 4 5 2Y 001aak036 001aak035 Transparent top view Fig 4. Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8) Fig 5. Pin configuration SOT996-2 (XSON8) 7.2 Pin description Table 3. Pin description Symbol Pin Description 1, 2, 3 1, 3, 6 data input GND 4 ground (0 V) 1Y, 2Y, 3Y 7, 5, 2 data output V CC 8 supply voltage 8. Functional description Table 4. Function table [1] Input n L H Output ny H L [1] H = HIGH voltage level; L = LOW voltage level. Product data sheet Rev. 5 9 December 2013 3 of 21

9. Limiting values Table 5. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +7.0 V I IK input clamping current V I < 0.5 V or V I >V CC + 0.5 V [1] - 20 m I OK output clamping current V O < 0.5 V or V O >V CC +0.5V [1] - 20 m I O output current V O = 0.5 V to V CC +0.5V [1] - 25 m I CC supply current [1] - +50 m I GND ground current [1] 50 - m T stg storage temperature 65 +150 C P tot total power dissipation [2] - 300 mw [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For TSSOP8 package: above 55 C the value of P tot derates linearly with 2.5 mw/k. For VSSOP8 package: above 110 C the value of P tot derates linearly with 8 mw/k. For XSON8 package: above 118 C the value of P tot derates linearly with 7.8 mw/k. 10. Recommended operating conditions Table 6. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 74HC3G14 74HCT3G14 Unit Min Typ Max Min Typ Max V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 - V CC 0 - V CC V V O output voltage 0 - V CC 0 - V CC V T amb ambient temperature 40 +25 +125 40 +25 +125 C Product data sheet Rev. 5 9 December 2013 4 of 21

11. Static characteristics Table 7. Static characteristics Voltages are referenced to GND (ground = 0 V). ll typical values are measured at T amb =25 C. Symbol Parameter Conditions 25 C 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC3G14 V OH HIGH-level V I = V T+ or V T output voltage I O = 20 ; V CC = 2.0 V 1.9 2.0-1.9-1.9 - V I O = 20 ; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 20 ; V CC = 6.0 V 5.9 6.0-5.9-5.9 - V I O = 4.0 m; V CC = 4.5 V 4.18 4.32-4.13-3.7 - V I O = 5.2 m; V CC = 6.0 V 5.68 5.81-5.63-5.2 - V V OL LOW-level V I = V T+ or V T output voltage I O = 20 ; V CC = 2.0 V - 0 0.1-0.1-0.1 V I O = 20 ; V CC = 4.5 V - 0 0.1-0.1-0.1 V I O = 20 ; V CC = 6.0 V - 0 0.1-0.1-0.1 V I O = 4.0 m; V CC = 4.5 V - 0.15 0.26-0.33-0.4 V I O = 5.2 m; V CC = 6.0 V - 0.16 0.26-0.33-0.4 V I I input leakage current V I =V CC or GND; V CC =6.0V - - 0.1-1.0-1.0 I CC supply current per input pin; V CC =6.0V; - - 1.0-10 - 20 V I =V CC or GND; I O =0; C I input capacitance - 2.0 - - - - - pf 74HCT3G14 V OH HIGH-level V I = V T+ or V T output voltage I O = 20 ; V CC = 4.5 V 4.4 4.5-4.4-4.4 - V I O = 4.0 m; V CC = 4.5 V 4.18 4.32-4.13-3.7 - V V OL LOW-level V I = V IH or V IL output voltage I O = 20 ; V CC = 4.5 V - 0 0.1-0.1-0.1 V I O = 4.0 m; V CC = 4.5 V - 0.15 0.26-0.33-0.4 V I I input leakage current V I =V CC or GND; V CC =5.5V - - 0.1-1.0-1.0 I CC supply current per input pin; V CC =5.5V; V I =V CC or GND; I O =0; - - 1.0-10 - 20 I CC additional per input; - - 300-375 - 410 supply current V CC = 4.5 V to 5.5 V; V I =V CC 2.1 V; I O =0 C I input capacitance - 2.0 - - - - - pf Product data sheet Rev. 5 9 December 2013 5 of 21

Table 8. Transfer characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit 74HC3G14 V T+ positive-going threshold voltage V T negative-going threshold voltage Min Typ Max Min Max (85 C) Max (125 C) see Figure 6, Figure 7 V CC = 2.0 V 1.00 1.18 1.50 1.00 1.50 1.50 V V CC = 4.5 V 2.30 2.60 3.15 2.30 3.15 3.15 V V CC = 6.0 V 3.00 3.46 4.20 3.00 4.20 4.20 V see Figure 6, Figure 7 V CC = 2.0 V 0.30 0.60 0.90 0.30 0.90 0.90 V V CC = 4.5 V 1.13 1.47 2.00 1.13 2.00 2.00 V V CC = 6.0 V 1.50 2.06 2.60 1.50 2.60 2.60 V V H hysteresis voltage (V T+ V T ); see Figure 6, Figure 7 and Figure 9 V CC = 2.0 V 0.30 0.60 1.00 0.30 1.00 1.00 V V CC = 4.5 V 0.60 1.13 1.40 0.60 1.40 1.40 V V CC = 6.0 V 0.80 1.40 1.70 0.80 1.70 1.70 V 74HCT3G14 V T+ positive-going see Figure 6, Figure 7 threshold voltage V CC = 4.5 V 1.20 1.58 1.90 1.20 1.90 1.90 V V CC = 5.5 V 1.40 1.78 2.10 1.40 2.10 2.10 V V T negative-going see Figure 6, Figure 7 threshold voltage V CC = 4.5 V 0.50 0.87 1.20 0.50 1.20 1.20 V V CC = 5.5 V 0.60 1.11 1.40 0.60 1.40 1.40 V V H hysteresis voltage (V T+ V T ); see Figure 6, Figure 7 and Figure 8 V CC = 4.5 V 0.40 0.71-0.40 - - V V CC = 5.5 V 0.40 0.67-0.40 - - V Product data sheet Rev. 5 9 December 2013 6 of 21

11.1 Waveforms transfer characteristics V O V I V T+ V T VH V H V T+ V I V O V T mna207 mna208 Fig 6. Transfer characteristic Fig 7. Definition of V T+, V T and V H 2.0 mna031 3.0 mna032 I CC (m) I CC (m) 2.0 1.0 1.0 0 0 2.5 V 5.0 I (V) 0 0 3.0 6.0 V I (V) Fig 8. a. V CC = 4.5 V. b. V CC = 5.5 V. Typical 74HCT3G14 transfer characteristics Product data sheet Rev. 5 9 December 2013 7 of 21

100 mna028 1.0 mna029 I CC (μ) I CC (m) 0.8 0.6 50 0.4 0.2 0 0 1.0 V 2.0 I (V) 0 0 2.5 V 5.0 I (V) a. V CC = 2.0 V b. V CC = 4.5 V 1.6 mna030 I CC (m) 0.8 0 0 3.0 6.0 V I (V) Fig 9. c. V CC = 6.0 V Typical 74HC3G14 transfer characteristics Product data sheet Rev. 5 9 December 2013 8 of 21

12. Dynamic characteristics Table 9. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11. Symbol Parameter Conditions 25 C 40 C to +125 C Unit Min Typ Max Min Max (85 C) Max (125 C) 74HC3G14 t pd propagation delay n to ny; see Figure 10 [1] V CC = 2.0 V - 53 125-155 190 ns V CC = 4.5 V - 16 25-31 38 ns V CC = 6.0 V - 13 21-26 32 ns t t transition time ny; see Figure 10 [2] V CC = 2.0 V - 20 75-95 110 ns V CC = 4.5 V - 7 15-19 22 ns V CC = 6.0 V - 5 13-16 19 ns C PD power dissipation capacitance V I = GND to V CC [3] - 10 - - - - pf 74HCT3G14 t pd propagation delay n to ny; see Figure 10 [1] V CC = 4.5 V - 21 32-40 48 ns t t transition time ny; see Figure 10 [2] V CC = 4.5 V - 6 15-19 22 ns C PD power dissipation capacitance V I = GND to V CC 1.5 V [3] - 10 - - - - pf [1] t pd is the same as t PLH and t PHL [2] t t is the same as t TLH and t THL [3] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V 2 CC f i N+ (C L V 2 CC f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in V; N = number of inputs switching; (C L V 2 CC f o ) = sum of the outputs. Product data sheet Rev. 5 9 December 2013 9 of 21

13. Waveforms n input V I GND V M V M t PHL t PLH V OH ny output V OL 90 % V M V M 10 % t THL t TLH mna722 Fig 10. Measurement points are given in Table 10. V OL and V OH are typical voltage output levels that occur with the output load. The data input (n) to output (ny) propagation delays and output transition times Table 10. Measurement points Type Input Output V M V M 74HC3G14 0.5V CC 0.5V CC 74HCT3G14 1.3 V 1.3 V Product data sheet Rev. 5 9 December 2013 10 of 21

V I negative pulse 0 V 90 % V M 10 % t W V M t f t r t r t f V I positive pulse 0 V 10 % 90 % V M t W V M V CC V CC G VI DUT VO RL S1 open RT CL 001aad983 Fig 11. Test data is given in Table 11. Definitions for test circuit: R T = Termination resistance should be equal to output impedance Z o of the pulse generator. C L = Load capacitance including jig and probe capacitance. R L = Load resistance. S1 = Test selection switch. Test circuit for measuring switching times Table 11. Test data Type Input Load S1 position V I t r, t f C L R L t PHL, t PLH 74HC3G14 GND to V CC 6 ns 50 pf 1 k open 74HCT3G14 GND to 3.0 V 6 ns 50 pf 1 k open Product data sheet Rev. 5 9 December 2013 11 of 21

14. pplication information The slow input rise and fall times cause additional power dissipation, which can be calculated using the following formula: P add =f i (t r I CC(V) +t f I CC(V) ) V CC where: P add = additional power dissipation ( W); f i = input frequency (MHz); t r = input rise time (ns); 10 % to 90 %; t f = input fall time (ns); 90 % to 10 %; I CC(V) = average additional supply current ( ). I CC(V) differs with positive or negative input transitions, as shown in Figure 12 and Figure 13. n example of a relaxation circuit using the 74HC3G14/74HCT3G14 is shown in Figure 14. 200 mna036 ΔI CC(V) (μ) 150 positive-going edge 100 50 0 negative-going edge 0 2.0 4.0 6.0 V CC (V) Fig 12. linear change of V I between 0.1V CC to 0.9V CC. I CC(V) as a function of V CC for 74HC3G14 Product data sheet Rev. 5 9 December 2013 12 of 21

200 mna058 ΔI CC(V) (μ) 150 positive-going edge 100 50 negative-going edge 0 0 2 4 V 6 CC (V) Fig 13. linear change of V I between 0.1V CC to 0.9V CC. I CC(V) as a function of V CC for 74HCT3G14 R C mna035 For 74HC3G14: f = 1 1 -- T 0.8 --------------------- RC For 74HCT3G14: 1 1 f = -- T 0.67 ------------------------ RC Fig 14. For K-factor, see Figure 15 Relaxation oscillator Product data sheet Rev. 5 9 December 2013 13 of 21

Fig 15. K-factor for 74HC3G14 Typical K-factor for relaxation oscillator K-factor for 74HCT3G14 Product data sheet Rev. 5 9 December 2013 14 of 21

15. Package outline TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2 D E X c y H E v M Z 8 5 2 1 ( 3 ) pin 1 index L p θ L 1 4 detail X e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1.1 0.15 0.00 2 3 b p c D (1) E (1) e H E L L p v w y Z (1) θ 0.95 0.75 0.25 0.38 0.22 0.18 0.08 3.1 2.9 3.1 2.9 0.65 4.1 3.9 0.5 0.47 0.33 0.2 0.13 0.1 0.70 0.35 8 0 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT505-2 - - - 02-01-16 Fig 16. Package outline SOT505-2 (TSSOP8) Product data sheet Rev. 5 9 December 2013 15 of 21

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1 D E X c y H E v M Z 8 5 Q 2 1 pin 1 index ( 3 ) L p θ 1 4 detail X L e b p w M 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT max. 1 mm 1 0.15 0.00 2 3 b p c D (1) E (2) e H E L L p Q v w y Z (1) θ 0.85 0.60 0.12 0.27 0.17 0.23 0.08 2.1 1.9 2.4 2.2 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.5 3.2 3.0 0.4 0.40 0.15 0.21 0.19 0.2 0.13 0.1 0.4 0.1 8 0 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT765-1 MO-187 02-06-07 Fig 17. Package outline SOT765-1 (VSSOP8) Product data sheet Rev. 5 9 December 2013 16 of 21

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 3 x 2 x 0.5 mm SOT996-2 D B E 1 detail X terminal 1 index area L 1 e 1 e b 1 4 v w C C B y 1 C C y L 2 L 8 5 X 0 1 2 mm scale Dimensions (mm are the original dimensions) Unit (1) 1 b D E e e 1 L L 1 L 2 v w y y 1 mm max nom min 0.5 0.05 0.00 0.35 0.15 2.1 1.9 3.1 2.9 0.5 0.15 0.6 0.5 1.5 0.1 0.05 0.3 0.05 0.4 0.05 0.1 sot996-2_po Outline version SOT996-2 References IEC JEDEC JEIT European projection Issue date 07-12-21 12-11-20 Fig 18. Package outline SOT996-2 (XSON8) Product data sheet Rev. 5 9 December 2013 17 of 21

16. bbreviations Table 12. cronym CMOS DUT ESD HBM MM bbreviations Description Complementary Metal Oxide Semiconductor Device Under Test ElectroStatic Discharge Human Body Model Machine Model 17. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT3G14 v.5 20131209 Product data sheet - 74HC_HCT3G14 v.4 Modifications: Figure 15 added (typical K-factor for relaxation oscillator). 74HC_HCT3G14 v.4 20131003 Product data sheet - 74HC_HCT3G14 v.3 Modifications: For type numbers 74HC3G14GD and 74HCT3G14GD XSON8U has changed to XSON8. 74HC_HCT3G14 v.3 20090508 Product data sheet - 74HC_HCT3G14 v.2 74HC_HCT3G14 v.2 20031104 Product specification - 74HC_HCT3G14 v.1 74HC_HCT3G14 v.1 20020723 Product specification - - Product data sheet Rev. 5 9 December 2013 18 of 21

18. Legal information 18.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). NXP does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Product data sheet Rev. 5 9 December 2013 19 of 21

Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 18.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Product data sheet Rev. 5 9 December 2013 20 of 21

20. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 pplications............................ 1 4 Ordering information..................... 2 5 Marking................................ 2 6 Functional diagram...................... 2 7 Pinning information...................... 3 7.1 Pinning............................... 3 7.2 Pin description......................... 3 8 Functional description................... 3 9 Limiting values.......................... 4 10 Recommended operating conditions........ 4 11 Static characteristics..................... 5 11.1 Waveforms transfer characteristics......... 7 12 Dynamic characteristics.................. 9 13 Waveforms............................ 10 14 pplication information.................. 12 15 Package outline........................ 15 16 bbreviations.......................... 18 17 Revision history........................ 18 18 Legal information....................... 19 18.1 Data sheet status...................... 19 18.2 Definitions............................ 19 18.3 Disclaimers........................... 19 18.4 Trademarks........................... 20 19 Contact information..................... 20 20 Contents.............................. 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V. 2013. ll rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 9 December 2013 Document identifier: 74HC_HCT3G14