The MC101 is a four bit counter capable of divide by two, five, or ten functions. It is composed of four set reset master slave flip flops. Clock inputs trigger on the positive going edge of the clock pulse. Set or reset input override the clock, allowing asynchronous set or clear. Individual set and common reset inputs are provided, as well as complementary outputs for the first and fourth bits. P D = 0 mw typ/pkg (No Load) f tog = 0 MHz typ t r, t f =.5 ns typ (0% 0%) LOGIC DIAGRAM CDIP 16 L SUFFIX CASE 60 16 1 MARKING DIAGRAMS MC101L AWLYYWW PDIP 16 P SUFFIX CASE 6 16 1 MC101P AWLYYWW 1 PLCC 0 FN SUFFIX CASE 5 101 AWLYYWW DIP PIN ASSIGNMENT A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week ORDERING INFORMATION Device Package Shipping MC101L CDIP 16 5 Units / Rail MC101P PDIP 16 5 Units / Rail MC101FN PLCC 0 6 Units / Rail Pin assignment is for Dual in Line Package. For PLCC pin assignment, see the Pin Conversion Tables on page 1 of the ON Semiconductor MECL Data Book (DL1/D). Semiconductor Components Industries, LLC, 00 January, 00 Rev. 1 Publication Order Number: MC101/D
MC101 BI QUINARY (Clock connected to C and Q connected to C1) COUNTER TRUTH TABLES BCD (Clock connected to C1 and Q0 connected to C) COUNT Q1 Q Q Q0 COUNT Q0 Q1 Q Q 0 L L L L 0 L L L L 1 H L L L 1 H L L L L H L L L H L L H H L L H H L L L L H L L L H L 5 L L L H 5 H L H L 6 H L L H 6 L H H L L H L H H H H L H H L H L L L H L L H H H L L H COUNTER STATE DIAGRAM POSITIVE LOGIC
MC101 ELECTRICAL CHARACTERISTICS Characteristic Power Supply Drain Current Symbol Input Current I inh 1 Output Voltage Logic 1 V OH, (.),,1, (.) Output Voltage Logic 0 V OL, (.),,1, (.) Threshold Voltage Logic 1 V OHA,,1, (.), (.) 1, (.) Threshold Voltage Logic 0 V OLA,,1, (.), (.) 1, (.) Switching Times (50Ω Load) Propagation Delay Clock Delays Test Limits Pin Under 0 C +5 C +5 C Test Min Max Min Typ Max Min Max Unit I E 0 madc 50 0 60 650 0 5 0 10 0 5 0 µadc I inl All 0.5 0.5 0. µadc t 1++ t 1++ t +1+ t ++ t ++ t ++ t 1+ t 1+ t +1 t + t + t + 1 1 Set Delay t 11++ t 11+ Reset Delay t ++ t + Rise Time (0 to 0%) t + t + Fall Time (0 to 0%) t t Counting Frequency f count 1.060 1.060 1.0 1.0 1.00 1.00 1.00 15 15 1. Individually test each input; apply V ILmin to pin under test.. Set all four flip flops by applying pulse. Reset all four flip flops by applying pulse 0.0 0.0 1.65 1.65 1.655 1.655 1.655.... 0.60 0.60 0 0 0.0 0.0 0.0 15 15.5.5.5.5 0 0 0.10 0.10 1.650 1.650 1.60 1.60 1.60.....5.5.5.5 0.0 0.0 1.5 1.5 0.10 0.10 0.10 15 15 0.00 0.00 1.6 1.6 5 5 5 5. 5. 5. 5. to pins 5, 6, 10, and 11 prior to applying test voltage indicated. to pin prior to applying test voltage indicated. Vdc Vdc Vdc Vdc ns MHz
MC101 ELECTRICAL CHARACTERISTICS (continued) NOTE: Each MECL 10,000 series circuit has been designed to meet the dc specifications TEST VOLTAGE VALUES (Volts) shown in the test table, after thermal equilibrium has been established. The circuit @ Test Temperature V IHmax V ILmin V IHAmin V ILAmax V EE is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50 ohm resistor to.0 volts. Test procedures are shown for only one 0 C +5 C 0.0 0.10 1.0 0 1.05 05 00 5 gate. The other gates are tested in the same manner. +5 C 0.00 1.5 1.05 0 Characteristic Symbol Pin TEST VOLTAGE APPLIED TO PINS LISTED BELOW Under (V CC ) Test V IHmax V ILmin V IHAmin V ILAmax V EE Gnd Power Supply Drain Current I E Input Current I inh 1 Output Voltage Logic 1 V OH, (.),,1, (.) Output Voltage Logic 0 V OL, (.),,1, (.) Threshold Voltage Logic 1 V OHA,,1, (.), (.) 1, (.) Threshold Voltage Logic 0 V OLA,,1, (.), (.) 1, (.) 1 I inl All Note 1.,1,1 Switching Times (50Ω Load) Pulse In Pulse Out. V +.0 V Propagation Delay Clock Delays t 1++ t 1++ t +1+ t ++ t ++ t ++ 1 t 1+ t 1+ t +1 1 t + t + t + Set Delay t 11++ t 11+ Reset Delay t ++ t + Rise Time (0 to 0%) t + t + Fall Time (0 to 0%) t t Counting Frequency f count 1. Individually test each input; apply V ILmin to pin under test.. Set all four flip flops by applying pulse. Reset all four flip flops by applying pulse 1 1 1 1 11 11 11 11 1 1 1 to pins 5, 6, 10, and 11 prior to applying test voltage indicated. to pin prior to applying test voltage indicated.
MC101 PACKAGE DIMENSIONS PLCC 0 FN SUFFIX PLASTIC PLCC PACKAGE CASE 5 0 ISSUE C B N Y BRK U D L M Z W D X G1 V VIEW D D Z A R K1 H C G G1 E J T VIEW S VIEW S K F 5
MC101 PACKAGE DIMENSIONS T F A E G D 16 PL B C N CDIP 16 L SUFFIX CERAMIC DIP PACKAGE CASE 60 10 ISSUE T K L M J 16 PL H A G B F C S K D 16 PL T PDIP 16 P SUFFIX PLASTIC DIP PACKAGE CASE 6 0 ISSUE R J L M 6
MC101 Notes
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