DP CoiNel Technology Solutions LLP GND GND GND GND. ETH_RST is connected to P1.28 GND GND GND GND GND GND GND GND GND ED 1. Vcc O 3 GND IOGND 35

Similar documents
CAN 1 CAN 2. CoiNel Technology Solutions LLP GND GND GND GND GND GND J1 JUMPER J2 JUMPER. 100nF. 100nF R2 120 R1 120 VDD 3 CAN1_H CAN2_H

DISPLAY 1 DISPLAY 2 a. a b. a f. a f. b g. c d. c d. 16 x 2 HD44780 BASED ALPHANUMERIC DISPLAY LCD 16 X 2

Design Overview. Page 2 Power,Flash,SDcard User switch,reset switch. Page 3 Ethernet. Page 4 Audio. Page 5 USB. Page 6 JTAG,BOOTSW,LED,Header

CD-DET TP5_CS- LCDPWR RFPWR CHPD5 GP05 GP25 RST5 L13 D12 D11 D10 LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS- LCD_MISO LCD5_MOSI LCD5_SCK SD5_CS-

C uF T16 VDD T15 TMS TMS MCU_PORT_VDD T14 TDO TDO T13 JCOMP JCOMP PF3 T12 PF3 T11 VDDE3 5.0V PF4 T10 PF4 PJ5 PJ5 PF6 PF6 PF9 PF9 5.0V 5.

Headers for all pins sorted by pin no. (unpopulated) TSX-1001 Cortex-M0. Oscillator 44MHz

KEIm Baseboard. PAGE DESCRIPTION 1 Block Diagram, History 2 SoM Connector. 3 LCD Connector. 4 Ethernet. 5 UART 6 Analog 7 Peripheral 8 Power

AS1117M3 or LM1117MPX-ADJ ADJ. C20 0.1uF + C56. + C57 10uF. 10 uf R K 1% R18 GND 10.0K 1%

AS1117M3 or LM1117MPX-ADJ REG_VDD ADJ. C20 0.1uF U6. + C57 10uF R K 1% GND 3.92K 1%

ADC IF1_P IF1_N INT_OSC_EN INT_OSC_EN ADC_PWDN ADC_PWDN INT_OSC_EN ADC_PWDN UC_CTRL[1-2] UC_DATA[0-7] FPGA_PROG[1-5] RF_POWER_DET

Block Diagram. Level Translators USB ICSP. Ethernet PoE. Atmega 32U4. 16MHz. User button Reset 32U4. Headers. Reset. Wi-Fi Module. Leds.

POWER-ON RESET CIRCUIT

Changed in Rev.3. Title. Revision: Size: A4 Number:

AD2_BUSY AD2_DIN AD2_DOUT AD2_/CS AD1_/CS AD1_DOUT AD1_DIN AD_SCLK AD_CCLK AD_OSC_EN AD1_BUSY AD_CONVERT GNDIO - P115

Project: Date. Version. Items V1.01 C C. SIM Technology TITLE DRAWN BY PORJECT. SIM800C+SIM28M_VTS Reference CONTENT VER CHECKED BY SIZE V1.

MSP430F16x Processor

L13X DAUGHTER CARDS TABLE OF CONTENTS REV SL NO. TABLE OF CONTENTS VERSION VERSION HISTORY BLOCK DIAGRAM 4 UART-0 INTERFACE

COVER PAGE, TOP 04 ~ 05 VGA, LED, 7SEGMENT

PS2_B_CLOCK PS2_B_DATA PS2_A_CLOCK PS2_A_DATA UART_C_RXD UART_B_RXD UART_A_RXD UART_C_TXD UART_B_TXD UART_A_CTS UART_A_TXD UART_A_RTS GPIO[0:31]

core Tiny6410.sch DM9000 DM9000-etc.sch AC97 AC97-etc.sch USB HUB USB-HUB.sch Tiny6410SDK 1103

Intel Edison. 7V to 15V Brick Power Supply. 4.4V power supply and battery recharger UART 1 USB 0TG. EDISON BREAKOUT BOARD Title Title page

CP2102 TESTAMATIC SYSTEMS POWER 5V TO 3.3V SECTION PINOUT CHECK DECOUPLING CAPACITORS. Btype USB connector TSPL_PPS_1 2.2

ISA INTERFACE & POWER SELECTION Size Document Number Rev Custom. XR82C684 EVAL BOARD 1.2 Date: Monday, August 13, 2007 DO NOT INSTALL CON_AT62B

Revisions. TWR-MEM Drawn by: Convert into FSL template 9/8/09

THE UNIVERSITY OF NEWCASTLE University Drive Callaghan NSW 2308 Australia

Renesas Starter Kit for RL78/G13 CPU Board Schematics

S08P-LITE. 1 Title Page 2 Block Diagram 3 MCU & Arduino Headers 4 OSBDM & Power Supply 5 On-board Peripherials S08P-LITE. 23-Jun-17. V3.

NOTE: please place R8 close to J1

0603/15p/10v L R/100MHz. 100nF/50V. 100nF/16V. 100nF/50V C105 C106 C108 C107 GND GND GND GND

U1-1 R5F72115D160FPV

ALEX +12VBUS PTC 1A J17 PTT U1B. 126 IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR. IO_VB1N1_9/DIFFIO_L7p/DQS2L/CQ3L/CDPCLK0 RUP3

B0549-SCH-01 RD VEGA STDP4028 (DVI to DPTx) Reference Design PCB# Revision History

For max 243 R2OUT is low when R2IN is disconnected enabling the MAX 489 (RS-485) This will not work if MAX232 is used!

RSC CHIP VDD P05 P03 P01 P04 VDD GND PWM0 AVDD VDD AVDD P0-2 P0-5 P0-1 P0-6 P0-4 P0.3 GND P00. Y1 3.58MHz P00 P01 AGND P01 P00 P02 P02 P07 P0-0 P0-7

Note: Please refer to AX110xx Network SoC Application Design Note for more detailed information.

OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OTG_FS_VBUS OTG_FS_N OTG_FS_P OTG_FS_ID OTG_FS_OC OTG_FS_PWR OLLO_SLEEP OLLO_SLEEP

Realtek Semiconductor Corp. Title RTL8213(M)_FHG_V1.0

3 Different test points used in design: TPx - Test point pad. TPHx - Through Hole Pad Large (for standard 0.1" header). Also used on IO Matrix (IOMx)

FRDM-KL27Z. 1 Title 2 Block Diagram 3 KL27Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Rev Description Date Approved

J1B B1 B3 B5 B7 B9 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B35 B37 B39 B41 B43 B45 B47 B49 B51 B53 B55 B57 VCC VCC USB_DET

ADC_1_AN[5]/SIUL_GPIO[64]/E[0] 49 ADC_0_AN[5]/SIUL_GPIO[66]/E[2] ADC_0_AN[7]/SIUL_GPIO[68]/E[4] ADC_0_AN[8]/SIUL_GPIO[69]/E[5]

Revisions. 2 Notes. 4 FXLC95000CL / MCU Circuit 5 Power and Battery Charger Circuit. KITFXLC95000EVM Drawn by:

Generated by Foxit PDF Creator Foxit Software For evaluation only.

ALEX +12VBUS PTC 1A J17 PTTOUT U1B 3V3 C IO_VB1N1_14/DIFFIO_L10p/FLASH_nCE/nCSO FLAGB NCS0 SLWR RUP3

Host MSP430. dacqs_host_board 12/7/2016 9:26 PM. U1 Value +3V3 AVCC_HOST UART_1_TX UART_1_RX MSP_SCLK UART_2_TX UART_2_RX CUTDOWN_EN MSP_SS

SVS 5V & 3V. isplsi_2032lv

HF SuperPacker Pro 100W Amp Version 3

NXP Automotive S12ZVMBEVB C U S T O M E R E V B

AML7266-H. Feature table. Block Thursday, February 12, 2009 AMLOGIC AML7266-H. Main Chip: Internal: Video: Audio: Interfaces: UART USB HOST RJ45

LED POWER STAGE1 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE2 NOT_EN LED+ PWM LED- 12V. LED Power Stage LED POWER STAGE3 NOT_EN LED+ PWM

#1 10P/DIL NORTH #3 #3 #3 #3 #3 #3 #3 #3 R198 RES0603 RES0603 DNP DNP DNP RES0603 RES0603 RES SDI_N 3-SDO_N 3-ALERT_N 3-CS_N 3-SCLK_N 3-CONV_N

VCC R4 10K ANA1 EXT-A1 EXT-A2 ANA2 C10 10NF/50V C11. DispKey.sch EXT-DATA EXT-SCK LCD-E KEY-E LCD-E. U_SpiUsb SpiUsb.

FREEDOM KE02Z. 1 Title 2 Block Diagram 3 KE02Z MCU. 4 OpenSDA INTERFACE. 5 I/O Headers and Power Supply. Initial Draft 02/01/13

General Description. Features. Kit Contents. MAX32660 EV System Photo

REVISION HISTORY DESCRIPTION INITIAL SCHEMATIC AIY REMOVED ANALOG SWITCHES CHANGED FEEDBACK

XR21B1422/1424 POWER & USB 1.0 Date: Thursday, February 13, 2014

Revisions. TRK-KEA128 Drawn by: Nov Original Release A. INZUNZA

P&E Embedded Multilink Circuitry

LED_POWER_STAGE1 PWM GND ADJ LED- -12V R2 RA. LED Power Stage LED_POWER_STAGE2 PWM GND ADJ LED- -12V R4 RB. LED Power Stage LED_POWER_STAGE3

MT9V128(SOC356) 63IBGA HB DEMO3 Card

Revisions. TWR-LCD-RGB Drawn by: Initial Release 15-JUL-11

SYMETRIX INC th Avenue West Lynnwood, WA USA REV: DATE:

RETICLE 2 NORTH SW2 DPDT SOUTH. LM339A TxD1 Out 11 U2D DEC PULSE 1 FOCUSER-2 3.0V 17 CCD EAST U2A AUX -6 FOCUSER-2 FOCUSER SW1 DPDT

01 TITLE PAGE 02 MCU 03 DEBUG INTERFACE 05 POWER BRIDGE 06 MOSFET DRIVERS / VI SENSING XSKEAZ128REFDES

GR-PEACH(mbed-RZ/A1) Circuit schematic X28

DNI TP25 ORG DNI 0.1UF 12V 47UF DNI DNI WHT DGND1 LM1117MP-3.3/NOPB +V_MTR +V DNI OUT1 OUT ADJ DNI 0.1UF R10 10K DGND 47UF DNI DNI EXLVL DGND DGND

Sirius-Rx-232. Sirius-Tx-232. SIRIUS-Rx. STATUS Prog RC-5. SIRIUS-Rx. Prog RCA-5 DAB-SDA DAB-SCL STAYUS AM-SMETER POWER-ON POWER-ON CE-PLL

Revision History. EFM32PG12 Pearl Gecko STK. Description. Board Function Page. EFM32PG12 Pearl Gecko Starter Kit. Title Page 1.

3JTech PP TTL/RS232. User s Manual & Programming Guide

Virtex 5 FF1760 DUT. Differential SMA Clocks 2X D. Single Ended Socket Clocks 2X. Upstream Connector. Upstream. Power Bus and Switches 5V

05 - Adaptacion Puerto Serie RXD_UC R35 0 DTR_UC R36 0 RI_UC Adaptacion Puerto Serie Señalizacion GSM R37 0 INFO_NETLIGHT R38 0

[1] [1] C7 10nF. C4 10nF SCL [2] SDA [2] CS_SD PWR_PRSNT [4] INT_BTN0 [2] INT_BTN1 [2] LOADER_EN [4] [1] TXLED [1] J11 [1] RST +3V3 RST

PLAY0 CT7601 QFN48 REC ADC REC. Power LDO RCA RCA RCA*2. Ext. MCU RCA*2. SPDIF output. PWM LED x 2 POR. SPDIF input x 1 Flash. connector.

DAC PLAY0 PLAY0 CT7601 DAC REC ADC REC RCA * 2. Power LDO RCA. RCA * 2 SPDIF output x2 RCA RCA RCA. Ext. MCU POR. PWM LED x 2. SPDIF input x 1.

5V_EXT J3-1 J3-1 5CSX_4A_IO39 5CSX_4A_IO37 5CSX_4A_IO40 UART0_CTS 5CSX_4A_IO32 UART0_RTS 5CSX_4A_IO29. 5CSX_IOp0 5CSX_IOn0. 5CSX_IOp1 5CSX_IOn1

RTL8211DG-VB/8211EG-VB Schematic

2 Notes 3 MC9S08LG32CLK 4 Touch Sensors 1 5 Touch Sensors 2 6 Power 7 OSBDM 8 USB COM

POSWD0SWO POKBD0ROW0A GND POSDIO0D3 POLCD0NOE

8V Title SCHEMATIC, 8V89317EVB REV A. Date: Friday, June 14, Power Supply. XTAL Interface. 12.8MHz TCXO/OCXO LED Status IN1 OUT1

C107 C108 C uF/10V Ta. 10uF/10V Ta. 100nF. 100nF. 100nF C106 C111 C110 VCC VCC AVCC (AD0)PA0 (AD1)PA1 (AD2)PA2 (AD3)PA3 (AD4)PA4 (AD5)PA5

A B C D TXD[15:0] TXD10 TXPAR 2.2K R38 RA12 1 RA13 AD10 +3V J98 PHY_INT HSERR R70 PRST TXPAR. ATM Physical Local Bus. Local Bus Interface.

EFM32 Tiny Starter Kit. EFM32 Tiny Starter Kit. Revision History. Page. Board Function. Rev. Description. Title Page 1 A00.

DOCUMENT NUMBER PAGE SECRET

R uF 4.7K VDD5.0 BS 1. 10uH/2A_LPF7030T-100M. 47uF/25V(CAN) 47uF/25V(CAN) 22uF/16V/X5R. 22uF/16V/X5R EC3 EUP K(1%) 0.

All use SMD component if possible

A Power, JTAG, LEDs FPGA_TCK FPGA_TDO FPGA_TMS FPGA_TRST FPGA_TDI nanofip_misc.sch

CLKOUT CLKOUT VCC CLKOUT RESOUT OSCOUT ALE TEST AD0 66 AD2 INT0 INT0 AD INT1 AD INT2/INTA0 AD5 AD7 AD7 INT AD8 AD8 AD10

R5 330K R49 100K Q4 BC549 R12 2K2 U2B TL074 R50 100K R28 3K3. VR7 47KB via J38 R48 100K C BASSDRUM_TRIG. VR6 10K via J39 R29 100K R51 22K Q11 BC559

LO_TX LO_TX MIXER_OUT MIXER_OUT VCC5V VCC5V VCC3V3 VCC3V3 VCC5V_TX VCC5V_TX VCC5V VCC5V VCC12V_TX VCC12V_TX VCC3V3 VCC3V3 AGND

LOAD EITHER U2 OR U4 (NOT BOTH) DEFAULT IS SDRAM (U4) RX MCU

XBee Interface Board XBIB-U-DEV TH/SMT Hybrid

ZCRMZN00100KITG. Crimzon Development Board Kit. Product User Guide. Introduction. Kit Contents. Applying Power to Development Board

XO2 DPHY RX Resistor Networks

VCC 52 VCC 21 AVCC PF0(ADC0) 60 PF1(ADC1) 59 PF2(ADC2) 58 PF3(ADC3) 57 PF4(ADC4/TCK) 56 PF5(ADC5/TMS) 55 PF6(ADC6/TDO) 54 PF7(ADC7/TDI) SCL TXD

ide ide.sch C1-C22 0.1uF

Table of Contents 1 TITLE PAGE

AXM88180-EVB-RTL8211E-1 SMDK2440 Demo Board Schematic Index

USBF USBF.prj. Title: Section: USBF-01. B Designer: Brian Ashelin Date: COMMUNICATIONS COMMUNICATIONS ADC ADC INPUT VCA 4 PAGE 7 PAGE 1 PAGE 5 PAGE 2

SM XBEE MODULE XBEE SMT MODULE NC GND GND RF_SELECT VCC COMM/AD0/DIO0 AD1/DIO1 DOUT/DIO13 AD2/DIO2 DIN/CONFIG/DIO14 DIO12 AD3/DIO3 RESET RTS/DIO6

Transcription:

V K R L FR nf nf Vcc E O MHZ_LK ENET_REF_LK ENET_MIO ENET_M MHZ_LK.K R Y OS_MHz LE_LK LE_SPEE LE_T nf is connected to P. ENET_TX ENET_TX ENET_RS ENET_RX ENET_RX ENET_REF_LK ENET_M ENET_MIO nf ENET_TX ENET_TX ENET_RS ENET_RX ENET_RX ENET_REF_LK ENET_M ENET_MIO R+ nf R R K K R R K R pf pf R T+ T- LE_LK LE_T LE_SPEE LE J T+ T R+ T N G_LE+ Y_LE+ T- R- G_LE- Y_LE- RJ_MGNETIS TX+ RX+ RIS PFOUT V RESERVE RESERVE _ PF T+ T- R+ R- TX- RX- ENET_RS ENET_RX ENET_RX ENET_TX ENET_TX nf nf PFOUT R K R R R R R R R U IO X X IOV M MIO RESET_N LE_LK/N LE_SPEE/N PF RX_LK RX_V/MII_MOE RS/RS_V/LE_FG RX_ER/MIX_EN OL/PHY RX_/PHY RX_/PHY RX_/PHY RX_/PHY IO_ IOV_ P TX_LK TX_EN TX_ TX_ TX_ TX_/SNI_MOE PWR_OWN/T RESERVE RESERVE RESERVE RESERVE RESERVE K R LE_T/OL/N_EN MHz_OUT R+ R- R- P ETHERNET PFOUT nf PFOUT nf R K oinel Technology Solutions LLP R R R R + uf T+ T- Size ocument Number Rev ustom V ate: Sheet of

V V V V nf R V K nf L FR L FR L FR L FR GL_ GL_ GL_ GL_ GL_ GL_ GL_ GL_ GL_S ONNET URT_TX URT_RX UF UF TO TI TMS TRST TK RST# RTK RSTOUTN P. P. VT nf nf URT_TX URT_RX PWM_. PWM_. PWM_. PWM_. P. P. P. ONNET P./L P. P. P. URT_TX_ URT_RX_ U VT V_Reg_ V_Reg_ VREF+ R/W RST RS S LE+ LE- VSS VREF- N V VSS TO/SWO TI TMS/SWIO TRST TK/SWLK nreset RTK RSTOUT P./PWM./TX P./PWM./RX P./PWM./TS/TRET P./PWM.//TRET P./PWM./SR/TRET P./PWM./TR/TRET P./PP./RI/TRELK P./R/RTS P./T/TX P./US_ONNET/RX P./nET/NMI P./nET/ISTX_LK P./nET/ISTX_WS P./nET/ISTX_S P./MT./PWM. P./STLK/MT./PWM. P./RX_MLK/MT./TX P./TX_MLK/MT./RX R V K V V V V nf LPXX VSS VSS VSS VSS VSS VSS nf nf nf P./R/TX/S P./T/RX/SL P./TX/. P./RX/. P./ISRX_LK/R/P. P./ISRX_WS/T/P. P./ISRX_S/SSEL/MT. P./ISTX_LK/SK/MT. P./ISTX_WS/MISO/MT. P./ISTX_S/MOSI/MT. P./TX/S/MT. P./RX/SL/MT. P./TX/SK/SK P./RX/SSEL/SSEL P./TS/MISO/MISO P.//MOSI/MOSI P./SR/S P./TR/SL P./RI/R P./RTS/T P././ISRX_LK/P. P././ISRX_WS/P. P././ISRX_S/TX P././OUT/RX P./S/US_S P./SL/US_SL P./US_P P./US_N P./ENET_TX P./ENET_TX P./ P./ENET_RS P./ENET_RX P./ENET_RX P./ P./ENET_REF_LK P./ENET_M P./ENET_MIO P./US_UP_LE/PWM./P. P./M/nUS_PPW/P. P./MF/PWM./SK P./MORT/PWM./SSEL P./M/US_PWR/MT. P./MF/PWM./MISO P./MF/PWM./MOSI P./M/MT. P./M/PWM./P. P./LKOUT/nUS_OVRR/P. P./M./MT. P./M/PP./MT. P./VUS/. P./SK/. RTK_I RTK_ XTL_I XTL_O P. P. N_R_ N_T_ URT_TX URT_RX P. L_RESET P. L_L P. L_S P. L_SK P. L_MISO P. L_MOSI P. TS_PEN P. S_R_ETET SPI_SK_ SPI_SK_ SPI_SSEL_ SPI_SSEL_ SPI_MISO_ SPI_MISO_ SPI_MOSI_ SPI_MOSI_ P. GL_RW P. GL_RS P. P.. P.. P.. P../OUT P. I_S_ P. I_SL_ P. US_P US_P US_N US_N ENET_TX ENET_TX ENET_TX ENET_TX ENET_RS ENET_RS ENET_RX ENET_RX ENET_RX ENET_RX ENET_REF_LK ENET_REF_LK ENET_M ENET_M ENET_MIO ENET_MIO US_UP_LE US_UP_LE US_PPWR US_PPWR P. TS_LK P. TS_S US_PWR US_PWR P. TS_MISO P. TS_MOSI P. P. US_OVRR US_OVRR P. TEST_LE./VUS VUS. POT RTK_I RTK_O XTL_I XTL_O. POT V R Variable Resistor RTK_I KHz RTK_O XTL_I MHz XTL_O VT Y pf pf Y pf MOS T nf T pf V P. P. P.. P.. P.. P../OUT P. I_S_ P. I_SL_ V GL_RW GL_RS GL_ GL_ GL_ GL_ GL_ GL_ GL_ GL_ P. P. P. P. P. P. V R K OX HEER ONNETOR ONLY J J ON ON GRPHIL L L EN L_RESET L_MISO L_MOSI L_SK L_S L_L TMHOW V P. P. P. P. N_R_ P. N_T_ P. P. P. P. RSTOUTN V R K R K J V GL_S J P OX HEER ON nf nf R R K V V R K LE_SUPPLY Q LE_SUPPLY TS_PEN P. TS_MISO P. TS_MOSI P. TS_S P. TS_LK P. V P./L nf SW ISP RST# LE nf SW RESET V R K R K R K R K R K R K R K R K J TRST TI TMS TK RTK TO RST# V TEST_LE R E LE V R E JTG LPXX M Size ocument Number Rev ate: Sheet of

V nf uf/.v SERIL PORT connections with TTL to RS onverter R V K SSEL MOSI SK MISO SPI_SSEL_ SPI_MOSI_ SPI_SK_ SPI_MISO_ S_R_ETET S V /T M LK T MIRO S J Vss SH SH SH SH JUMPER FOR SPI_ T T SSEL MOSI SK MISO R K K R V URT_TX URT_TX URT_RX URT_RX nf nf TX TX RX RX U + V - + - Tin Tin TT L Rout Rout V V+ RS V- Tout Tout Rin Rin MX nf nf nf TOUT TOUT R R R TOUT R TOUT R R R R FEMLE URT FEMLE J J URT oinel Technology Solutions LLP PERIPHERLS Size ocument Number Rev ate: Sheet of

PWR JK J SS US_V US_V J N V SLIE SWITH LE R E uf/v U N OUT N LM V uf/.v US_V US_V V V U OUT N V J LM uf/.v ON oinel Technology Solutions LLP POWER SUPPLY +V and +V Size ocument Number Rev ate: Sheet of

US_V J _H Vusb N _H P R K US_V R + R nf E E N_E P_E R K VUS VUS + R K V R K Q R K ONNET ONNET US TYPE LE J US_P US_N US_P US_N US_P US_N US_P US_N P_E N_E P_HST N_HST V R E LE US_UP_LE US_UP_LE R E ON V V US_PWR R K US_OVRR US_PPWR R K R K nf FLG_ EN FLG_ EN LM U OUT OUT R K R uf/.v nf N_HST P_HST pf R R pf R K R K J VUS - + S S US_PPWR US_PWR US_OVRR US_PPWR US_PWR US_OVRR L FR US_ oinel Technology Solutions LLP US HOST N EVIE Size ocument Number Rev ate: Sheet of