5. Properties and modeling of onchip Power Distribution Networks Decoupling capacitance
Electrical properties of on-chip PDN: capacitance Capacitance associated with PDN: Gates Interconnects Well (in standard CMOS) Effects Provide current to close switching gates Reduce the loop area where the switching current flows As a consequence: reduce the peak current in the power/ground pins and reduce PSN However the intrinsic capacitance is not enough to reduce PSN to the required level Intentionally added Decoupling capacitors (Decaps)
Intra-block decaps Intra-block decaps have constrained dimensions For example, they are implemented in the standard-cell template They are usually implemented as MOS capacitors Digital logic block
MOS decaps V DD N-well V DD P diffusion row height GND tie-off cell (Veendrick00) N diffusion GND
MOS decaps N-well V DD P diffusion W P L P V DD row height GND N diffusion W N L N GND
Decap Model r G = poly gate resistance r = channel resistance NMOS decap: c = gate to channel capacitance c B = channel to substrate capacitance l r B = substrate resistance GND r G V DD GND i(v) = direct tunneling gate current ALL PARAMETERS ARE PER UNIT LENGTH i(v) (B) p+ n+ n+ p+ c B r c r B substrate Model characteristics: Distributed RGC model to take into account HF effects Gate leakage modeled by a voltage-dependent current source
Decap Model (cnt d) NMOS decap: l GND V DD GND i(v) (B) p+ n+ n+ p+ r c r B substrate Model simplification: Exploit symmetry of the decap Poly gate resistance (r G ) << channel resistance (r) Channel-to-substrate capacitance (C B ) neglected
Model of a PMOS decap GND V DD V DD n+ p+ r i(v) p+ n+ r B c N well c W to substrate contact (GND) r S to substrate contact (GND) PMOSt decap has the same model as the NMOSt decap N-well decap in parallel; two decap structures with different parameters, coupled through the boundary
Electrical model of MOS decaps Gate current (log. scale) V DD t OX v(x,t) r, c i(v) Gate current (linear scale) i(v) is linearized around V DD i( v) I + gv 0 Voltage (linear scale) -L 2 v 2 x GND 0 L v = rc + ( I0 + gv) r t x V DD Voltage (linear scale) Channel term Gate leakage term
Example: response of a MOS decap to DC bias + AC excitation V M e jωt in steady state can be separated in DC solution + AC solution r, c v(x,t) + V DD ( ) i(v) I cosh x gr vdc ( x) VDD g cosh ( l gr ) 0 I0 = + g -L 0 +L x 2 v v PDE: = rc + 2 ( I0 + gv) r x t j t BC: v( L, t) = v( + L, t) = VDD + VM e ω ( x gr + jωrc ) ( l gr + jωrc ) cosh jωt vac ( x, t) = Re VM e cosh
Example DC response: Impact of technology scaling Drop voltage along the channel increases as t OX is reduced Drop voltage along the channel increases with channel length 90nm L = 10µm, W = 3µm, L = 5µm W = 3µm, 65nm technology L = 10µm 65nm 45nm L = 20µm 0 Normalized voltage along the channel +L Normalized distance along a half of channel length length 0 +L
DC response: Impact of technology scaling Loss of charge due to gate leakage WIDTH = 3µm, L = { 5µm 10µm 15µm 20µm
Example AC response. No leakage case 1.1 Normalized voltage along the channel Movie r, c V M e jωt 1 v(x,t) 0.9 -l δ 0 δ +L x 0.8 0 L v (, ) ( )cos( ) AC x t = A x ωt + φ Amplitude A(x) changes along the channel It depends on r and c as well as ω at low ω A( x) V M behaves as a lumped element decap
Example AC response. No leakage case 1.1 Normalized voltage along the channel Movie r, c V M e jωt 1 δ 0.9 v(x,t) -l δ 0 δ +L x 0.8 0 L v (, ) ( )cos( ) AC x t = A x ωt + φ Amplitude A(x) changes along the channel It depends on r and c as well as ω at higher δ = 2 ωrc ωrc 2 ω A( x) V e, where δ = L x M δ if the amplitude decreases times e 1 skin depth If δ L (at ω ω C ), decap AC performance decreases.
Example AC response. No leakage case 1.1 Normalized voltage along the channel Movie r, c V M e jωt 1 δ 0.9 v(x,t) -l δ 0 δ +L x 0.8 0 L v (, ) ( )cos( ) AC x t = A x ωt + φ Amplitude A(x) changes along the channel It depends on r and c as well as ω If δ << L (at ω >> ω C ), decap AC performance is very low.
Example AC response. Leakage case 1.1 Normalized voltage along the channel Movie r, c V M e jωt 1 g 0.9 v(x,t) -l δ 0 δ +L x 0.8 0 L v (, ) ( )cos( ) AC x t = A x ωt + φ At low ω is only dimmed by g and r Amplitude A(x) changes along the channel It depends on r, c and g as well as ω
Example AC response. Leakage case 1.1 Normalized voltage along the channel Movie r, c V M e jωt 1 g v(x,t) 0.9 δ L -l δ 0 δ L +L x 0.8 0 L v (, ) ( )cos( ) AC x t = A x ωt + φ Amplitude A(x) changes along the channel It depends on r, c and g as well as ω Now δ L can be approximated by δ δ L < δ 2 g 1 g 1+ ωc 2 ωc
AC response: Impact of technology scaling Solid blue line: no leakage Dashed red line: leakage Decap channel half length L = 20µm
Frequency response
Skin depth (NMOSt W = 3 µm, L = 2.8 µm) 5 GHz 10 GHz 20 GHz Dots: HSPICE Lines: equations 200 GHz 50 GHz x 0.14 um 0.35 µm technology
Input Impedance of a MOS Decap 2l r, c g Z = Z l IN coth 0 ( γ ) Z IN Z 0 = g r + jωc γ = r g + ( jωc) Critical frequency at l = δ The frequency that separates lumped and distributed behaviour Lower critical frequency in case of gate oxide leakage NO LEAKAGE: if l = δ f = C 1 π rcl 2 LEAKAGE: if l = δ f = L L C 1 grl π rcl 2 2
Normalized R and C as a function of frequency Normalized Capacitance 10E+3 1E+3 100E+0 10E+0 1E+0 100E-3 45nm 65nm 90nm 90nm - no leakage Analytical model PSTAR simulations 10E-3 100E+3 1E+6 10E+6 100E+6 1E+9 10E+9 100E+9 Frequency [Hz] Normalized Resistance 10E+3 1E+3 100E+0 10E+0 1E+0 100E-3 10E-3 1E-3 90nm 90nm - no leakage 45nm 65nm 100E+3 1E+6 10E+6 100E+6 1E+9 10E+9 100E+9 Frequency [Hz] Analytical model PSTAR simulations R C EQU EQU = Re { Z } IN 1 = ω Im normalized R = normalized C = { Z } IN R EQU lr C EQU lc
Conclusions At high frequency, decaps must be modeled as a distributed structure Model based on physical grounds Relevant parameters for each technology node are easily obtained Methodology to analyze the decap response Example: analysis of the DC and AC response Critical frequency/dimension expressions define the border between full and reduced decap performance w/wout gate leakage Gate leakage decreases the decap performance at low as well as at high frequencies
Allocation of intra-block decaps Simple strategy (Smith94) Decap at block i should be able to provide the charge as the power voltage level varies as δvdd avg δ Q = I / f i i CLK during one clock cycle C δq avg decap i i i = = δvdd fclkδvdd Assumptions: a) during the switching event, the decap is effectively disconnected from the power supply. It provides all the required charge. b) The decap is fully recharged before the beginning of the next clock cycle. I More elaborate strategy (Zhao02) 1. The circuit without any decap is analyzed and the worst case power noise is determined. 2. Blocks with power noise V noise below the target margin δv do not receive additional decaps. 3. In blocks where V noise > δv, an additional decoupling capacitance is added C decap V δv δq noise = Vnoise δv The additional charge provided by the decap is porportional to the difference V noise - δv
Allocation of intra-block decaps A further refined strategy (Su03) 1. For each circuit node determine the value of the following metric: T 0 ( j δ ) M j = max V ( t) V, 0 dt 2. Calculate the overall power supply quality as: M = j M j 3. Add decaps at the places where M j > 0. M become zero when the power supply margin is satisfied at all times and nodes V j (t) M j V DD δv t1 t2 T t
An on-chip voltage regulator (Ang00) VDD VDD enabled GND GND VDD 0 t disabled
Gated decaps, active decaps (Roy05, Gu06) Gated decaps Active decaps
Application of the model: inter-block decaps (Rius06) Intra-block decaps have constrained dimensions Inter-block decaps do not suffer from this constraint Typically, used for EMI reduction purposes Digital logic block System-on-Chip
Example Inter-Block Decap: Gate length must be limited (A) (B) L F L F L F L F L F L F L F VDD Y VDD W S GND GND VDD Y VDD Z Z Z Z Z Z Z Z Z
Example Inter-Block Decap: Fingers and Stripes Finger VDD Stripe GND VDD Stripe GND VDD
Inter-Block Decap Model Parameters Model parameters are defined to be independent of length and width r C g I OX OX OX WL Channel sheet resistance [Ω/ ] Gate capacitance per unit area [F/m 2 ] Gate oxide conductance per unit area [S/m 2 ] Gate current density per unit area [A/m 2 ] Total gate area [m 2 ] Critical frequency f L C = 1 gox π r C l OX r l 2 2 Total gate-oxide leakage ( ) I = WL g V + I LEAK OX DD OX
Procedure for Optimum Inter-Block Decap Design 1. Define the total decoupling capacitance C DEC to be included in the IC 2. Determine the effective total area as A C C C = DEC OX 3. Obtain the gate length of a finger L F0 to get the maximum frequency f C for which the decap needs to perform f L C = 1 g π r C r L 2 OX F 0 2 OX LF 0 4. Define the number of gate fingers as 5. Obtain the gate length of a single decap as 6. Define the number of stripes as where W MAX is the maximum allowed gate width 7. Obtain the gate width of a single decap as 8. Calculate total leakage n A L = / C F 0 L = A / n F C m = A / C WMAX W = A / m S C ( ) I = A g V + I LEAK C OX DD OX
Example 90nm GP technology Required decap C DEC = 1nF Three gate-oxide thicknesses Area total [um2] 3.5E+05 3.0E+05 2.5E+05 2.0E+05 1.5E+05 1.0E+05 90nm GP Total decap area vs. f C red : tox = 6.5 nm magenta: tox = 5 nm black: tox = 1.6 nm 100 90nm GP Gate length of a finger vs. f C red : tox = 6.5 nm magenta: tox = 5 nm black: tox = 1.6 nm 5.0E+04 0.0E+00 1.00E+07 1.00E+08 1.00E+09 1.00E+10 fc [Hz] LF [um] 10 1 1.00E+07 1.00E+08 1.00E+09 1.00E+10 fc [Hz] Results: Area factor = 1.01 to 1.23 Total leakage current I LEAK = 1.1 ma