Grabber 0 MHZ Analog Signal Digitizer Technical Manual 0 th Street, Davis, CA, USA Tel: 0--00 Fax: 0--0 Email: sales@tern.com http://www.tern.com
COPYRIGHT Grabber, and A-Engine are trademarks of TERN, Inc. AmES and AmES are trademarks of Advanced Micro Devices, Inc. Version.00 November, 00 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of TERN, Inc. 000-00 0 th Street, Davis, CA, USA Tel: 0--00 Fax: 0--0 Email: sales@tern.com http://www.tern.com Important Notice TERN is developing complex, high technology integration systems. These systems are integrated with software and hardware that are not 00% defect free. TERN products are not designed, intended, authorized, or warranted to be suitable for use in life-support applications, devices, or systems, or in other critical applications. TERN and the Buyer agree that TERN will not be liable for incidental or consequential damages arising from the use of TERN products. It is the Buyer's responsibility to protect life and property against incidental failure. TERN reserves the right to make changes and improvements to its products without providing notice. Temperature readings for controllers are based on the results of limited sample tests; they are provided for design reference use only.
Grabber Introduction Functional Description The Grabber (GR) is a high speed, analog signal digitizer board. Features:. x. x 0. inches 0 MHz, -bit ADC, with front signal conditioning DC only, driven by AE/AE/BBA/SL///IE/IEM/IEP/ID KB 0 ns FIFO for 0MHz ADC data Two channels of 0 MHz ADC with two KB SRAMs for data storage Clock selectable from on-board oscillator, external, or host controller clock. Trigger window based on one shot, from an external pulse or host controller I/O. Analog input signal conditioning with front amplifier. The GR supports two channels of high speed analog signal digitizers. Each channel consists an -bit 0/0 MHz ADC (, Analog Devices), an 0 MHz Rail-to-Rail front amplifier (A, Analog Devices), and a KB SRAM FIFO. An optional high speed KB FIFO (IDT, or CYC) can be installed to store ADC data up to 0 MHz. Two ADC channels are driven by the same clock and same address generator, so two analog signals can be digitized and recorded simultaneously. The ADC clock can be selected, via H header, from an on-board clock oscillator, or host controller s clock, or an external clock. The ADC can operate continuously at full clock speed, but the ADC data can only be stored in the FIFO within a trigger window, while /WRFF low active. A trigger signal can be generated by a host controller s I/O pin (P for example), or by an external trigger pulse with a HC one shot. The conversion and the recording can not be stopped until the pre-select address size reached. A address generator can be reset by software, or reset by reaching a pre-set address. There are length of ADC data can be selected via H jumper: KB, KB, or KB. When the address reaches the selected length, the ADC conversion stopped, and the address generator reset to zero, ready for the host controller to read out ADC data. The ADC data can only be read in the sequence of First In First Out. Only one channel ADC data can be read out continuously at a time. Each read operation by the host controller will increment the address. The host controller can also directly read each ADC without store any data in the FIFO RAM. It will be useful during a calibration. The GR is designed as an expansion board, measuring. by. inches, for TERN controllers such as A-Engine/i-Engine/BB-A. The GR interface to the host controller via 0x pins at J, and 0x pins at J.
Grabber Introduction By default, the valid analog signal input voltage level at J, and J header should be V peak to peak, and centered at.. So the valid analog input signal should be in the voltage range of V to V. I/O Map All devices on the GR are I/O mapping for host controller access. You can access such I/O devices, using J pin /PCS0, with inportb(port) or outportb(port,dat). These functions will transfer one byte or word of data to the specified I/O address. The table below shows more information about I/O mapping. I/O space Select Usage Location 0x000 /PCS0 Reads address status, SA H pin 0x000 /PCS0 Reads Write window status, /WRFF H pin =/WRFF 0x00b0 /PCS0 Write to. Low=ADC active U pin 0x00a0 /PCS0 Write to /RESET. High=reset address U pin 0x00c0 /PCS0 Read U ADC, if =0 0x00c0 /PCS0 Read U RAM, if = 0x00d0 /PCS0 Read U0 ADC, if =0 0x00d0 /PCS0 Read U0 RAM, if = Usage of Controller I/O Pins P=J pin. Start digitizing if P high via Jumper H pin 0 (P)=pin (/WRFF). /CTS=J pin, /PCS0=J pin, /RTS=J pin are used for optional base peripheral chip select via H header to pin =/PCS. /INT=J pin, may use as input or interrupt for U FIFO pin, and H pin. J pin = =H pin. For A-Engine, J pin =P (Timer output). For A-Engine, J pin = 0 MHz system. It is too fast to use. User may use J pin =P as digitize clock, or use external clock, or install a oscillator in K. Optional connectors can be installed on J, J, J, and J, replacing pin headers. Please read the grabber schematic included in the CD for more details. A sample program grabber.c is available.
J U FIFO J U A U0 A U ADS00 U U0 U RAM U0 U U U U0 J RAM J Grabber Layout, Mar., 000
J N R 0 R 0K R 0K P I+ I- R 0K HDRS R 0K C 0.UF P R 0K I- I+ U NC DE I- V+ I+ VO V- NC A AS C 0.UF J N R0 I- R0 U0 0K 0K NC DE R0 I- I- V+ 0 I+ I+ VO V- NC C00.UF A I+ AS R0 P P R0 0K R0 0K C0 0K 0.UF HDRS C DIPCAP C R DIPCAP C 00 J EX K NC + 0MHZ OS C J /TRI OS C 0.UF C DIPCAP C 0.UF U Q SA Q SA Q Q Q0 SA SA Q Q SA Q Q SA SA Q RST Q 0 /RESET SA Q SA 00 00 U SA Q SA Q Q Q Q0 S SA Q Q SA SA Q Q SA SA SA Q RST SA /RESET SA Q 0 /RAM Q S 00 00 R 0 + U PD RO RI BIO 0 U0 PD RO RI R0 BIO + 0 0 BD BD BD BD A AD AD AD AD AD AD AD AD A AD AD BD B BD BD U B B B B B B B 0 B B B0 B B D LED 0 D D D VC D D D D 0 D D D VC D D D D IN- IN+ + CM - 0 ADS00 ADS00 MSB /OE A AD AD AD AD AD AD AD B BD BD BD BD BD BD BD + H AD AD AD AD HDRD HDRD H HDRD HDRD BD BD BD BD R0 LED 0 SA SA SA SA SA SA SA SA SA SA SA S A AD AD U RAM0 MEMS A A A A A A A A 0 A A A D D VDD A CE 0 R/W A A A A /OE /CE D D 0 D D D U0 RAM0 MEMS SA A SA A SA A SA SA A SA A A SA A SA SA A SA 0 A A SA A S B BD BD D D C0 0.UF RN /RD /WR A A A A /PCS 0K RNS VDD A CE 0 R/W A A A A /OE /CE D D 0 D D D SA SA SA SA SA SA /RDFF S /RAM AD AD AD AD AD U A AD A A AD A AD AD A AD A AD A A AD A /RDFF G G HC HC U0 B A SA BD A SA BD A BD SA BD A SA BD A A SA BD A SA BD /RDFF A S /RDFF G /RAM G BD BD BD BD BD HC HC Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y D D D D D D D D D D D D D D H /CTS /PCS0 /PCS /RTS /WRFF EX 0 OS C 0.UF U CK 0 I O I O /RDFF I O SA I O I O /RDFF I O I O /WRFF 0 I O0 /RESET G /OE /RAM PALV HDRD HDRD H SA SA SA SA /INT /TRI 0 P /TR /WRFF =0, RD ADC =, RD RAM GRABP000.PDS /FF 0XB0 RD STATUS OF FF /EF 0X RD STATUS OF EF 0XB0 WR TO RESET 0X WR RESET LOW PULSE /RDFF 0XC0 RD FIFO /TRI /RDFF /RDFF /WRFF /RESET /RAM HDRD HDRD 0 P 0 /CTS 0 0 R HDR P P /INT /RTS J STE/TERN Title High Speed Analog Signal Digitizer Size Document Number B grab.sch J 0 /RST /PCS0 0 /WR 0 /RD 0 AD AD AD AD 0 HDR AD A D D D D D D D A A A A A A A AD D D D D D D D D RS /RESET AD WEN PAF W /WRFF PAE WEN/LD 0 REN Q /RDFF R Q REN Q D /RDFF OE E F Q Q Q Q D Q Q F F 0 FIFO IDT 0 /INT D P D D D D R 0K HDRS UA C CEXT 0.UF CEXT HC REV Date: November, Sheet of U 0K REXT REXT/CEXT /TRI A Q LED /RESET B CLR Q /TR