A Systematic Approach to Frequency Compensation o the Voltage Loop in oost PFC Pre- regulators. Claudio Adragna, STMicroelectronics, Italy Abstract Venable s -actor method is a systematic procedure that allows designers to compensate the error ampliier in eedback loops o control systems to achieve the desired bandwidth and phase margin. This approach is o general use and can be applied to PFC pre-regulators as well. In this paper, a slightly dierent algorithm to Venable s original version is proposed, tailored to the particular characteristics o PFC pre-regulators. 1. Introduction Venable s -actor method [1] deines an algorithm allowing power supply designers to determine the requency compensation components needed to achieve the desired control goal. Starting rom the control-to-output transer unction o the converter, an appropriate structure or the output-to-control transer unction is selected and then gain and pole/zero locations are chosen so that the gain o the resulting open-loop transer unction crosses over the d axis at a given requency, while its phase lag at that requency is such that the speciied phase margin is obtained. In other words, in Venable s method, the control goal is expressed in terms o dynamic accuracy, response speed and degree o stability. The reader will certainly recall that the open-loop crossover requency is related to the closed-loop settling time o the step-change response, while phase margin aects both the settling time and the damping ratio o the response. When one applies -actor method to PFC preregulators, using phase margin as part o the control goal makes deinitely sense. System stability and the tendency to be more or less prone to ringing are o primary importance. However, the characteristics o the PFC preregulator render crossover requency goal o little use. It does not provide much insight concerning the trade-o between good pre-regulator perormance (low total harmonic distortion o the input current and high power actor and acceptable dynamic behavior. A more appropriate approach is suggested in [], where the level o harmonic distortion introduced by the compensated error ampliier in the input current is taken into consideration. In the ollowing sections the control goal will be ormulated in a more convenient way ollowing the approach given in [], and Venable s -actor method will be adapted accordingly. The modiied algorithm will be entirely developed and lead to the ollowing result: PFC stages with input eed-orward can be compensated so that they exhibit a preset phase margin and a preset distortion level or any operating condition; those without input eed orward can be compensated so that their phase margin is kept above a minimum value or any operating condition, with a distortion not exceeding a maximum preset level.. Input current distortion and voltage loop compensation There are two maor sources o distortion in the input current o a PFC pre-regulator. The irst is the so-called crossover distortion, which appears as a small plateau next to the zero-crossings o the line voltage. Essentially, it stems rom the power stage s inability to transer energy eectively in that zone and is unrelated to voltage loop compensation. The second contributor is the distortion o the current reerence generated by the control IC, which equally impacts the input current rom the mains. Unlike the irst, this second contributor is heavily dependent on the way the voltage loop is compensated. The current reerence is obtained by multiplying the properly scaled-down rectiied line voltage with the error signal (Vc o the voltage control loop (the output o the error ampliier, E/A, o the control IC. With a perectly sinusoidal line voltage, an undistorted current reerence can be obtained i, and only i, the error signal is a dc voltage. Any ac component would introduce higher order harmonic components. Actually, the output voltage o a PFC stage has a nearly sinusoidal ripple at the second harmonic
o the line requency ( L superimposed on the dc regulated value Vo; its peak amplitude V O is essentially related to the reactance o the output capacitor at L : Po Vo, (1 4 π L Vo Co where Po is the output power and Co the output capacitance. The error ampliier has a non-zero gain (H at that requency, and thereore, a voltage ripple with peak amplitude equal to Vc H Vo ( will appear at the E/A output, superimposed on the dc value Vc. Vc depends on the operating conditions (input voltage and output current, as well as the control technique and the characteristics o the control IC. It is possible to show that the ripple Vc contributes an additional component at the undamental requency and a third-harmonic component in the current reerence, both with peak amplitude equal to Vc /., The third-harmonic distortion o the current reerence and input current is given, with good approximation, by: 1 Vc D3, (3 Vc Vc where Vc is the zero-power level o the control voltage. Table 1 shows the eective control voltage Vc-Vc or some commercially available PFC controllers. Part # L6561 L656 L6563 L4981 NOTES: Control method Transition Mode Transition Mode Fixed Freq. Avg. CM Feedwd Vc - Vc Pi No Rs M P V i Yes Yes 4 P M Rs Pi FF Rs Pi M P Ri M : multiplier gain (reer to IC datasheet P : multiplier input divider ratio (L656x; reciprocal o multiplier input bias resistor (L4981 FF : eed-orward circuit gain (L4981 Rs: current sense resistor Ri: current gain programming resistor (L4981 Pi: input power to the PFC stage (Po/η, η eiciency Vi: line voltage (rms value Table 1. Eective control voltage in dierent control ICs. Once the power stage has been deined, the control voltage Vc under assigned operating conditions can be taken rom Table 1 and the peak output voltage ripple derived rom (1. Given the maximum speciied level o thirdharmonic distortion D 3, with (3 it is possible to ind the maximum output ripple Vc o the E/A and, rom (, the E/A gain at L, H : Vc Vc Vc H D3. (4 Vo Vo 3. PFC small-signal model Once a constraint on the E/A gain has been determined, voltage loop stability and dynamic perormance need to be addressed. To do so, as in any closed-loop control problem, the starting point is the transer unction o what in control theory terminology is called the plant, in the present case the small-signal control-to-output transer unction o the PFC pre-regulator. The discussion will be ocused on pre-regulators powering a downstream dc-dc converter. It is well known [3] that a regulated dc-dc converter represents a constant power load to the PFC pre-regulator and that, as shown in Fig. 1, the small-signal model o such a system is given by a controlled current generator which drives the output capacitor Co. ^ Io Co ^ Vo Fig. 1 Small-signal model o a PFC stage with a constant-power load (dc-dc converter. The generator î o is controlled by the small-signal ac control voltage v c. This system behaves as a pure integrator and the resulting control-to-output transer unction is: vˆ o G G(, (5 vˆ c where the unity gain actor G is given by Po G, (6 Vo ( Vc Vc C regardless o the control method and the characteristics o the control IC [3]. The transer unction then presents ust one pole at the origin. As illustrated in Fig., the gain alls at -1 slope (- d/decade and the phase shit is -9º (i.e. +9º phase lag at all requencies.
Observing the values o Vc-Vc in Table 1 and equation (6, G is essentially independent o the load. Additionally, with input voltage eed-orward it does not depend on the line voltage either. Without input voltage eed-orward, rather, G is proportional to Vi. G ( d 1 5 5 w/o FFWD min. to max. line 1.1 1 1 1 1.1 3 w FFWD underdamped the system will be (aster rise and settling times but with larger overshoots and ringing. A well-known rule o thumb in servo systems suggests 45º as the optimum phase margin. This ensures ast transient response with an acceptable level o ringing. In SMPS it is not uncommon to speciy higher phase margins (even 75º or more to account or very large spreads in line, load and temperature changes as well as manuacturing tolerances, or to ulill special requirements. For example, to achieve a lat closed-loop requency response and minimize peaking o the output impedance, which could result in poor reection o periodic disturbances, it is necessary to have Φ m 66º. To achieve a critically damped step response it should be Φ m > 76º. G( G ( 89 H ( deg 9 d 4 6 Z P 91.1 1 1 1 1.1 3 Fig.. ode plots o the control-to-output transer unction G( (eq. 5. In a typical wide-range mains application there is a 3:1 ratio between the maximum and the minimum line voltage. This means that without input voltage eed-orward G is 9 times ( 19 d higher at maximum line than at minimum line. 4. Phase margin and -actor As previously stated, the priorities in designing a control loop are its closed-loop stability and its dynamic behavior. Phase margin plays a key role in both o these aspects. The characteristics o a closed-loop system can be inerred rom its open-loop properties. Stability, in particular, is related to the so-called phase margin (Φ m, deined as the dierence between 18º and the actual phase lag at the requency where the open-loop gain is unity. Phase margin, however, is also related to the dynamic behavior o the closed-loop controlled system. Qualitatively, it is possible to state that the higher the phase margin, the more overdamped the system will be (longer rise and settling times and smaller overshoots; conversely, the lower the phase margin, the more H( H ( deg 8.1 1 1 1 1.1 3 5-9 1.1 1 1 1 1.1 3 Φ Fig. 3. ode plots o a Type ampliier s transer unction H( (eq. 7. As with many power conversion systems, in PFC pre-regulators, additional E/A gain requirements arise rom the need to ensure both good line and load regulation (which requires maximizing the low requency gain and switching requency noise reection (which requires minimizing the high requency gain. In PFC pre-regulators, as shown in Section, a limit on the gain at the second harmonic o the line requency ensures that the input current does not exceed a speciied distortion level. All o these requirements can be ulilled by what in Venable s approach is called a Type ampliier.
Its transer unction H( includes one pole at the origin and a zero-pole pair: π Z H(. (7 π P Its ode plots and circuit implementation are shown in Fig. 3 and Fig. 4 respectively. Vo R1 R V REF C FP R FS - + C FS Vc Fig. 4. Schematic diagram o a Type ampliier. The relations between the component values in Fig. 4 and the parameters o (7 are listed below: Z 1 1 CFP P R1 P z CFS CFP. (8 Z 1 1 RFS π Z CFS The zero-pole pair creates a region o requencies where the gain lattens and the phase lag is reduced. The maximum phase lag reduction Φ, called phase boost, depends on the zero-pole requency spread P / Z and occurs at the requency: The quantity:. (9 Z P Z (1 is the so-called -actor and is related to the phase boost Φ : 1 1 1 Φ tan ( tan, (11 which, solved or, provides the ollowing relationship: sin Φ. (1 cos Φ Note that the phase shit is symmetrical to, which means that or any positive real number λ the ollowing equality holds true: H( π / λ H( λ π. (13 P 5. Calculation method In Venable s original approach, coincides with the crossover requency o F( G( H( c. Zero and pole are placed symmetrically around it at / and at respectively, with derived rom (1 to achieve the phase boost Φ necessary or the speciied phase margin. Unlike the original ormulation, in this context the condition c is replaced by the equivalent constraint (4 on the E/A gain at L. The second harmonic o the line requency L is typically 3-4 times P and much larger than Z. Thereby, starting rom (7 and taking (1 into account, with good approximation we have: H H( π L, (14 4 π L which will be solved or the unity gain actor H : H 4 π L. (15. In this equality, H is calculated rom (4 but still needs to be ound. To calculate, it is necessary to treat the cases o PFC pre-regulators with and without input eed-orward separately. For the derivations that ollow it is useul to rewrite (7 in terms o and : π H(. (16 π 5.1. Systems with eed-orward In systems with eed-orward the unity gain actor o the control-to-output transer unction G is a constant. Since the pre-regulator s operating conditions do not aect the voltage loop, a speciic design setpoint is not needed and can be selected to be the open-loop crossover requency as in Venable s original approach. In order or to be the crossover requency o the open-loop gain F( G( H(, the ollowing condition must be met: G H( π 1, (17 π which, combined with (16, becomes: G 1. (18 ( π This equation can be solved or ( c: 1 G H ; (19 π subsequently, Z and are determined by dividing and multiplying by, respectively:
1 G Z P G. ( π π Finally, to ind, note that as the transer unction (5 eatures a ixed 9º phase lag, the phase boost Φ equals the phase margin Φ m. In act, being the crossover requency, by deinition: o o o [( 9 Φ + ] Φm 18 9 Φ ; (1 will then be calculated rom (1 with Φ Φ m. To summarize, the design algorithm can be outlined in seven steps starting rom the ollowing data: L, Vo, Po, η, M, Vc, P, Rs, Co. 1 Calculate the output voltage ripple rom (1 and the eective control voltage with the aid o Table 1; use ull load conditions. Calculate the E/A gain H rom the speciied third-harmonic distortion level D 3 using (4. 3 Calculate G rom (6. 4 Substitute the speciied phase margin Φ m in Φ in (1 and calculate. 5 Calculate H rom (15. 6 Calculate Z and P rom (. 7 Determine the component values o Fig. 4 rom (8. R1 can be either selected arbitrarily or determined based on other requirements. 5. Systems without eed-orward In systems without eed-orward the unity gain actor o the control-to-output transer unction G is proportional to Vi. The pre-regulator s operating conditions will aect the voltage loop s characteristics considerably and the algorithm given in the previous section would achieve the speciied third-harmonic distortion level and phase margin at a speciic line voltage only. Here a dierent approach is proposed that allows the design o the voltage loop such that the thirdharmonic distortion level will always be lower than a speciied value and the phase margin always higher than a speciied value. I (Vi min, Vi max is the line voltage range, it is convenient to consider the quantity Λ as: Vimax Λ. ( Vimin As stated in section 3, the unity gain actor G o (5 will change with Vi. I G G x at Vi Vi max, it will be G G x /Λ at Vi Vi min. This will aect the open-loop crossover requency: its value will be in a range (c min, c max that will clearly depend on Λ and on how H( is designed. We deine: cmax α. (3 c min The algorithm is based on the key idea o placing the requency at the geometric mean o what the resulting (c min, c max range will be. Consequently, the phase shit and the resulting phase margin will have the same minimum value at c min and c max by virtue o (13. Additionally, rom (3: cmin ; cmax α. (4 α This concept is illustrated in Fig. 5. Starting rom (16 and (4, it is possible to write the expression H(πc max as ollows: α H(π c max. (5 πα α In order or c max to be the crossover requency at Vi Vi max, the ollowing condition must be met: Gx H( πc max 1. (6 π c max Considering (5 and (4, equation (6 solved or c max, provides: c max 1 F ( d F( F ( deg 1 1 α Gx. (7 π α +.1 1 1 1 1. 1 3 /α c min 1 14 16 @ Min. Line 18.1 1 1 1 1. 1 3 @ Max. Line α c max Φ m Fig. 5. placed symmetrically to (c min, c max ensures the same Φ m at ViVi min, ViVi max. Using a similar method it is possible to ind c min : 1 1 c min α + Gx π Λ. (8 α Finally, dividing (7 by (8 and by virtue o (3: 1 + α α Λ. (9 α +
Similar to the previous case, will be derived rom the condition on the phase shit necessary to achieve the speciied phase margin Φ m. In this case, however, the concept expressed in (1 has to be slightly modiied: Φ m will be equal to the phase lag reduction at c max (which equals that at c min, by assumption. Then, rom (5: 1 1 α Φm tan ( α tan. (3 This equation, solved or, yields: ( Φ ( α + [ tan( Φm ( α ] tan m + 4α. (31 α Equations (9 and (31 must be solved simultaneously to ind the value o that provides the same phase margin Φ m at both c max and c min, with c max /c min α. The analytic solution is diicult to ind and it is preerable to use either calculation sotware or a numerical method. The solution is presented in Table, which shows the values o α and corresponding to some typical values that can be speciied or Φ m and Λ (Λ 1.5 is or single mains, Λ 3 or widerange mains applications. Φ m [º] Λ 1.5 Λ 3 α Φ [º] α Φ [º] 3 1.311 1.764 3.9.115 1.995 36.8 35 1.33 1.966 36.1.6.97 43. 4 1.35.7 41.3.3.671 48.9 45 1.37.5 46.4.43 3.138 54.6 5 1.391.864 51.5.55 3.79 6. 55 1.41 3.38 56.6.65 4.491 64.9 6 1.43 3.943 61.5.699 5.499 69.4 Table. Numerical solution o system (9 & (31. Table shows also the phase boost Φ, which is the maximum phase margin that will be achieved when the input voltage is such that c. Frequency can be easily obtained by either dividing (7 by α or multiplying (8 by α. A simpler expression or can be obtained by multiplying (7 by (8 and recalling that it is the geometric mean o c min and c max ; the result is: 1 Gx. (3 π Λ The locations o Z and can be ound by dividing and multiplying by, respectively: 1 Gx Gx Z P. (33 π Λ π Λ In the above equations, H will be computed rom (15. Since the value G x o G at maximum line voltage Vi max has been used, H will be determined evaluating (4 at maximum line voltage. The design algorithm can be outlined again in seven steps, i the ollowing data are available: L, Vi min, Vi max, Vo, Po, η, M, Vc, P, Rs, Co. 1 Calculate the output voltage ripple rom (1 and the eective control voltage with the aid o Table 1 at Vi Vi max and ull load. Calculate the E/A gain H rom the speciied third-harmonic distortion level D 3 using (4. 3 Calculate G G x rom (6. 4 Calculate the ratio Λ Vi max /Vi min, substitute the speciied Φ m in (31 and solve the system (9, (31; use Table i possible. 5 Calculate H rom (15. 6 Calculate Z and P rom (33. 7 Determine the component values o Fig. 4 rom (8. R1 can be either selected arbitrarily or determined based on other requirements. 6. Conclusions The control goal o PFC pre-regulators has been ormulated in terms o maximum third-harmonic distortion level and phase margin. A modiied version o Venable s original -actor method, where crossover requency is not previously speciied, has been used to deine the error requency compensation o the ampliier. The algorithm has been derived considering two separate cases: PFC stages with and without input voltage eed-orward. In the ormer case, compensation is done such that the system exhibits a speciied phase margin and a speciied distortion level or any operating condition. In the latter case it is done so that the system exhibits a phase margin equal to or larger than a speciied value, with a distortion level equal to or less than a speciied level or any operating condition. In both cases a step-by-step algorithm has been provided. 7. Reerences [1] D.H. Venable, Optimum Feedback Ampliier Design or Control Systems, Technical Paper #3, www.venable.biz [] L. Dixon, Optimizing the Design o a High Power Factor Switching Preregulator, SLUP93, SEM7 [3] R. W. Erickson, D. Maksimović, Fundamentals o Power Electronics, nd Edition, 1, ISN -793-77-