EE 330 Lecture 17 MOSFET Modeling CMOS Process Flow
Review from Last Lecture Limitations of Existing Models V DD V OUT V OUT V DD?? V IN V OUT V IN V IN V DD Switch-Level Models V DD Simple square-law Model Logic Gate V DD V BIAS V OUT Switch-Level Models Simple square-law Model } Voltage Gain Input/Output Relationship? V IN Voltage Amplifier
Review from Last Lecture Model Extensions 300 I D 250 200 150 100 50 V A 1 0 0 1 2 3 4 5 V DS Projections intersect V DS axis at same point, termed Early Voltage Typical values from -20V to -200V Usually use parameter λ instead of V A in MOS model
Review from Last Lecture Model Extensions 300 250 200 Id 150 100 50 0 0 1 2 3 4 0 VGS VT W VDS ID μcox VGS VT VDS VGS VT VDS VGS VT L 2 W 2 μcox VGS VT 1 VDS VGS VT VDS VGS VT 2L Note: This introduces small discontinuity (not shown) in model at SAT/Triode transition Vds
Review from Last Lecture
Review from Last Lecture Typical Bulk Effects on Threshold Voltage for n-channel Devices V TH=V TH0+γ -VBS - 1/2 0.4V 0.6 V V TH V TH0-6 -5-4 -3-2 -1 0 1-5V V BS Bulk-Diffusion Generally Reverse Biased (V BS <0 or at least V BS <0.3V ) for n-channel Shift in threshold voltage with bulk voltage can be substantial Often V BS =0
Review from Last Lecture Model Extension Summary I I G B 0 0 0 V V GS T W V L 2 W 2 μc V V 1 V V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T OX GS T DS GS T DS GS T V T V T0 V BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L
Id Review from Last Lecture Operation Regions by Applications I D 300 250 200 150 100 50 Triode Region Saturation Region Analog Circuits Cutoff Region 0 0 1 2 3 4 5 Vds Digital Circuits V DS Most analog circuits operate in the saturation region (basic VVR operates in triode and is an exception) Most digital circuits operate in triode and cutoff regions and switch between these two with Boolean inputs
Review from Last Lecture Model Extension (BSIM model)
Review from Last Lecture BSIM Binning Model - Bin on device sizes - multiple BSIM models! With 32 bins, this model has 3040 model parameters!
Review from Last Lecture Model Changes with Process Variations (n-ch characteristics shown) I D TT FS or FF (Fast n, slow p or Fast n, fast p ) SS or SF (Slow n, slow p or Slow n, fast p ) V GS3 V GS2 V GS1 V DS Corner models can improve model accuracy
Review from Last Lecture BSIM Corner Models with Binning - Often 4 corners in addition to nominal TT, FF, FS, SF, and SS - bin on device sizes With 32 size bins and 4 corners, this model has 15,200 model parameters!
How many models of the MOSFET do we have? Switch-level model (2) Square-law model Square-law model (with λ and bulk additions) α-law model (with λ and bulk additions) BSIM model BSIM model (with binning extensions) BSIM model (with binning extensions and process corners)
The Modeling Challenge I D Actual Modeled with one model V GS3 (and W/L variations or Process Variations) Local Agreement with Any Model V GS2 (and W/L variations or Process Variations) V GS1 (and W/L variations or Process Variations) V DS (and W/L variations or Process Variations) I G I D V DS I = f V,V D 1 GS DS I = f V,V G 2 GS DS I = f V,V B 3 GS DS V GS I B V BS = 0 Difficult to obtain analytical functions that accurately fit actual devices over bias, size, and process variations
Model Status Simple dc Model Square-Law Model Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations BSIM Model Square-Law Model (with extensions for λ,γ effects) Short-Channel α-law Model Frequency Dependent Small Signal Simpler dc Model Switch-Level Models Ideal switches R SW and C GS
In the next few slides, the models we have developed will be listed and reviewed Square-law Model Switch-level Models Extended Square-law model Short-channel model BSIM Model BSIM Binning Model Corner Models
Square-Law Model I D V GS4 V GS3 V DS V GS2 V GS1 0 V V GS T W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T Model Parameters : {μ,c OX,V T0 } Design Parameters : {W,L} but only one degree of freedom W/L
Switch-Level Models Drain Gate G D Source R SW C GS V GS Switch closed for V GS = 1 S Switch-level model including gate capacitance and drain resistance C GS and R SW dependent upon device sizes and process For minimum-sized devices in a 0.5u process 2KΩ n channel C GS 1.5fF R sw 6KΩ p channel Considerable emphasis will be placed upon device sizing to manage C GS and R SW Model Parameters : {C GS,R SW }
Extended Square-Law Model I I G B 0 0 0 V V GS T W V L 2 W 2 μc V V 1 V V V V V V 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T OX GS T DS GS T DS GS T V T V T0 V BS Model Parameters : {μ,c OX,V T0,φ,γ,λ} Design Parameters : {W,L} but only one degree of freedom W/L
Short-Channel Model 0 V V GS T W I μc V V V V V V V D OX GS T DS GS T DS 1 GS L 1 W μc V V V V V V 2 OX GS T GS T DS 1 GS L V 2 2 2 V α is the velocity saturation index, 2 α 1 T T 2 Channel length modulation (λ) and bulk effects can be added to the velocity Saturation as well
BSIM model Note this model has 95 model parameters!
BSIM Binning Model - Bin on device sizes - multiple BSIM models! With 32 bins, this model has 3040 model parameters!
BSIM Corner Models - Often 4 corners in addition to nominal TT, FF, FS, SF, and SS - five different BSIM models! TT: typical-typical FF: fast n, fast p FS: fast n, slow p SF: slow n, fast p SS: slow n, slow p With 4 corners, this model has 475 model parameters!
Accuracy Complexity Hierarchical Model Comparisons BSIM Binning Models Analytical Numerical (for simulation only) L Number of Model Parameters BSIM Models Number of Model Parameters Square-Law Models Number of Model Parameters Switch-Level Models Approx 3000 (for 30 bins) Approx 100 3 to 6 W Number of Model Parameters 0 to 2
Corner Models Basic Model FF (Fast n, Fast p) FS (Fast n, Slow p) TT Typical-Typical SF (Slow n, Fast p) SS (Slow n, Slow p) Corner Model Applicable at any level in model hierarchy (same model, different parameters) Often 4 corners (FF, FS, SF, SS) used but sometimes many more Designers must provide enough robustness so good yield at all corners
n-channel. p-channel modeling Source Gate Drain Bulk I D 3 V GS4 2.5 D n-channel MOSFET D 2 1.5 1 V GS3 V GS2 G S G D S 0.5 0 0 1 2 3 4 5 VDS GS4 GS3 GS2 GS1 V GS1 V V V V > 0 V DS G B (for enhancement devices) G I G V GS I D D S I B B S V BS V DS 0 VGS VTn W V L 2 W 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B 2 μ C V V V V V V V n OX GS Tn GS Tn DS GS Tn Positive V DS and V GS cause a positive I D
Bulk Source n-channel. p-channel modeling Gate Drain (for enhancement devices) VTp 0 p-channel MOSFET S S G G D S D V GS G I G G I D B S D I B D V BS B V DS 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp Negative V DS and V GS cause a negative I D Functional form of models are the same, just sign differences and some parameter differences (usually mobility is the most important)
Bulk Source n-channel. p-channel modeling Gate Drain (for enhancement devices) VTp 0 p-channel MOSFET S S G G S D G D S D B 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp V GS G I G I D B D I B V BS V DS V GS G I G S B I B -I D D V BS V DS Actually should use C OXp and C OXn but they are usually almost identical in most processes μ n 3μ p May choose to model I D which will be nonnegative
n-channel. p-channel modeling Bulk Source Gate Drain V GS G I G I D S B D I B V BS V DS p-channel MOSFET (for enhancement devices) 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp Alternate equivalent representation 0 V V GS Tp W V L 2 W 2L I =I =0 G B These look like those for the n-channel device but with DS I μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp 2 μ C V V V V V V V p OX GS Tp GS Tp DS GS Tp
D n-channel. p-channel modeling D S S G G G G S D S D S D G B G B S D G I G V GS I D D S I B B V BS V DS V GS G I G I D S B D I B V BS V DS I D 3 2.5 2 1.5 V GS4 V GS3 Models essentially the same with different signs and model parameters 1 V GS2 0.5 0 V GS1 0 1 2 3 4 5 V DS VDS VGS4 VGS3 VGS2 V GS1> 0 0 VGS VTn W V L 2 W 2 μ C V V V V V V V 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B n OX GS Tn GS Tn DS GS Tn 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C p OX VGS VTp VGS VTp VDS VGS VTp
Model Relationships G D R SWn C GSn V GS Determine R SW and C GS in the switch-level model for an n-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) S 0 V V GS T W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T when SW is on, operation is deep triode
Model Relationships G D R SWn C GSn V GS Determine R SW and C GS for an n-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) When on operating in deep triode W V W L 2 L DS I μc V V V μc V V V D OX GS T DS OX GS T DS V 1 1 DS R = 4K SQ I W 1 D V GS =VDD μc V V ( E 4) 3. 5 1 OX GS T L V GS =3.5V 1 S C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF
Model Relationships G D C GSp R SWp V GS Determine R SW and C GS for an p-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 S 0 V V GS T W V L 2 W 2L DS -I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T When SW is on, operation is deep triode
Model Relationships D G C GSp R SWp V GS Determine R SW and C GS for an p-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u Observe µ n \ µ p 3 ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) W V W L 2 L DS -I μ C V V V μ C V V V D p OX GS T DS p OX GS T DS -V 1 1 DS R = 12K SQ -I W 1 1 D V GS =VDD μ C V V ( 4) 3. 5 1 p OX GS T L E V GS =3.5V 3 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF Observe the resistance of the p-channel device is approximately 3 times larger than that of the n-channel device for same bias and dimensions! S
Modeling of the MOSFET Goal: Obtain a mathematical relationship between the port variables of a device. I f V,V,V I I D G B 1 f f 2 3 GS DS BS VGS,V DS,VBS V GS,V DS,VBS Drain V DS I D I B Gate Bulk I D Simple dc Model V GS V BS Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations Frequency Dependent Small Signal Simpler dc Model
Small-Signal Model Goal with small signal model is to predict performance of circuit or device in the vicinity of an operating point Operating point is often termed Q-point
Small-Signal Model y Y Q Q-point X Q x Behaves linearly in the vicinity of the Q-point Analytical expressions for small signal model will be developed later
Design Rules Technology Files Process Flow (Fabrication Technology) Model Parameters
n-well n-well n- p-
Bulk CMOS Process Description n-well process Single Metal Only Depicted Double Poly This type of process dominates what is used for high-volume lowcost processing of integrated circuits today Many process variants and specialized processes are used for lowervolume or niche applications Emphasis in this course will be on the electronics associated with the design of integrated electronic circuits in processes targeting highvolume low-cost products where competition based upon price differentiation may be acute Basic electronics concepts, however, are applicable for lower-volume or niche applicaitons
Components Shown n-channel MOSFET p-channel MOSFET Poly Resistor Doubly Poly Capacitor
C D A A B B C D
Consider Basic Components Only Well Contacts and Guard Rings Will be Discussed Later
A A B B
A A B B
Metal details hidden to reduce clutter A A D G S B D B S B n-channel MOSFET G
A A D G S B B B W L
A A Capacitor Resistor p-channel MOSFET B B n-channel MOSFET
n-well n-well n- p-
N-well Mask A A B B
N-well Mask A A B B
Detailed Description of First Photolithographic Steps Only Top View Cross-Section View
~ Blank Wafer Implant n-well Photoresist Mask p-doped Substrate Will use positive photoresist (exposed region soluble in developer) A A B Develop Expose B
Develop N-well Exposure Photoresist Mask A-A Section B-B Section
Implant A-A Section B-B Section
N-well Mask A-A Section B-B Section
n-well n-well n- p-
Active Mask A A B B
Active Mask A A B B
Active Mask Field Oxide A-A Section Field Oxide Field Oxide Field Oxide B-B Section
n-well n-well n- p-
Poly1 Mask A A B B
Poly1 Mask A A B B
Poly plays a key role in all four types of devices! A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET
Poly 1 Mask A-A Section Gate Oxide Gate Oxide B-B Section
n-well n-well n- p-
Poly 2 Mask A A B B
Poly 2 Mask A A B B
Poly 2 Mask A-A Section B-B Section
n-well n-well n- p-
P-Select A A B B
P-Select A A B B
P-Select Mask p-diffusion p-diffusion A-A Section Note the gate is self aligned!! B-B Section
n-select Mask n-diffusion A-A Section n-diffusion B-B Section
n-well n-well n- p-
Contact Mask A A B B
Contact Mask A A B B
Contact Mask A-A Section B-B Section
n-well n-well n- p-
Metal 1 Mask A A B B
Metal 1 Mask A A B B
Metal Mask A-A Section B-B Section
A A B B
A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET
Should now know what you can do in this process!! Can metal connect to active? Can metal connect to substrate when on top of field oxide? How can metal be connected to substrate? Can poly be connected to active under gate? Can poly be connected to active any place? Can metal be placed under poly to isolate it from bulk? Can metal 2 be connected directly to active? Can metal 2 be connected to metal 1? Can metal 2 pass under metal 1? Could a process be created that will result in an answer of YES to most of above?
How we started this course CAD Tools Circuit Structures and Circuit Design Device Operation and Models Semiconductor and Fabrication Technology
Thanks for your patience!! The basic concepts should have now come together Semiconductor and Fabrication Technology CAD Tools Device Operation and Models Circuit Structures and Circuit Design
How does the inverter delay compare between a 0.5u process and a 0.18u process? V DD V IN V OUT V IN V OUT V SS
How does the inverter delay compare between a 0.5u process and a 0.18u process? Feature 0.5 0.18 Units Vtn 0.81 0.5 V Vtp -0.92-0.53 V ucoxn 109.6 344 ua/v^2 ucoxp 39.4 72.6 ua/v^2 Cox 2.51 8.5 ff Vdd 5 1.8 V fosc-31 94.5 402.8 MHz V IN Assume n-channel and p-channel devices with L=Lmin, W=1.5Lmin V OUT n t HL =R pd C R L pd ncoxw n VDD VTN t LH =R pd C L Lp Rpu C W V V Feature 0.5 0.18 Units L p OX p DD TP C C W L W L L OX n n p p CL 1.88 0.83 ff Rpd 1452 1491 ohms Rpu 2858 3941 ohms THL 2.73 1.23 psec TLH 5.38 3.26 psec f 123 223 GHz Note 0.18u process is much faster than 0.5u process
End of Lecture 17