Fundamentals of ANALOG TO DIGITAL CONVERTERS: Part I.3 Technology January 019 Texas A&M University 1 Spring, 019
Well-Diffusion Resistor Example shows two long resistors for K range Alternatively, serpentine shapes can be used Noise problems from the body Substrate bias surrounding the well Substrate bias between the parallel strips Dummies Texas A&M University Spring, 019
Factors affecting accuracy : Plastic packages cause a large pressure on the die (= 800 Atm.). It determines a variation of the resistivity. For <100> material the variation is unisotropic, so the minimum is obtained if the resistance have a 45 o orientation. compensated Temperature : Temperature gradient on the chip may produce thermal induced mismatch. uncompensated Texas A&M University 3 Spring, 019
Etching Wet etching : isotropic (undercut effect) H F for SiO ; H 3 PO 4 for Al Dx for polysilicon may be 0.75-1 mm with standard deviation 0.1 mm. Reactive ion etching (R.I.E.)(plasma etching associated to bombardment ) : unisotropic. Dx for polysilicon is 0.4 mm with standard deviation 0.03 mm Boundary : The etching depends on the boundary conditions Use dummy strips Texas A&M University 4 Spring, 019
Side diffusion effect : Contribution of endings Interdigitized structure : Texas A&M University 5 Spring, 019
Poly Resistors First polysilicon resistance First polysilicon resistance with a well shielding Second polysilicon resistance Second polysilicon resistance with a well shielding Texas A&M University 6 Spring, 019
TYPES OF INTEGRATED CAPACITORS Electrodes : metal; polysilicon; diffusion Insulator : silicon oxide; polysilicon oxide; CVD oxide C ox t ox WL DC C D r r Dt t ox ox DL L DW W TOP VIEW Texas A&M University 7 Spring, 019
Factor affecting accuracy Oxide damage Impurities Bias condition Bias history (for CVD) Stress D ox ox Grow rate Poly grain size Dt t ox ox Temperature Etching Alignment DL DW ; L W DC C D r r Dt t ox ox DL L DW W DC C 1 0.1% Texas A&M University 8 Spring, 019
Poly1 - Poly Capacitor Poly Poly 1 Area is determined by poly Problems undercut effects nonuniform dielectric thickness matching among capacitors Minimize the rings (inductors) Texas A&M University 9 Spring, 019
Accuracy of integrated capacitors Perimeter effects led the total capacitance: C = C A A A = (x-dx)(y- Dy) = (xy - xdy - ydx - 4Dx Dy) Assuming that Dx = Dy = De A = (xy - De(x + y) - 4D e) A xy - De(x + y) C e = - De(x + y) The relative error is = C e /C = -De(x + y) / xy C A = capacitance per unit area y Dy Real Area of Poly x Dx Then maximize the area and minimize the perimeter use squares!!! Texas A&M University 10 Spring, 019
Common Centroid Capacitor Layout Unit capacitors are connected in parallel to form a larger capacitance Typically the ratio among capacitors is what matters The error in one capacitor is proportional to perimeter-area ratio Use dummies for better matching (See Johns & Martin Book, page 11) Texas A&M University 11 Spring, 019
Common centroid structures C 1 C C 3 C 4 C 5 TC 1 TC TC 3 TC 4 TC 5 C = C 1 C 3 = C 1 C 4 = 4C 1 C 5 = 8C 1 Texas A&M University 1 Spring, 019
Floating Capacitors Be aware of parasitic capacitors Polysilicon-Polysilicon: Bottom plate capacitance is comparable (10-30 %) with the poly-poly capacitance poly C P1 poly1 C P C P C 1 C P1 C1 C P Metal1-Metal: More clean, but the capacitance per micrometer square is smaller. Good option for very high frequency applications ( C~ 0.1-0.3 pf). C P1 substrate CP1, CP are very small (1-5 % of C1) CP is around 10-50 % of C1 metal metal1 substrate C 1 C P Thick oxide CP is very small (1-5 % of C1) Texas A&M University 13 Spring, 019
Design example: Simplest OTA Texas A&M University 14 Spring, 019
Overall amplifier: Have a look on the guard rings and additional deep well! Texas A&M University 15 Spring, 019
BIAS: you may be able to see the dummies, symmetry and S/D connections Texas A&M University 16 Spring, 019
From downstairs Differential pair Texas A&M University 17 Spring, 019
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Details on the P-type current mirrors Texas A&M University 19 Spring, 019