All-Carbon Spin Logic Sensor for RRAM Arrays

All-Carbon Spin Logic Sensor for RRAM Arrays Stephen K. Heinrich-Barna Connected Microcontrollers Texas Instruments, Inc Dallas, TX USA s-barna@ti.com Jean-Pierre Leburton Electrical and Computer Engineering Univ. Illinois at Urbana-Champaign Urbana, IL USA jleburto@illinois.edu Joseph S. Friedman Electrical and Computer Engineering Univ. Texas at Dallas Richardson, TX USA joseph.friedman@utdallas.edu Abstract The high speed of all-carbon spin logic (ACSL) is an ideal match for the non-volatility of resistive random-access memory (RRAM). Combining these two technologies in a computing system provides exceptionally high efficiency, with the possibility of replacing traditional CMOS due to the potential for high speed, low cost, and low energy. Before such a system can be realized, circuits must be designed that interface the ACSL processing with the RRAM storage. This work therefore proposes an ACSL sensor circuit that enables detection of the resistance states in an RRAM array. This sensor circuit and the underlying symmetric latch are validated through a novel behavioral model that enables SPICE simulations of ACSL circuits. Keywords RRAM, spintronics, all-carbon spin logic, graphene nanoribbon, carbon nanotube, magnetoresistance, sense amplifier I. INTRODUCTION Resistive random-access memory (RRAM) has emerged as a potential replacement for embedded non-volatile memories used in the commercial space [1]. The reduced mask count needed for RRAM when compared with FLASH at the same technology node offers a significant cost reduction without significant deleterious impact on power or performance. In order to maximally exploit the advantages that RRAM brings to novel memories, it is necessary to develop logical interface circuits that provide exceptional behavior with the potential for low cost. The recently proposed all-carbon spin logic (ACSL) family [2] is a potential logical counterpart to a computing system with RRAM non-volatile memory. This spintronic logic family is composed of magnetoresistive graphene nanoribbon (GNR) transistors connected with and controlled by carbon nanotubes (CNTs). As the ACSL logical states are encoded with current rather than voltage magnitudes, the delay of ACSL circuits approaches the time required for an electromagnetic wave to propagate through the CNT interconnect. Preliminary estimates indicate an ACSL gate delay in the range of a few hundred femtoseconds and a power-delay product that is two orders of magnitude smaller than 22nm CMOS [2]. Given the exciting potential of carbon-based RRAM structures [3] [5], a solely carbon-based computer can be envisioned with potential economic benefits over CMOS resulting from a fully-carbon system with potential reductions in lithography steps. The advance of this vision is dependent on the interface between the RRAM array and the ACSL information processing circuits. A single-device toggle latch was previously shown [2], providing an ACSL memory concept that can be extended to RRAM interface circuits. However, control logic, drivers, decoders, and power switches have not yet been proposed. It is therefore of interest to develop a stable symmetric latch that serves as a state retention device. This device can then be used to store the value obtained from the state of a resistive memory cell for further processing downstream. The concepts developed for the symmetric latch can then be extended to an RRAM sensor circuit that translates the small-signal bitline current (representing either a 0 or 1 resistive state) to create a fullswing ACSL current output. This paper describes the operation of ACSL and the GNR and CNT devices in section II, presenting physical device parameters and a preliminary model in accordance with the available experimental and simulation data. Section III proposes a symmetric latch and discusses its functionality and performance. In section IV, the symmetric latch concept is extended with the proposal of an RRAM sensor circuit, demonstrating the ability to efficiently transfer information from the RRAM non-volatile memory to the ACSL information processing circuits. Finally, concluding remarks are provided in Section V. II. BACKGROUND: ALL-CARBON SPIN LOGIC Zigzag GNRs have been experimentally and theoretically demonstrated to exhibit negative magnetoresistance when subjected to an applied magnetic field [6] [10]. As depicted in Fig. 1, this GNR magnetoresistance can be controlled by the magnetic fields created by adjacent CNTs [2]. The relative current magnitude and directions of current through these CNTs can be considered as a logical input, while the magnitude of current through the GNR is the output of this logic gate. In ACSL, current magnitudes define the binary states, with a 1 represented as a large current magnitude while a 0 is represented as a small current magnitude [11], [12]. A constant voltage is applied across each GNR such that a change in resistance results in a change in current. These logic gates can Figure 1. An ACSL gate with two CNT control wires adjacent to a GNR [2].

be cascaded by using the output GNR current from one logic gate as the input CNT current for another logic gate, as described in [2]. A. ACSL Device Functionality Depending on the relative magnetization at the two zigzag edges of a GNR, the GNR is in either the ferromagnetic (FM) or antiferromagnetic (AFM) state. The FM state is highly conductive, and is a result of aligned edge magnetization; the GNR is highly resistive when in the AFM state, which results from opposite edge magnetizations [6], [13]. Resistance in the FM state is approximately two orders of magnitude lower than AFM. Placing one or more conductive elements in parallel and in close proximity to the edges of a GNR as in Fig. 1, the currents through these conductive elements can modulate the GNR edge magnetization. In ACSL, CNTs are used as these controlling conductive elements, and are covalently bonded to the GNRs for efficient electrical connectivity. When the currents through the CNT control wires are in the same direction, an XOR gate results in which the inputs and output are current magnitudes. When the currents through the CNT control wires are in opposite directions, the GNR performs the OR function based on the input current magnitudes. This logical functionality is a result of switching between the FM and AFM states due to the edge magnetic fields created by CNT control currents, as described thoroughly in [2]. B. Behavioral Device Model As the physics underlying the GNR magnetoresistance is not fully understood [9], and the analyses of the ACSL basis logic gate remain preliminary [2], the design and simulation of ACSL circuits is impeded by the lack of a device model. In order to initiate the investigation of complex ACSL circuits, a behavioral model is necessary to evaluate the effect of device parameters on the circuit and system. While not predictive of precise voltage and current magnitudes, this behavioral model permits the analysis of circuit structures and design techniques, while also providing materials science researchers with guidance towards the optimization of the device structure. The behavior of a general magnetoresistive spin-diode [14] can be described by = + ( ) ( ), (1) which is here applied to GNRs. R GNR is the resistance of the GNR, R MIN is the minimum resistance in the FM state, R MAX is the maximum resistance in the AFM state, I NET is the additive or counteractive sum of the two input control currents, I CRIT is the threshold I NET current magnitude at which the GNR switches between the FM and AFM states, and N is a slope constant that determines the abruptness of the transition between the FM and AFM states. The CNT is modeled as a resistor with values matching those experimentally observed in [15]. For several of these parameters, reasonable values can be determined based on previously published work [2], [15]. For others, no previous experimental or theoretical work provides guidance for the choice of parameters; values were chosen that TABLE I. GNR BEHAVIORAL MODEL PARAMETER VALUES Parameter Value Reference R GNR 12.6 kω (FM) [2] 1.29 MΩ (AFM) R CNT 20 KΩ [15] I CRIT 2.5 µa V IN 0.12 V N 8 matched intuitive expectations. The GNR parameter values used to analyze the circuits described here are shown in Table I. The resistance changes smoothly from R MAX to R MIN, achieving 37% of the R MAX value at the threshold current, I CRIT. The combined effect of both CNTs determines the state of the GNR by summing the net current (and thus the net magnetic field) adjacent to the GNR. Equal currents flowing in each CNT in the same direction create counteracting magnetic fields, causing the GNR to be in the AFM state. Current flowing in only one of the CNTs, or in opposite directions through both CNTs causes the GNR to be in the FM state when the net current is above a critical level (I CRIT). While not physically precise, this model adequately captures the device behavior to enable transient and operating-point simulations. III. ACSL SYMMETRIC LATCH Latches provide a method by which a state can be stored until a controlling signal alters the state. An initial ACSL latch circuit design was presented in [2], where a toggle latch was shown to maintain a binary state until switched by a toggle pulse. However, the timing constraints of this toggle latch are rather challenging, as the input toggle signal must induce a change in the GNR resistance without interference from the switched output signal. Though the ability to provide this toggle latch functionality with a single GNR is intriguing, the development of a stable symmetric latch is a necessary component for the further advancement of ACSL. A symmetric ACSL latch is shown in Fig. 2. The SET/RESET input current switches the two GNRs such that both GNRs are always in the same state, either FM or AFM. Thus, I CB and I CT are always similar to each other at steady-state, either both being a large 1 current or both being a small 0 current. The output current I OUT is a function of the left GNR resistance, with this I OUT current flowing from a V IN outside this circuit, along the CNT, and through the left GNR to the electrical ground. Thus, when both GNRs are in the AFM state, I OUT is a small 0 current; when both GNRs are in the FM state, I OUT is a large 1 current. The RESET operation is performed as follows: given two GNRs initially in the FM state, large 1 currents flow through the CNTs as shown by the two arrows I CB and I CT. This current Figure 2. ACSL symmetric latch

reinforces the FM states in both GNRs, stabilizing the latch. When a low resistance path to ground is provided at the SET/RESET input node, current flows from the latch to the input, thus reducing the current through I CB. There is therefore reduced current controlling the left GNR, resulting in reduced magnetic field applied to the left GNR. When I CB reaches a value of less than half of I CRIT (and therefore I NET becomes less than I CRIT), the left GNR state changes from FM to AFM. This in turn causes a reduction in the current I CT. When I CT becomes less than half the value of I CRIT (and therefore I NET becomes less than I CRIT), the right GNR also transitions from an FM to AFM state, thus completing the RESET operation. The resistance to ground through I OUT is now maximized at R MAX, due to the fact that the left GNR is in the AFM state. At this point, the low resistance between the input and ground can be removed and the latch retains its AFM/AFM condition and continues to produce a small 0 output current. The SET operation is performed by injected current to the latch from the input node. This current raises I CB from a small 0 current produced by the AFM GNR to a large 1 current due to the inclusion of the input RESET signal current. When the current in I CB is equal to half of I CRIT, the left GNR enters the FM state. The FM state in the left GNR causes sufficient I CT current to also switch the right GNR to the FM state. This right GNR then provides sufficient current into I CB to maintain both GNRs in the FM state. The output current thus becomes 1, and the input SET current can be removed without destabilizing the latch. The operation of this symmetric latch has been demonstrated through the simulation results of Fig. 3 with the behavioral model described in section II.B. The input is driven by pull-up and pull-down ACSL gates, each comprised of a GNR controlled by two CNTs. The output is loaded by two series CNTs from cascaded ACSL gates. V IN has been chosen to be high enough to ensure that the current in the upper and lower CNTs is approximately 60% greater than the current needed to change the two GNRs to FM. As shown in the figure, the latch changes from an initial 0 state, is SET to 1, and then RESET back to 0. Note that when the input current is not applied to the latch (indicated by zero SET and RESET current), the latch maintains its state. IV. SENSOR FOR RRAM ARRAYS As shown in Fig. 4, a non-volatile RRAM array is composed of an RRAM device at each intersection between a bit line and Figure 4. RRAM array with sensors (SA) terminating each bit line (blue) with bits controlled by a word line (red) connecting multiple cells. a word line. When voltage is supplied to a word line, current flows to the various bit lines through the RRAM devices. Depending on the resistance states of the RRAM devices, this bit line current is either large or small. A sensor connected to each bit line converts the RRAM current into a binary signal that can be used within the logic structure. To sense the state within RRAM arrays, it is necessary to detect whether a bit line current is large or small. This task of determining whether an RRAM device is in a conductive or resistive state is well-suited to ACSL circuits, where large and small currents define 1 and 0 states. Therefore, the translation to a voltage required by CMOS sensor circuits is not necessary with ACSL. A. Single-Level Sensor The proposed sensor circuit leverages the concept of the symmetric latch but adds the ability to set the level of the transition to a particular reference value. In this manner, regular reads can be performed at a certain level, with the level later changed for margining or test purposes. The output of the sensing circuit is a measurable change in the resistance of a GNR where the AFM and FM states represent 0 and 1 respectively. Fig. 5 depicts the ACSL bit-current sensor for RRAM arrays comprised of twin ACSL gates. I BIT is the input to the sensor and Figure 3. SPICE simulation of the symmetric latch demonstrating the RESET and SET functionality. Figure 5. ACSL sensor for RRAM arrays.

Figure 7. Cascaded RRAM sensors. Figure 6. The left (blue) and right (red) GNR resistance as a function of I BIT, with I REF = 4 µa. represents the current from the memory cell on the bit line. A non-zero, tunable reference level, I REF, is placed on both sides of the sensor with opposing polarity to create the gain mechanism. At an I BIT near zero, both of the GNR devices are in the FM state and divide the I BIT current, and transfer that portion to the other side s second CNT. As the I BIT is increased, the effect on the left device where the reference and I CR currents are in the same direction is to reduce the net current controlling the GNR. As the reduction of the net current approaches the I CRIT for the left GNR, that device begins to change state to AFM and all of the current from I BIT then flows through the right GNR due to the high impedance seen at the left branch. Fig. 6 shows the change in the resistance of the left GNR as the I BIT is varied from 0 to 10 µa in a DC sweep. As the current approaches the reference level minus the I CRIT, the resistance begins to change until it saturates near the reference level. An interesting feature of Fig. 5 is that as I BIT increases beyond I REF plus I CRIT, both the left and right devices begin to saturate and because the I CR and I CL currents are well above I REF, the I BIT current evenly divides again between the left and right sides. This causes the resistance of the left GNR to drop by almost two orders of magnitude from the R MAX value. Further increasing I BIT above 10 µa results in both GNRs returning to the FM state. In this fashion, the I CRIT level can be considered as the ACSL analog of an input offset on the lower end and a differential common-mode range on the upper end. B. Cascaded Sensors The symmetry in the behavior of the ACSL gates highlights an issue that limits the range of a single sensing circuit. Options to improve the range can include tuning the ACSL gates to have a higher I CRIT, but this gain comes at the cost of the output of the sensor reading high earlier in the I BIT sweep since the width of the region of high resistance can be approximated by twice the value of I CRIT. The sensor can also be made more accurate by reducing the I CRIT level and moving the onset of the resistive increase in the left GNR closer to the I REF level at the cost of saturating at a lower value above I REF. An alternative solution to this issue can be realized by virtue of the current-controlled aspect of the ACSL devices. In the sensor of Fig. 5, I BIT divides between the two branches and provides the values for I CR and I CL. As there is no loss of current Figure 8. The cascaded left GNR resistance as a function of the current I BIT for I REF=4µA (blue), 6uA (green), and 8uA (purple). The right GNR (red) resistance is constant. to a supply, it is therefore possible to recombine the two currents I CR and I I CL and again form I BIT. The recombined current can then be used in a cascaded sensor as shown in Fig. 7. Each sensor can be used with a separate I REF level, and a simple OR function of all left GNR resistance values can be used to ensure the logic state sensed is correct up to higher and higher values of I BIT. GNR resistances for the three cascaded sensors are shown in Fig. 8. With the overlap between each stage, it is therefore possible to tune the I CRIT to a smaller value to provide for a more accurate result at the lower end of the distribution. V. CONCLUSIONS Interfacing RRAM non-volatile storage with ACSL processing has been demonstrated here with novel latch and sensor circuits. These interface circuits have been shown to be feasible using physical device parameters and a preliminary model in accordance with the available experimental and simulation data. An initial exploration of the capabilities and limitations of these circuits was provided, along with techniques for leveraging the current-based nature of ACSL in novel cascaded sensor circuits. These interface circuits serve as building blocks for the potential replacement of CMOS with a computing system that exploits the high speed of ACSL and the non-volatility of RRAM arrays in an economically viable manner. REFERENCES [1] H. Akinaga and H. Shima, Resistive random access memory (ReRAM) based on metal oxides, Proc. IEEE, vol. 98, no. 12, pp. 2237 2251, 2010.

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