Massachusetts Institute of Technology Department of Electrical Engineering and omputer Science 6.002 í Electronic ircuits Homework è3 Solution Handout F9827 Exercise 31: When a particular network having a single port is connected to a 1 kæ resistor, its port voltage is 2:5 V.When the same network is connected to a 4 kæ resistor, its port voltage is 4 V. Determine the Thevenin and Norton equivalents of the network. If we take the Thevenin model of the unknown network, we can get a simple voltage divider relationship. TH V TH Vport port Vport = TH port V TH port Each voltage measurement generates an equation when a resistor is connected to the network. 2:5V = 4V = 1kæ TH 1kæ V TH 4kæ TH 4kæ V TH Solving these two equations gives all the necessary values. V TH = V O =5V TH = N = EQ =1kæ I N =I S = V O = EQ =5m The Norton equivalent just has the I N current source in parallel with N. 1
Exercise 32: This exercise applies two diæerent analyses to determine the unknown node voltages in Network èaè shown below. It illustrates that the direct method of analysis is not always the simplest. èaè Use the node method to ænd the two unknown node voltages in Network èaè. 2 V e 1 e 2 2 Network (a) We write KL at nodes e 1 and e 2 with all currents into the node summing to zero @e 1 V, e 1 2 e 2, e 1, e 1 =0 @e 2 V,e 2 e 1,e 2, e 2 2 =0 Solving these two equations for the node voltages, e 1 = 3 7 V and e 2 = 4 7 V èbè First, explain why Network èaè may be redrawn as network èbè. Second, combine the left source in Network èbè with the two leftmost resistors to form their Thevenin equivalent and redraw the resulting network. Third, combine the right source with the two rightmost resistors to form their Thevenin equivalent and again redraw the resulting network. Finally, using superposition, determine the two unknown node voltages in the thrice redrawn version of Network èaè thereby completing the analysis. V 2 e 1 e 2 2 V V 2 2 V Network (b) 2
From the point of view of either node e 1 or e 2, the wire between the top 2 and resistors just sets that node voltage to V. If we look at network and write the KL equations, the results are the same as network. However, now we can form Thevenin circuits to the left of ' and to the right of '. Looking to the left of ', V TH can be calculated by using a voltage divider and TH is just k 2. Similar calculations for the circuit to the right of ' yield the following results. V THa = V=3 V THb =2V=3 THa =2=3 THb =2=3 So our new circuit looks like this e 1 e 2 V THa THa THb V THb Solving by superposition, if we keep the left source on and turn the right source oæ, e 1 = THb THa THb V THa and vice versa e 2 = THb THa THb V THa e 1 = THa THa THb V THb dding the results we get e 2 = THa THa THb V THb e 1 = 3 7 V e 2 = 4 7 V 3
Problem 31: This problem studies the æuid æow system shown below, and illustrates how the concepts taught in 6.002 can be applied to the study of systems beyond electronic circuits. The æow system comprises a pump, two sections of pipe and two open æuid reservoirs. Note, however, that the joint between the two pipes leaks. The pump draws æuid from the ærst reservoir at ambient pressure and raises the æuid pressure to p PUMP above ambient. This pressure rise pumps the æuid through the two sections of pipe, delivering the æuid to the second reservoir at ambient pressure. It is assumed here that æuid æow in a pipe obeys the linear law p = f where p is the pressure drop across the pipe ènèm 2 è, f is the æuid æow through the pipe èm 3 èsè, and is the æow resistance of the pipe ènsèm 5 è. Note that the pipe sections in the system shown belowhaveæows f 1 and f 2, and æow resistances 1 and 2. In contrast to pipe æow, æuid æow through the leak obeys the nonlinear law f LEK = F LEK p plek =P LEK where p LEK is the pressure rise at the leak, f LEK is the æuid æow through the leak, and F LEK and P LEK are a reference æow rate and pressure, respectively. 1 p LEK 2 f 1 f 2 Leak p PUMP Pump f LEK eservoir mbient Pressure (p = 0) eservoir èaè dopt the following analogy: pressure $ voltage, æuid æow rate $ current and æow resistance $ resistance. Draw the electricnetwork analog to the æuid æow system, but label its node voltages and branch currents with the æow system variables. dditionally, state the æuid æow equivalents to KL and KVL. f 1 f 2 p PUMP 1 p LEK 2 f LEK ΣPressures = 0 KVL around a loop ΣFlows = 0 KL at a node,p PUMP p 1 p 2 =0 KV L f 1, f LEK, f 2 =0 KL 4
èbè Derive a Thevenin equivalent for the pump and the two sections of pipe, and redraw the analog to the æow system accordingly. The terminal variables for the Thevenin equivalent should be,f LEK and p LEK. Use the Thevenin equivalent to simplify the remaining parts of this problem. f 1 f LEK p PUMP 1 2 p LEK f 2 f LEK TH P TH p LEK flek First of all, we can redraw the circuit in part èaè like the circuit on the left since the leak and 2 are in parallel. Now it should be easy to derive a Thevenin to the left of the terminals. P TH = These values give us the circuit on the right. 2 1 2 P PUMP TH = 1 k 2 ècè In terms of f LEK and p LEK, graph the æowpressure relation of the Thevenin equivalent network and the leak on the same graph, and indicate the operating point of the æow system. f LEK P TH TH p LEK f = F LEK LEK P LEK P p TH LEK f = LEK TH operating point P TH p LEK The æowpressure relation of the Thevenin network has a negative slope because the terminal variables are,f LEK and p LEK while the plot is f LEK versus p LEK. You can derive the equation for the line by doing a KVL around the Thevenin circuit. 5
èdè nalytically determine f LEK and p LEK, and then f 1 and f 2. Substituting the equation for the Thevenin into the equation for the leak we get, f 2 LEK = F 2 LEK P LEK èp TH, TH f LEK è Solving the quadratic equation, f LEK = F 2 LEK TH è 2P LEK s 1 4P THP LEK F 2 LEK 2 TH,1è p LEK = f 2 LEK P F 2 LEK LEK f 2 = p LEK 2 f 1 = f 2 f LEK èeè Determine the power delivered by the pump as it pumps the æuid. Hint: consider the electrical analog of power, and check units. Power = p PUMP æ f 1 This gives us units of ènèm 2 èèm 3 èsè which simpliæes to Nm. Power is work s time is forceènèædistanceèmè where work Problem 32: with gates. This problem studies boolean algebra and the implementation of logic functions èaè For the functions F è; ; è and Gè; ; è speciæed in the following truth table, write a corresponding logic expression. F è; ; è Gè; ; è 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0 0 1 1 1 1 1 1 F = æ æ æ æ æ æ æ æ 6
If we simplify F, combining the ærst pair and the second pair, F = æ æ and G = æ æ æ æ æ æ æ æ We can combine the second pair, G = æ æ æ æ æ èbè Implement F è; ; è with 2input NND gates. Hint: Use DeMorgan's laws. Using our simpliæed version of F, DeMorgan's laws, and the fact that a NND gate with X tied into both inputs produces X, F F = è æ è æ è æ è ècè Give an implementation using gates for each of the logic expressions below. lso, write the truth table for expression 1. 1. è èè æ èæd D F è; ; ; Dè 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 0 1 1 1 1 1 1 7
simpliæcation of this expression would be F = è æ æ æ Dè 2. è æ æ DèèD è Using DeMorgan's laws, the fact that X æ X = 0, the fact that X æ X = X, and the distributive law, F =èædèèd æ æ è F = D æ æ 3. æ D æ æ D Using the fact that X X æ Y = X and DeMorgan's, F = D 4. èè èdèææd Using the fact that X XæY=X Y and DeMorgan's, F = æ D æ 1) D F 2) D F 3) D F 4) D F 8
Problem 33: onsider a family of logic gates which operate under the static discipline with the following voltage thresholds: V OL =0:5V,V IL =1:6V,V OH =4:4 V and V IH =3:2V. èaè Graph an inputoutput voltage transfer function of a buæer satisfying the voltage thresholds given above. V O V OH V OL V IL V IH V I ny input below V IL must produce an output less than or equal to V OL and any input above V IH must produce an output greater than or equal to V OH. èbè When transmitting information over a noisy wire, buæers can be used to minimize transmission errors by restoring signal values. onsider the transmission of data over a noisy wire which picks up a maximum of 80 mv symmetric peaktopeak noise per centimeter. How many buæers are needed to transmit a signal over a distance of 2 meters in this noisy environment? 2 meters = 200 cm which translates into 16V of noise peaktopeak centered at 0, meaning our signal could be plus or minus 8 volts from the desired. The smaller noise 8V margin is NM 0 which equals 1.1 volts. is 7 something so we need 8 buæers in 1:1V between the sender and receiver. ècè How large are the 0 and 1 noise margins? Now consider three buæers connected in series and behaving as a single buæer. What are the noise margins for this new buæer? NM 0 = V IL, V OL =1:1V NM 1 = V OH, V IH =1:2V If we look at what happens with a triplebuæer at the sender side and at the receiver side, we realize that the noise margins stay the same. asically this means we are not allowed any more noise during transmission than with a single buæer. If we look at the low noise margin, the minimum voltage the triplebuæer is guaranteed to output for a ëlow" is still V OL = 0.5V èany logic gate under this static disciplineè and likewise, the maximum voltage the receiving triplebuæer is guaranteed to interpret as a ëlow" is still V IL = 1.6V giving us a 0 noise margin of 1.1V 9
èdè Using the switchresistor MOSFET model, design an inverter satisfying the static discipline for the above voltage thresholds using an nchannel MOSFET with n =1kæ and V T =1:8V. ecall, on = n èl=w è. ssume V S =5V and 2 for a resistor is 500 æ. Further assume that the area of the inverter is given by the sum of the areas of the MOSFET and the resistor. ssume that the area of a device is approximately L æ W. The inverter should take as little area as possible with minimum size for L or W being 0:5 çm. Graph the inputoutput transfer function of the inverter. What is the total area of the inverter? What is its maximum static power dissipation? asically, we need to sift through the given information to see what is important. When the MOSFET is oæ, there is no current æowing, thus the power dissipated is zero, and the output is just V S. When the MOSFET turns on, the output must become less than or equal to V OL. voltage divider relationship results in the following equations Substituting, V OL ç on L on V S fter lots of algebra, 0:5 ç 1000 L W 1000 L 500 5 L W W L W æ W L ç 18 If we make each ratio a bit above p 18 or about 4.25 and use the minimum dimension of 0:5 çm, we get the following values for our design MOSFET esistor L =0:5çm and W =2:125 çm L = 2:125 çm and W = 0:5çm T otal rea =2:125 çm 2 on = 235æ L =2:125kæ M aximum Static P ower Dissipation = V 2 S on L =10:6mW 5 V OH V O V OL V T V IL V IH 5 V I 10
Problem 34: èaè Give a resistormosfet implementation of the following two logic functions. 1. æ æ æ D Using DeMorgan's laws, we can transform the expression into æ D D L L Output 2. èy æ W èèx æ W èèx æ Y æ W è Using DeMorgan's laws, we can transform the expression into Y æ W X æ W X W Y Y L L X W L Y W X W Output èbè emember that a NND gate can be implemented as a circuit with two nchannel MOSFETs and a pullup resistor L. Let us call it the NND circuit shown below. These NND circuits are used by PennyWise omputer orporation in their computer boards. In one illfated shipment of computer boards, the outputs of a pair of NND circuits get shorted accidentally resulting in the eæective ircuit X shown below. What logic function does ircuit X implement? onstruct its truth table. L D NND circuit NND circuit E NND ircuit ircuit X 11
Shorting the two NND circuits is like putting two L 's in parallel above the output line and two pairs of MOSFETS in parallel where each pair is in series. ircuit X should implement the following logic function æ æ D D F è; ; ; Dè 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 1 0 1 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0 ècè If we connect n identical NND circuits together in parallel forming ircuit Y as shown in the ægure below, what is the general form of the logic function it implements? If for each MOSFET, on = 500 æ, L = 100 kæ, and V T = 1V, how many NND circuits can we connect in parallel and still satisfy the static discipline for the voltage thresholds given in Problem 33? I 1 I 2 I 3 I 4 NND circuit NND circuit Out I 2n1 I 2n NND circuit ircuit Y 12
The logic function has the following form I 1 æ I 2 I 3 æ I 4 ::: I 2n,1 æ I 2n Taking just one NND gate on, the following must be satisæed V OL ç eq L eq V S We nowhavetwo MOSFETs in series giving us an eq of 1kæ. Our worst case with n circuits would have only 1 of n NND gates on but we can't change the fact that there are n L 's in parallel giving an equivalent of L ènresulting in the following equation. V OL ç eq L =n eq V S Plugging in the values, we see this equation is satisæed for n ç 11.11 so n =11 èdè We now connect 10 identical NND circuits together and have the resulting ircuit Y satisfy the static discipline for the voltage thresholds in Problem 33 with L = 500 æ. Give speciæcations on the dimensions of the MOSFETs such that total MOSFET area is minimized. s before, assume that the area of a device is L æ W. ssume that n = 1kæ and no resistor dimension or MOSFET gate dimension should be smaller than 0:5 çm. For what inputs does ircuit Y dissipate maximum static power, and what is that power? gain looking at one NND circuit, it must satisfy the following equation where eq =2 on = 2kææ L since there are two MOSFETs in series W V OL ç Substituting the values, we get that W L ç 360 eq L eq V S L =0:5çm and W = 180 çm on = 1000 360 = 25 9 To maximize the static power, we want the equivalent on and L to be as small as possible since P ower Dissipation = V 2 S on L If we turn all inputs on, the equivalent on has 10 pairs of MOSFETs in parallel which gives 0.56æ and the 10 L resistors in parallel gives 50æ. P ower Dissipation =0:49W 13