DRAMATIC advances in technology scaling have given us

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004 919 Complementary Ferroelectric-Capacitor Logic for Low-Power Logic-in-Memory VLSI Hiromitsu Kimura, Member, IEEE, Takahiro Hanyu, Member, IEEE, Michitaka Kameyama, Fellow, IEEE, Yoshikazu Fujimori, Member, IEEE, Takashi Nakamura, Member, IEEE, and Hidemi Takasu, Member, IEEE Abstract A novel nonvolatile logic style, called complementary ferroelectric-capacitor (CFC) logic, is proposed for low-power logic-in-memory VLSI, in which storage elements are distributed over the logic-circuit plane. Standby currents in distributed storage elements can be cut off by using ferroelectric-based nonvolatile storage elements, and the standby power dissipation can be greatly reduced. Since the nonvolatile storage and the switching functions are merged into ferroelectric capacitors by the capacitive coupling effect, reduction of active device counts can be achieved. The use of complementary stored data in coupled ferroelectric capacitors makes it possible to perform a switching operation with small degradation of the nonvolatile charge at a low supply voltage. The restore operation can be performed by only applying the small bias across the ferroelectric capacitor, which reduces the dynamic power dissipation. Applying the proposed circuitry in a fully parallel 32-bit content-addressable memory results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6- m ferroelectric/cmos. Index Terms Content-addressable memory (CAM), dynamic logic, ferroelectric capacitor, nonvolatile storage, pass-transistor logic, pseudo non-destructive read operation. I. INTRODUCTION DRAMATIC advances in technology scaling have given us the capability to realize a giga-scaled system-on-a-chip, while rapid increases in the wiring complexity and the global wiring delay have led to serious data-transfer bottlenecks between separated logic modules and memories in current deep-submicron VLSI [1], [2]. Logic-in-memory structures [3], [4], where storage functions are distributed over a logic-circuit plane, provide a key architecture for ensuring highly effective use of internal memory bandwidth. However, usual logic-in-memory VLSI becomes generally complicated, because of the hardware overhead involved in distributing storage elements [5]. Furthermore, the static power dissipation in logic-in-memory VLSI is a critical obstruction for low-power VLSI because distributed storage elements must be connected Manuscript received September 4, 2003; revised March 8, 2004. This work was supported by the IEEE. H. Kimura and M. Kameyama are with the Graduate School of Information Sciences, Tohoku University, Sendai 980-8577, Japan (e-mail: kimura@ngc.riec.tohoku.ac.jp). T. Hanyu is with the Research Institute of Electrical Communication, Tohoku University, Sendai 980-8577, Japan. Y. Fujimori, T. Nakamura, and H. Takasu are with the Semiconductor Research and Development Headquarters, Rohm Company, Ltd., Kyoto 615-8585, Japan. Digital Object Identier 10.1109/JSSC.2004.827802 to the permanent power supply in order not to lose the cell data [6], [7]. As a possible approach to implementing logic-in-memory VLSI, we have already presented ferroelectric-based (FE-based) functional logic gates for highly parallel VLSI systems [8], [9]. FE devices have increasingly attracted attention because of the nonvolatile storage function with a high-speed access capability [10] [12]. Moreover, FE capacitors can sit directly on top of the transistors by means of stacked vias, hence they have an advantage to implement high-density memories. In FE-based logic gates, since both nonvolatile storage and switching functions are performed simultaneously in FE capacitors, chip size and leakage current can be reduced. However, these FE-based functional logic gates are insufficient to implement low-power VLSI because high supply voltage is required to perform the switching operation, which involves a large loss of the dynamic power. To overcome the above serious problems, this paper presents a ferroelectric-based logic circuit, called a complementary ferroelectric-capacitor (CFC) logic for low-power logic-in-memory VLSI [13]. A basic component of the proposed circuit is a CFC logic gate, which is used to perform a switching operation together with FE-based nonvolatile storage. Since both nonvolatile storage and switching functions are merged into FE capacitors by the capacitive coupling effect under the control of external and stored inputs, the active device counts of a CFC logic network become small. In the CFC logic gate, coupled FE capacitors with complementary data storage are introduced to reduce the dynamic power dissipated in logic-in-memory VLSI. Using two FE capacitors where a pair of complementary data representations is stored, the voltage swing generated by the capacitive coupling effect becomes large enough to perform the switching operation at low supply voltage. Moreover, degradation of the nonvolatile charge caused by the switching operation becomes small because the bias voltage across the FE capacitor is always lower than its coercive voltage. Since the disturbed polarization charges can be switched back by only the low reverse voltage across the FE capacitor, the loss of the dynamic power caused by the restore operation becomes small. As a result, the dynamic power and static power dissipated in logic-in-memory VLSI are greatly reduced. As a typical example of the proposed logic-in-memory circuit, a 32-bit content-addressable memory (CAM) [14] is also implemented using 0.6- m ferroelectric/cmos. Its chip size, dynamic power dissipation, and static power dissipation are reduced to about 1/3, 2/3, and 1/7700, respectively, in comparison 0018-9200/04$20.00 2004 IEEE

920 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004 Fig. 2. Ferroelectric capacitor. (a) Cross-sectional view. (b) Symbol. (c) Hysteresis loop characteristic. Fig. 1. Logic-in-memory circuit. (a) Overall structure. (b) Block diagram of a CFC logic gate. with those of a corresponding binary implementation under the same execution time. II. FERROELECTRIC-BASED LOGIC-IN-MEMORY CIRCUIT Fig. 1(a) shows the general structure of a logic-in-memory circuit. It performs a logic function between an external input vector and a stored input vector. Its result is obtained as an output vector. The logic-in-memory circuit is implemented by using a CFC logic gate, which consists of a 1-bit storage element, a logic element and a pass gate as shown in Fig. 1(b). A 1-bit data is stored into the storage element of the CFC gate as a pair of complementary code. When 1-bit external inputs, and, are applied to this gate, a switching operation is performed with a logic function. Since a pass gate turns on only the result of the switching operation becomes 1, the logical AND and OR operations between the CFC logic gates can be implemented by series and parallel connections of the CFC logic gates. Additional precharge and evaluate transistors are used to control precharge and evaluate phases based on dynamic-logic style. In this section, the circuit implementation of the CFC logic gate is discussed. A. Review of a Ferroelectric Capacitor The FE capacitor is physically distinguished from a regular capacitor by substituting the dielectric with an FE material as shown in Fig. 2(a). Fig. 2(b) is a symbol of an FE capacitor. When the voltage is applied across the FE capacitor, the polarization charge in the FE capacitor shows a hysteresis Fig. 3. Nonvolatile charge in a ferroelectric capacitor. loop characteristic with a remnant-polarization charge as shown in Fig. 2(c). Since this remnant-polarization charge is retained at, the FE capacitor is capable of a nonvolatile memory device, where is for a logic value 0 or for 1. If is lower than the coercive voltage, the remnantpolarization charge is never switched to an opposite state and the disturbed polarization charges can be switched back by applying the reverse voltage as shown in Fig. 3. In this case, stored data can be retained in the FE capacitor, so that a pseudo non-destructive operation can be performed. On the other hand, becomes higher than, the polarization charge has shape transitions and the remnant-polarization charge is switched to an opposite state. An example of a destructive operation is a write operation. Since is saturated at, either or is stored into the FE capacitor by or, respectively. The transitive speed of polarization charges is extremely high. Hence, the write speed is as fast as that of DRAM. B. CFC Logic Gate The CFC logic gate consists of four conventional nmos transistors and two identical ferroelectric capacitors as shown in Fig. 4. The transistors, and are used to control voltages at two terminals of ferroelectric capacitors and. The transistor is a pass gate that is used to discharge the match line ML when the gate voltage of is higher than its threshold voltage. A result of the switching operation,, is obtained by the voltage level on the output line OUT.

KIMURA et al.: CFC LOGIC FOR LOW-POWER LOGIC-IN-MEMORY VLSI 921 Fig. 6. Write mode. Fig. 4. Circuit diagram of a CFC logic gate. Fig. 5. Timing diagram. Fig. 5 shows a basic behavior of the CFC logic gate. In the write mode, a pair of complementary voltages which corresponds to a pair of complementary codes, is applied simultaneously to two FE capacitors and, respectively, through bitlines BL1, BL2, and BLw by activating the write line WL. If a stored data is 1, its complementary codes are represented as (1,0), and are set to as shown in Fig. 6. In the case that, and. Then, complementary codes are stored into and as remnant-polarization charges respectively. The execute mode consists of three schemes; the INI- TIALIZE scheme, the OPERATE scheme, and the RESTORE scheme. In the INITIALIZE scheme, BL1 and BL2 are held at, and the reset line RL is set to high in order to initialize the intermediate node between and. In the OPERATE scheme, the precharge control signal PRE is set to high, and and corresponding to external inputs and appear at BL1 and BL2, respectively, as shown in Fig. 7(a). If (for or ), becomes approximately the same voltage as ( ). On the other hand,, the generated voltage strongly depends on stored complementary codes in and, Fig. 7. Execute mode. (a) CFC logic gate in OPERATE scheme. (b) Capacitance of the ferroelectric capacitor. (c) Graphic solution of the generated voltage by using coupled FE capacitors with complementary stored data. because the capacitance of an FE capacitor changes physically depending on the remnant-polarization charge as shown in Fig. 7(b). Let us explain the behavior of the switching operation where (for ) and. In the case of, capacitance of is smaller than that of. Therefore, the voltage across and generated by the capacitive coupling effect becomes high and low, respectively, as shown in Fig. 7(c). Since goes lower than of, remains off. In case of, becomes low and goes higher than. Then, the match line ML is discharged through, and the output becomes 1. Consequently, the gate voltage and a switching state of in OPERATE scheme are summarized in Fig. 8 and Table I, respectively. Hence, the switching function of the CFC logic gate is represented as (1)

922 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004 Fig. 8. Gate voltage generated by using coupled FE capacitors with complementary stored data. Fig. 11(a) and (b) shows measured waveforms and the gate voltage in the CFC logic gate when repetitive execute cycles are performed for stored data 0 and 1. The RESTORE scheme is performed in every execute scheme. In the first 10 cycles, the remnant-polarization charges in and decrease with execute cycles because of distributed polarization charge, which results in decreasing the voltage generated by the capacitive coupling effect. After that, becomes constant and the large voltage swing over 1 V is maintained independent of execute cycles because the distributed polarization charge in and are switched back by a revised voltage in the RESTORE scheme. Consequently, high durability for the repetitive execute cycles is confirmed in the proposed CFC logic gate. TABLE I SWITCHING STATE OF THE PASS GATE The use of complementary stored data makes the output voltage swing large enough to perform the switching operation because of the large capacitance ratio of to. Moreover, the voltages across and never exceed their coercive voltage, so the pseudo non-destructive switching operation can be performed by using coupled ferroelectric capacitors. After some OPERATE schemes, the RESTORE scheme is performed to recover the remnant-polarization charge in the FE capacitor. In this scheme, voltage signals on BL1 and BL2 are inverted, and the disturbed polarization charges caused by excursion along a minor hysteresis loop in and are switched back by reverse voltage. During the standby state, RL is set to high. Since both nodes of and are short-circuited by and, stored data in the FE capacitor is retained steadily. C. Experimental Result Fig. 9 shows a photomicrograph of the fabricated test chip using a 0.6- m ferroelectric/cmos. The ferroelectric capacitors and are fabricated by using with 20- C cm remnant-polarization charge with a ratio of 1. Since this CFC logic gate has regular structure like a memory cell, it is suitable to fabricate the high-density logic-in-memory circuit. Fig. 10(a) and (b) shows waveforms of switching operations measured on the test chip. For the generated voltage adjustment to distinguish on-state and off-state of the pass gate, and are set to 3.1 V and 0.4 V, respectively. As determined by the synchronization of the precharge control PRE, two successive execute phases are demonstrated for one write phase. In these waveforms, the voltage level on ML falls to low, and the output rises to high when the result of in (1) becomes 1. This means that the pass gate in the CFC logic gate turns on in the case of, so that the ferroelectric-based switching operation is performed correctly. III. DESIGN EXAMPLES As an example of the efficient application of the CFC logic circuit, a fully parallel CAM for a 32-bit input word and a 32-bit stored word has been designed. Fig. 12 shows an overall structure of the CAM. Each CAM word circuit performs a magnitude comparison between two kinds of four-valued input words, (the 32-bit external input word) and (the th 32-bit stored input word), and generates a binary output word, ( -bit output) as its comparison result. The magnitude comparison between and is defined as otherwise. The th binary output is equal to. In the following subsection, a hardware algorithm of the magnitude comparison and its circuit design are discussed. A. Hardware Algorithm The magnitude comparison in (2) is represented by two kinds of threshold functions for each bit. One is the greater-than search function,, and the other is the greater-than-or-equal-to search function,, between and where and indicate the th bits of and, respectively. These functions are defined as otherwise otherwise. In general, the magnitude comparison between be represented by using and as Equation (3) is also transformed into (2) -bit words can Consequently, magnitude comparison is performed by two kinds of threshold operations, and, in each bit between and. (3) (4)

KIMURA et al.: CFC LOGIC FOR LOW-POWER LOGIC-IN-MEMORY VLSI 923 Fig. 9. Chip photomicrograph. Fig. 11. Durability for repetitive execute cycles with restore schemes. Fig. 10. Experimental result. (a) Input vector. (b) Measured waveforms of switching operations. B. Circuit Design A 32-bit CAM word circuit given by (4) can be designed by using the proposed CFC logic gate. Two threshold functions and are represented by in (1) as respectively. Since logical AND and OR functions between CFC logic gates are realized by series and parallel connections of CFC logic gates, respectively, the CAM word circuit with 32-bit word length consists of 31 CFC logic gates as shown in Fig. 12. Overall structure of a CAM. Fig. 13(a). In each CAM cell, two kinds of threshold operations and between the th input bit and the stored bit

924 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004 Fig. 15. Evaluation. Fig. 13. CAM word circuit. (a) Block diagram. (b) CAM cell circuit using CFC logic gates. (c) Equivalent CMOS circuit. Fig. 14. Basic behavior of CAM word circuits. are performed by using two CFC logic gates. Fig. 13(b) and (c) show the proposed CAM cell circuit and the equivalent CMOS circuit, respectively. Fig. 14 shows the basic operation of the CAM word circuit. In the write mode, the reset line of the th selected CAM word circuit is set to low. Then, complementary voltage signals ( ) which correspond to complementary codes ( ) are supplied to CFC logic gates through the bitlines,, and. Since both nodes of all FE capacitors in the th unselected CAM word circuits are short-circuited by activating, all stored data in the unselected CAM word circuit are protected. In the execute mode, magnitude comparison is performed by CAM word circuits. First, all of the bitlines are set to in order to perform the INITIALIZE scheme in each CFC logic gate. Then, and are held to 0 V and, respectively, and corresponding to appears at. Simultaneously, two kinds of threshold operations and are performed by two separated CFC logic gates in the th bit CAM cells. A result of magnitude comparison is obtained by the voltage levels on the match line. Finally, the voltage signals on all bit lines are inverted to perform RESTORE scheme. Since revised voltages are applied to all FE capacitors, the disturbed polarization charges are switched back. During the standby state, all reset lines are set to high, and FE capacitors in CFC logic gates are short-circuited. C. Evaluation Fig. 15 summarizes a comparison of 32-bit magnitude comparators in CAMs. The chip size is greatly reduced in the proposed CAM by the CFC logic network, because FE-based threshold functions and nondestructive storage functions are merged into the CFC logic gate. A small number of activedevice counts results in dynamic power reduction of the proposed CAM. Moreover, the use of the CFC logic network reduces standby current in the proposed CAM because CAM cells require no permanent voltage supply in order to hold stored data. Consequently, its chip size and dynamic power dissipation can be reduced to 1/3 and 2/3, respectively, under the same switching speed in comparison with those of a corresponding CMOS implementation. The static power dissipation in the proposed circuit is reduced to 1/7700 of that in a corresponding CMOS implementation. IV. CONCLUSION Complementary ferroelectric-capacitor (CFC) logic is proposed for low-power logic-in-memory VLSI. Since nondestructive storage and high-speed switching functions are merged into

KIMURA et al.: CFC LOGIC FOR LOW-POWER LOGIC-IN-MEMORY VLSI 925 coupled FE capacitors, active device counts of storage and logic elements become small, which reduces dynamic power dissipation. The use of ferroelectric-based nonvolatile storage makes leakage currents cut off. Applying the proposed circuitry in a fully parallel 32-bit CAM results in about 2/3 dynamic power reduction and 1/7700 static power reduction with chip size of 1/3, compared to a CMOS implementation using 0.6- m ferroelectric/cmos. It is expected that new logic-in-memory VLSI using the CFC logic gate would offer attractive features as an emerging technology. While it has been shown to be effective in realizing high-performance CAM, it is likely to be of importance also for ultra-low-power VLSIs for fine-grain computation such as are needed in intelligent vision VLSI processors. ACKNOWLEDGMENT The authors would like to thank K. C. Smith of the University of Toronto, Canada, for many helpful comments. REFERENCES [1] S. Katkoori and P. Maurer, Challenges for CAD in deep submicron regime, Computer Society TCVLSI Tech. Bull., pp. 7 10, 1998. [2] H. Iwai, CMOS technology Year 2010 and beyond, IEEE J. Solid- State Circuits, vol. 34, pp. 357 366, Mar. 1999. [3] W. H. Kautz, Cellular logic-in-memory arrays, IEEE Trans. Comput., vol. C-18, pp. 719 727, Aug. 1969. [4] D. G. Elliott, M. Stumm, W. M. Snelgrove, C. Cojocaru, and R. McKenzie, Computational RAM: Implementing processors in memory, IEEE Des. Test Comput., vol. 16, no. 1, pp. 32 41, Jan. Mar. 1999. [5] T. Hanyu, K. Teranishi, and M. Kameyama, Multiple-valued logic-inmemory VLSI based on a floating-gate-mos pass-transistor network, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 1998, pp. 194 195. [6] A. Chandrakasan, W. J. Bowhill, and F. Fox, Design of High-Performance Microporcessor Circuits. New York: IEEE Press, 2001. [7] H. J. M. Veendrick, Deep-Submicron CMOS ICs. New York: Kulwer BedrijfsInformatie, 1998. [8] T. Hanyu, H. Kimura, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, Ferroelectric-based functional pass-gate for fine-grain pipelined VLSI computation, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2002, pp. 208 209. [9], Ferroelectric-based functional pass-gate for low-power VLSI, in IEEE Symp. VLSI Circuits Dig. Tech. Papers, 2002, pp. 196 199. [10] A. Sheikholeslami, A survey of circuit innovations in ferroelectric random-access memories, Proc. IEEE, vol. 88, pp. 667 689, May 2000. [11] T. Nakamura, Y. Nakao, A. Kamisiwa, and H. Takasu, Electrical properties of Pb(Zr; Ti)O thin film capacitor on Pt and Ir electrodes, Jpn. J. Appl. Phys., vol. 34, no. 9B, pp. 5184 5187, 1995. [12] D. Takashima and I. Kunishima, High-density chain ferrlelectric random access memory (chain FRAM), IEEE J. Solid-State Circuits, vol. 33, pp. 787 792, May 1998. [13] H. Kimura, T. Hanyu, M. Kameyama, Y. Fujimori, T. Nakamura, and H. Takasu, Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI, in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, 2003, pp. 160 161. [14] T. Hanyu, N. Kanagawa, and M. Kameyama, Design of a one-transistor-cell multiple-valued cam, IEEE J. Solid-State Circuits, vol. 31, pp. 1669 1674, Nov. 1996. Hiromitsu Kimura (M 03) received the B.E. degree in electrical engineering and the Master of Information Science and Doctor of Information Science degrees in computer and mathematical sciences from Tohoku University, Sendai, Japan, in 1998, 2000, and 2003, respectively. He is currently a Research Associate in the Graduate School of Information Sciences, Tohoku University. His main research interests and activities are in nonvolatile logic-in-memory circuit technologies and its application to highly parallel VLSI computing. Dr. Kimura received the Judge s Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News of Japan in 2002. Takahiro Hanyu (M 89) received the B.E., M.E., and D.E. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1984, 1986, and 1989, respectively. He is currently a Professor in the Research Institute of Electrical Communication, Tohoku University. His general research interests include nonvolatile logic-in-memory circuit technologies, low-power multiple-valued integrated circuit technologies, and their application to next-generation VLSI computing. Dr. Hanyu received the Outstanding Paper Award at the IEEE International Symposium on Multiple-Valued Logic in 1986, the Distinctive Contribution Award at the IEEE International Symposium on Multiple-Valued Logic in 1988, the Niwa Memorial Award in 1988, the Sakai Memorial Award from the Information Processing Society of Japan in 2000, and the Judge s Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News of Japan in 2002. Michitaka Kameyama (M 79 SM 91 F 97) received the B.E., M.E., and D.E. degrees in electronic engineering from Tohoku University, Sendai, Japan, in 1973, 1975, and 1978, respectively. He is currently a Professor in the Graduate School of Information Sciences, Tohoku University. His general research interests include intelligent integrated systems for real-world application and robotics, VLSI processor architecture and high-level synthesis, and multiple-valued VLSI computing. Dr. Kameyama received the Outstanding Paper Awards at the 1984, 1985, 1987, and 1989 IEEE International Symposiums on Multiple-Valued Logic, the Technically Excellent Award from the Society of Instrument and Control Engineers of Japan in 1986, the Outstanding Transactions Paper Award from the IEICE in 1989, the Technically Excellent Award from the Robotics Society of Japan in 1990. Yoshikazu Fujimori (M 03) was born in Osaka, Japan, on December 7, 1971. He received the B.E. and M.E. degrees in electronics engineering from Kyoto University, Kyoto, Japan. In 1996, he joined Rohm Company, Ltd., Kyoto, where he has been working on device and process development of ferroelectric random access memory (FeRAM). His research interests include logic applications of ferroelectric materials. Mr. Fujimori received the Judge s Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News Japan in 2002 and the Best Presenters Awards from IEEE Electron Device Society Kansai Chapter in 2004.

926 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 6, JUNE 2004 Takashi Nakamura (M 98) was born in Osaka, Japan, on May 3, 1965. He graduated in physics from Kansei Gakuin University, Japan, in 1990. He received the Doctor degree in engineering from Kyoto University, Kyoto, Japan, in 1998. In 1990, He joined Rohm Company, Ltd., Kyoto, Japan, where he has worked in research and development on ferroelectric random access memory (FeRAM). Dr. Nakamura received the Judge s Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News Japan in 2002. Hidemi Takasu (M 00) was born in Japan in 1948. He received the B.S. degree in science from Ritumeikan University, Kyoto, Japan. In 1971, he joined Rohm Company, Ltd., Kyoto, Japan, where he worked on the development of semiconductor process. In 1991, he was General Manager of the VLSI Research and Development Division, where he has managed research and development of nonvolatile memories. In 1998, he became a Board Member of Rohm. Mr. Takasu received an award from the International Symposium on Ingetrated Ferroelectrics (ISIF) in 2001, and the Judge s Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News Japan in 2002.