Supporting Information Assembly and Densification of Nanowire Arrays via Shrinkage Jaehoon Bang, Jonghyun Choi, Fan Xia, Sun Sang Kwon, Ali Ashraf, Won Il Park, and SungWoo Nam*,, Department of Mechanical Science and Engineering, University of Illinois, Urbana-Champaign, Urbana, IL 61801 Division of Materials Science and Engineering, Hanyang University, Seoul, 133-791, Republic of Korea Department of Materials Science and Engineering, University of Illinois, Urbana-Champaign, Urbana, IL 61801 Methods Supporting Figures: Figure S1: A photo of contact printing stage. Figure S2: Scanning electron microscope images of NW arrays following shrink induced assembly. Figure S3: Schematic drawing of geometrically controlled shrinkage. Figure S4: Scanning electron microscope images of shrink assembled NWs with initial misalignment. Figure S5: X-ray photoelectron spectroscopy result of SiNW assembly on a SiO 2 /Si substrate after Au film etching. Figure S6: Dark-field optical microscope image of NW arrays before and after transfer to a SiO 2 /Si substrate. Figure S7: Shrink-assembled NW field-effect transistors. 1
Methods (1) Synthesis of Si nanowires (NWs) Si NWs were synthesized via the vapor-liquid-solid process using a 5 nm thick Au film catalyst on a SiO 2 /Si substrate deposited by thermal evaporation. During the Si NW growth, a piece of the substrate was first placed in a chemical vapor deposition (CVD) tube furnace and annealed at 600 C for 20 min in vacuum. The temperature was then gradually decreased to 500 C followed by introducing 50 sccm H 2, 10 sccm SiH 4 (10%) and 5 sccm B 2 H 6 (100 ppm) into the CVD chamber to initiate the synthesis reaction. The growth was performed at 40 Torr for 20 min, which produced high density SiNWs on entire substrate. (2) Polystyrene (PS) substrate preparation A piece of PS sheet (Shrinky Dinks, K & B Inovations, Inc.) was immersed in acetone and isopropanol mixed solvent bath (1:1 volume ratio) for 10 seconds to clean the surface. After cleaning, the PS substrate was rinsed with fresh isopropanol and blow-dried with a N 2 gun. (3) Contact printing of NWs A PS substrate was attached to the contact printing stage (Figure S1) with double sided tape. A piece of wafer (7 mm 12 mm) with the synthesized NWs on top was attached to the bottom of the pillar post (Ø 25mm, 190 g). The post was placed onto the substrate so that the NWs could face the PS substrate. The PS substrate traveled with a single axis translation stage to induce shear force between the NWs and PS substrate (traveling speed, 1 mm/sec). (4) Shrink-induced assembly A PS substrate with NWs was clamped with a customized clamp for uniaxial shrinkage. Then the PS substrate was sealed with a glass beaker cover to prevent contamination during the heating process. The PS was then put into a dry oven (150 ) and heated for 40 min for shrink-induced assembly. (5) Solution transfer of shrink-assembled NWs To transfer the shrink-induced NW arrays from PS to other substrates, a metal encapsulation layer (5 nm Cr, 100 nm Au) was deposited onto the NW array with a thermal evaporator (Kurt J. Lesker Nano 36). The metal coated sample was immersed in a toluene bath (ACS reagent, 99.5%, SIGMA-ALDRICH ) for 1 hour to dissolve the PS substrate. After dissolving the PS, the metal film/nw array was moved to another toluene bath for rinsing. The target substrate (SiO 2 wafer, Kapton film, or glass flask) was immersed into the toluene bath and the metal film/nw array was gently fished out from the bath. The sample was then blow-dried with a N 2 gun. For better attachment, the sample was kept in a desiccator overnight. Finally, the Au/Cr layer was removed with Au etchant and Cr etchant, respectively. We note that the solution transfer method using metal thin film is likely to be limited to a monolayer NW transfer. 2
(6) NW field-effect transistor (FET) fabrication and measurement Shrink assembled NW array was transferred on to a 50nm SiO 2 /Si wafer (Nova Electronic Materials) using the solution transfer method. The source/drain electrodes were patterned with photolithography and metallized (CHA e-beam evaporator) with Ni (70 nm). Buffered oxide etch (BOE) of SiNWs prior to Ni contact metallization was carried out to remove surface oxide. Measurements were conducted with a probe station (model PM8, Karl Suss) and a sourcemeter (model 2614B, Keithley). The source-drain voltage was set to 1 V and the gate voltage was swept from -15 V to 15 V. 3
Figure S1. A photo of contact printing stage (scale bar, 2 cm). 4
Figure S2. Scanning electron microscope images of NW arrays following shrink induced assembly. (a) Initial NW density was set at 1.25 NWs/µm. We were able to achieve density amplifications of 2.25 NWs/µm (190% shrinkage; (b)) and 4 NWs/µm (310% shrinkage; (c)) (scale bars, 1 µm). 5
a b c w l 1 l 2 l 3 Figure S3. Schematic drawing of geometrically controlled shrinkage. Areas with blue diagonal lines indicate clamping region. Width (w) was 2 cm in each case and respective lengths were (a) l 1 =1cm, (b) l 2 =2cm, (c) l 3 =3cm. 6
Figure S4. Scanning electron microscope images of shrink assembled NWs with initial misalignment of 30 (a), 45 (b) and 90 (c). Inset shows the angle of initial misalignment of the NWs. Red dash lines indicate the shrinking direction (scale bars, 1 µm). 7
Figure S5. X-ray photoelectron spectroscopy (XPS) result of SiNW assembly on a SiO 2 /Si substrate after Au film etching. The result shows negligible amount of Au detected by XPS. 8
Figure S6. Dark-field optical microscope image of NW arrays before transfer (a) and after transfer (b) to a SiO 2 /Si substrate (scale bars, 50 µm). 9
Figure S7. Shrink-assembled NW field-effect transistor. (a) Transfer characteristics of shrink assembled NW FETs (red) and NW FETs without shrink assembly (black). Output characteristics at low source-drain voltage of both NW FETs showed a linear behavior. SEM images of shrink-assembled NW FET (b) and NW FET without shrink assembly (c) (scale bars, 5 µm). 10