RECENTLY, A junctionless (JL) double-gate (DG) fieldeffect

39 IEEE TRANSACTIONS ON EECTRON DEVICES, VO. 59, NO. 1, DECEMBER 1 Surface-Potential-Based Drain Current Model for ong-channel Junctionless Double-Gate MOSFETs Zhuojun Chen, Yongguang Xiao, Minghua Tang, Ying Xiong, Jianqiang Huang, Jiancheng i, Xiaochen Gu, and Yichun Zhou Abstract A surface-potential-based model is developed for the symmetric long-channel junctionless double-gate MOSFET. The relationships between surface potential and gate voltage are derived from some effective approximations to Poisson s equation for deep depletion, partial depletion, and accumulation conditions. Then, the Pao Sah integral is carried out to obtain the drain current. It is shown that the model is in good agreement with numerical simulations from subthreshold to saturation region. Finally, we discuss the strengths and limitations i.e., threshold voltage shifts) of the JFET, which has been recently proposed as a promising candidate for the JFET. Index Terms Double gate DG), junctionless J) MOSFET, surface potential, threshold voltage shift. I. INTRODUCTION RECENTY, A junctionless J) double-gate DG) fieldeffect transistor DGFET) J DGFET) has been reported 1] 3] as a promising candidate for future technology nodes. The fabricated device with a high content of impurity concentration within the channel and source/drain S/D) regions requires no junctions and exhibits many advantages 4] 7], such as the simplified flexible fabrication process, nearly ideal subthreshold slope SS 6 mv/dec), high ON OFF-current ratio I ON /I OFF > 1 7 ), low S/D series resistance, and small drain-induced barrier lowering. Moreover, the J transistor shows many interesting characteristics, like conductance oscillations at low temperature 8] and hightemperature behavior 9]. Manuscript received April 8, 1; revised June 18, 1, August 5, 1, and September 5, 1; accepted September 4, 1. Date of publication October 18, 1; date of current version November 16, 1. This work was supported in part by the Key Project of National Natural Science Foundation of China NSFC) under Grant 1131, by NSFC under Grants 517171, 617417, 6117693, and 1175163, by PCSIRT under Grant IRT18, by 973 Program under Grant 1CB3644, by the Hunan Provincial Innovation Foundation for Postgraduate under Grant CX11B48, and by the Doctoral Program of Higher Education of China under Grant 1431111. The review of this paper was arranged by Editor D. Esseni. Z. J. Chen and M. H. Tang are with the Key aboratory of ow Dimensional Materials and Application Technology, Ministry of Education, Xiangtan University, Xiangtan 41115, China e-mail: zhuojunchan@yahoo.cn; mhtang@ xtu.edu.cn). Y. G. Xiao, Y. Xiong, J. Q. Huang, and Y. C.. Zhou are with Xiangtan University, Xiangtan 41115, China e-mail: ygxiao@xtu.edu.cn; xiongying@ xtu.edu.cn; hjq_hjq8@yahoo.cn; zhouyc@xtu.edu.cn). J. C. i and X. C. Gu are with ASIC R&D Center, College of Electronic Science and Engineering, National University of Defense Technology, Changsha 4173, China e-mail: lijc@nudt.edu.cn; xc.gu61@gmail.com). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 1.119/TED.1.1164 Due to the excellent electrostatic performance of the J DGFET, it is necessary to develop an accurate model to investigate its theoretical foundations, to better understand the behavior of this device, and to elucidate its strengths and weaknesses. Duarte et al. 1] first proposed a simple bulk current model relying on depletion approximation for the J DGFET but neglected the accumulation condition. Then, Sallese et al. 11] carried out a space-charge-based model for the J DGFET to calculate the charge density and drain current, but it may cause convergence problems. Subsequently, Duarte et al. 1] proposed a nonpiecewise model for the J DGFET based on parabolic potential approximation by a uniform charge potential relationship. However, few studies have been carried out to develop a surface-potential-based compact model for the J DGFET valid in all regions, which includes a more physical and accurate description of the transistor behavior and is commonly accepted in compact modeling applications. In this paper, a regional approach is used to establish the relationships between surface potential and gate voltage by a separate consideration of the accumulation, partial depletion, and deep depletion conditions. With the derived surface potential model, the Pao Sah integral is analytically obtained, which leads to a full-range drain current model. In particular, ambert W -function is used to express the subthreshold current, which is more accurate than that in previous studies 1], 1]. Finally, we discuss the strengths and the limitations i.e., threshold voltage shifts) of the J DGFET for future technology developments. II. DEVICE STRUCTURE AND OPERATION We assume a J DG MOSFET with channel length, silicon thickness t Si, oxide thickness t ox, and a uniform impurity concentration N D within the channel and S/D regions. The cross section of a symmetric J DGFET is shown in Fig. 1a). The operating principle of an n-channel J DGFET differs from the conventional inversion-mode DGFET. In the subthreshold region, the gate field pushes the majority carriers away from the surfaces, and the silicon body is fully depleted, as is shown in Fig. 1b). By increasing the gate voltage, the electric field in the channel reduces. In the above-threshold region, the depletion width in the body decreases, and the device forms a conducting channel in the center squeezed by depleted regions near the silicon surface, as is shown in Fig. 1c). Then, a completely neutral channel is created, and the bulk current tends to reach its maximum value when the gate voltage increases to flatband 18-9383/$31. 1 IEEE

CHEN et al.: DRAIN CURRENT MODE FOR ONG-CHANNE J DG MOSFETs 393 and N D is replaced by intrinsic carrier concentration 13]. An approximate solution of 1) can be obtained by using a regional approach and taking different assumptions or approximations under accumulation, partial depletion, and deep depletion conditions. In the accumulation mode, the electric field drops down very quickly to zero, and the electric potential ϕx) V, without consideration of volume inversion 14]. Using Taylor expansion, we can simplify 3) as { ) ] qn D ϕs V E s exp 1 ϕ } s V. 5) ε Si Fig. 1. a) Schematic description of a symmetric n-channel J DGFET simulated with Sentaurus Device 14]. b) Electron density of J DGFET in the fully depleted mode V G <V TH ). c) Electron density of J DGFET in the partly depleted mode V TH <V G <V FB ). d) Electron density of J DGFET in the accumulation mode V G >V FB ). voltage. By further increasing the gate voltage, the device eventually forms electron accumulation layers at the surfaces and produces large surface current, as is shown in Fig. 1d). III. SURFACE POTENTIA MODE According to the classic model and Boltzmann statistics, one can write Poisson s equation in the silicon body as d ϕ dx = q ) ] ϕ V N D exp 1 1) ε Si where q is the electronic charge, ε Si is the permittivity of silicon, = kt/q is the thermal voltage, ϕx) is the electrostatic potential, and V is the electron quasi-fermi potential. It has been assumed that the hole density is negligible compared with the electron density. Equation 1) must satisfy the following boundary conditions: dϕ dx = ϕ ± t ) Si = ϕ s. ) x= Once integrating 1), we obtain Es = qn ) ) D ϕs V ϕ V exp exp ϕ ] s ϕ ε Si 3) where ϕ = ϕ x = ) is the potential at the center of the silicon film and ϕ s is the surface potential. According to Gauss s law, the relationship between surface potential ϕ s and gate voltage V G is determined as dϕ Q SC = ε Si dx x=± t Si = C ox V G V FB ϕ s ). 4) Here, Q SC is the space charge density per unit area, C ox = ε ox /t ox is the capacitance of the oxide, V FB Φ MS is the flatband voltage, and Φ MS is the work function difference between the gate electrode and n-type silicon. Despite its apparent simplicity, 1) has no closed-form analytical solution, as opposed to the case of an undoped DG MOSFET where the 1 term on the right-hand side is missing Noting that the ratio between the term in the bracket and the term ϕ s V )/ is larger than unity for aforementioned flatband conditions and becomes unity at the flatband 11], we propose to omit the term ϕ s V )/ in the square root. Hence, the surface electric field in accumulation can be expressed as ) ] qn D ϕs V E s exp 1. 6) ε Si Substituting E s obtained from 6) into 4), after some manipulation, we thus obtain a relationship between surface potential and gate voltage valid in the accumulation region ) ] V G V FB ϕ s ) ϕs V = β exp 1 7) where β = ε Si qn D /Cox. In the partly depleted mode, we can take a depletion approximation to derive the relationship ϕ s V G for simplicity. Under the coordinates shown in Fig. 1a), the solution of Poisson s equation is ϕx) =ϕ qn D ε Si )] tsi x x d 8) for the depletion width x d t Si /. Replacing ϕ with V, the surface potential is therefore ϕ s = V qn D x ε d. 9) Si The space charge density in this limit is Q SC = qn D x d = C ox V G V FB ϕ s ). 1) The combination of 9) and 1) leads to the following relationship between ϕ s and V G in the partly depleted mode: ϕ s = V 1 β V G V FB ϕ s ). 11) It is worth mentioning that the gate voltage can be expressed as the sum of the flatband voltages; the voltage drops across the semiconductor and the oxide layer V G = V FB + ϕ s + ϕ ox = V FB qn D x d qn D x d t ox. ε Si ε ox 1)

394 IEEE TRANSACTIONS ON EECTRON DEVICES, VO. 59, NO. 1, DECEMBER 1 Then, the threshold voltage can be found in 1) by setting x d = t Si /, yielding the following: V TH = V FB qn Dt Si 13) C eff with C 1 eff =4C Si) 1 +C ox ) 1 and C Si = ε Si /t Si. However, the depletion approximation presented earlier is not quite suitable for subthreshold conditions. The usual solution to derive the drain current is to carry out charge carrier statistics 1]; however, we use deep depletion approximation based on surface potential. In this limit, the difference between the potential at the center of the silicon body and the surface potential is ϕ ϕ s = qn Dt Si. 14) 8ε Si Combining 3) and 4), we can obtain V G V FB ϕ s qnd ε Si α = 1 1 exp α) α C ox ) ϕ V exp 15) where α =ϕ ϕ s )/ is the normalized difference of potentials. Then, ϕ s can be calculated by solving this transcendental equation. For the below-threshold regime, the term 1 exp α))/α < 1 and 15) can be simplified through expanding the square root. After some rearrangements, it can be rewritten as V G V FB ϕ s = qn Dt Si 1 1 )] C ox exp ϕ V. 16) The explicit expression of surface potential can be written as ϕ s = V G V TH qn Dt Si 8C Si )] qnd t Si VG V TH V W exp 17) 4C ox where W is the ambert W -function which is the inverse of the function z = W z)e W z) 15]. The ambert-w function has already proved its usefulness in numerous physics applications and has also been recently utilized for finding the solutions to bipolar transistor 16] circuit analysis problems. Fig. shows the relationship between ϕ s and V G of the J DGFET for different impurity concentrations, oxide thicknesses, and silicon thicknesses, with the quasi-femi potential V =. The proposed model represented in 7), 11), and 17) is in good agreement with numerical simulations of the longchannel J DGFET, and the transitions between adjacent regions are smooth as required. IV. DRAIN CURRENT MODE The mobile charge density Q m can be written as Q m = Q SC Q d 18) where Q d = qn D t Si is the fixed charge density. According to the current continuity condition, the current is given by I DS = μw d Q m dv/dy. Here, μ is the carrier mobility assumed to Fig.. Surface potential of the J DGFET against the gate voltage for different a) impurity concentrations, b) oxide thicknesses, and c) silicon thicknesses with the quasi-femi potential V =, compared with numerical simulations. be a constant along the channel), and W d is the device width. Making use of the gradual-channel approximation, replacing the mobile charge density in 18) and then integrating I DS dy from the source to the drain, we can express the Pao Sah integral as I DS = μ W d = μ W d V DS V DS Q m dv C ox V G V FB ϕ s )+Q d ] dv 19) with the assumption of V S = and V D = V DS. Based on the surface potential model developed in Section III, a compact analytical expression for the drain current is proposed valid in all regions of operation. If V G >V FB + V DS, the whole channel of the J DGFET is in the accumulation mode. In this case, differentiating 7) with respect to ϕ s leads to dv V G V FB ϕ s = 1 + dϕ s V G V FB ϕ s ). ) + β After calculating the integral in 19), we obtain the following expression for the drain current: I DS = μ W d Q d V 4C ox V G V FB ϕ s ) C ox V G V FB ϕ s ) + 4C ox βvt arctan VG V FB ϕ s βvt )] D S 1)

CHEN et al.: DRAIN CURRENT MODE FOR ONG-CHANNE J DG MOSFETs 395 where S and D denote the limits ϕ s ) and ϕ s ), respectively. Hence, the current in accumulation can be calculated from the surface potential evaluated from 7) at the source and the drain. If V TH <V G <V FB, the whole channel of the J DGFET is in the partly depleted mode. From 11), we obtain dv = 1 dϕ s β V G V FB ϕ s ). ) Similarly, the drain current in depletion becomes Q d V C ox V G V FB ϕ s ) I DS = μ W d + 4 ] D 3β C oxv G V FB ϕ s ) 3. 3) S If V FB <V G <V FB + V DS with V DS >, the channel is biased in the accumulation mode from the source to some flatband position and biased in the partly depleted mode from the flatband coordinate to the drain. Under the circumstances, the integral in 19) must be divided into two parts, and the total current has to be written as the sum of two components, each being calculated by 7) and 11). Then, we can obtain the drain current in hybrid channel I DS =μ W d V G V FB Q d V DS +C ox V G V FB ϕ s )dv V DS + C ox V G V FB ϕ s )dv V G V FB dep acc. 4) If V G <V TH, the whole channel of the J DGFET is in the fully depleted mode, entering into the subthreshold region. From 17), we can obtain the subthreshold current as follows: I DS =μ W d C ox V DS W 4C ox β exp VG V TH V Qd )] dv. 5) In terms of the regional approach, a simple interpolation 17] of the form { I ) sub ) } 1 I DS = DS + I dep DS 6) is adopted in the partially depleted region, where I dep DS and IDS sub correspond to the partial depletion current and subthreshold current, which can be calculated from 3) and 5), respectively. It can provide good agreement with the numerical simulation results. Moreover, the current in hybrid channel ensures the continuity between accumulation condition and partial depletion condition. V. M ODE VERIFICATION AND DISCUSSION In order to validate the proposed model, numerical simulations were carried out with the TCAD tool Sentaurus Device 18]. Due to the long-channel device, the ombardi mobility Fig. 3. Output characteristic calculated from lines) the proposed model of the J DGFET for V G ranging from.5 to 1 V in steps of.5 V, compared with symbols) numerical simulation results. Fig. 4. Transfer characteristic obtained from lines) the proposed model of the J DGFET for V DS ranging from.1 to.5 V in steps of. V, compared with symbols) numerical simulation results. model is employed, accounting for the dependence on the impurity concentration as well as the transverse and longitudinal electric field values. Also, the Shockley Read Hall recombination model and the Fermi Dirac carrier statistics are used through simulation. Despite the relatively low impurity concentration within the channel and the S/D regions, dopingdependent bandgap narrowing model is included. Through simulations, the channel length and the device width are equal to 1 μm to avoid short- and narrow-channel effects, while the source and drain lengths are 1 nm to avoid parasitic resistance effects. In addition, the gate work function is set to be 5. ev. Then, the effective mobility value extracted from the simulations is 1 cm /V s for devices with an impurity concentration of 1 19 cm 3. Fig. 3 shows the output characteristic of the J DGFET for V G ranging from.5 to 1 V in steps of.5 V. The model lines) shows good agreement with the simulation results symbols). At higher drain voltages, the J DGFET is saturated as is expected. Figs. 4 7 show the transfer characteristic of the J DGFET for various drain voltages, channel lengths, oxide thicknesses, silicon thicknesses, and impurity concentrations, respectively. The same currents are plotted on both logarithmic left) and linear right) scales. We can find that the agreement

396 IEEE TRANSACTIONS ON EECTRON DEVICES, VO. 59, NO. 1, DECEMBER 1 Fig. 5. Transfer characteristic obtained from lines) the proposed model of the J DGFET for t ox ranging from to 8 nm in steps of 3 nm, compared with symbols) numerical simulation results. Fig. 8. Transconductance obtained from lines) the proposed model of the J DGFET for t ox ranging from to 8 nm in steps of 3 nm, compared with symbols) numerical simulation results. Fig. 6. Transfer characteristic obtained from lines) the proposed model of the J DGFET for t Si ranging from 8 to 1 nm in steps of nm, compared with symbols) numerical simulation results. Fig. 9. Output conductance obtained from lines) the proposed model of the J DGFET for V G ranging from.5 to.5 V in steps of.5 V, compared with symbols) numerical simulation results. Fig. 7. Transfer characteristic obtained from lines) the proposed model of the J DGFET for N D ranging from 5 1 18 to 1 19 cm 3 in steps of.5 1 18 cm 3, corresponding to μ varying among 15, 11, and 1 cm /V s, compared with symbols) numerical simulation results. of the model with simulation results is quite good in the whole range of the applied gate voltages, and transitions at the boundaries among the subthreshold, partial depletion, and accumulation regions are relatively smooth. Fig. 8 shows the transconductance characteristic of the J DGFET for various oxide thicknesses, and Fig. 9 shows the output conductance characteristic of the J DGFET for various gate voltages. Good agreement between the model and simulation results further validates the proposed model. In previous studies 4] 7], the J DGFET device presents many advantages, such as the simplified manufacturing process, nearly ideal subthreshold slope, high I ON /I OFF ratios, and small DIB, which is quite comparable with that of the conventional inversion-mode DGFET with the same geometry, making it attractive for future technology nodes. However, due to its heavily doped channel, the threshold voltage shift is significantly larger than that of the undoped channel transistor, just as mentioned in 19]. In order to quantify the threshold voltage sensitivity of the J DGFET, we can calculate the threshold voltage shifts caused by variations of the impurity concentration, silicon thickness, and oxide thickness. Fig. 1 shows the threshold voltages obtained from 13) for different impurity concentrations, silicon thicknesses, and oxide thicknesses, in good agreement with numerical simulations. We observe that the threshold voltage decreases with thicker

CHEN et al.: DRAIN CURRENT MODE FOR ONG-CHANNE J DG MOSFETs 397 variability issue even more severe, owing to the limited control of geometry and impurity concentration. Fig. 1. Threshold voltages obtained from lines) the proposed model of the J DGFET for various a) oxide thicknesses and b) silicon thicknesses as a parameter of impurity concentration, compared with symbols) numerical simulation results. VI. CONCUSION In this paper, we have proposed an analytical model to calculate the surface potential and the drain current for a symmetric long-channel J DGFET. Constant carrier mobility is employed; short-channel and quantum effects are not included in the developed model. Due to no closed-form solution of Poisson s equation, appropriate simplifying assumptions are taken under deep depletion, partial depletion, and accumulation conditions. The model is valid in all regions of operation, i.e., the subthreshold, linear, and saturation regimes, in good agreement with numerical simulations. On the other hand, the structural optimization is required to lessen the threshold voltage shift of the J DGFET. It is expected that the model may provide some insight into the design and application of the J DGFET, a promising candidate for future technology nodes. Fig. 11. Threshold voltage shifts obtained from lines) the proposed model as a function of the relative changes of a) impurity concentration, b) silicon thickness, and c) oxide thickness, compared with symbols) numerical simulation results. oxide or silicon layer, as well as higher impurity concentration. According to 13), the threshold voltage shifts can be given by ΔV TH,ND = qn ) Dt Si ΔND C eff N D ΔV TH,tSi ΔV TH,tox = qn Dt Si = qn Dt Si C ox 1 4C Si Δtox t ox ΔtSi ) t Si ) ] + 1 Δt Si C ox t Si 7) where ΔV TH,ND, ΔV TH,tSi, and ΔV TH,tox are threshold voltage shifts caused by relative changes of impurity concentration, silicon thickness, and oxide thickness, respectively. The obtained results are shown in Fig. 11. We found that a variation of 1% of N D,t Si, and t ox would lead to threshold voltage shift of mv in the worst case when all of the aforementioned parameters deviate in the same direction. It may pose a grave threat to the yield of large SRAM arrays with minimum-width devices in the cell ]. Hence, the use of thinner J DGFET, dictated by the need for a high doping density, would make the REFERENCES 1] C.-W. ee, A. Afzalian, N. D. Akhavan, R. Yan, I. Ferain, and J. P. Colinge, Junctionless multigate field-effect transistor, Appl. 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398 IEEE TRANSACTIONS ON EECTRON DEVICES, VO. 59, NO. 1, DECEMBER 1 15] R. M. Corless, G. H. Gonnet, D. E. G. Hare, D. J. Jeffrey, and D. E. Knuth, On the ambert W function, Adv. Comput. Math., vol. 5, pp. 39 359, 1996. 16] T. C. Banwell, Bipolar transistor circuit analysis using the ambert W-function, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.47, no. 11, pp. 161 1633, Nov.. 17] E. Gnani, A. Gnudi, S. Reggiani, and G. Baccaranicd, Theory of the junctionless nanowire FET, IEEE Trans. Electron Devices,vol.58,no.9, pp. 93 91, Sep. 11. 18] Sentaurus Device Users Manual, Synopsys, Mountain View, CA, 8, Release a-8-9 Ed. 19] S.-J. Choi, D.-I. Moon, S. Kim, J. P. Duarte, and Y.-K. Choi, Sensitivity of threshold voltage to nanowire width variation in junctionless transistors, IEEE Electron Device ett., vol. 3, no., pp. 15 17, Feb. 11. ] Y. Taur, H.-P. Chen, W. Wang, S.-H. o, and C. Wann, On off charge voltage characteristics and dopant number fluctuation effects in junctionless double-gate MOSFETs, IEEE Electron Device ett.,vol.59, no. 3, pp. 863 866, Feb. 1. Minghua Tang received the B.S. degree and the Ph.D. degree from Xiangtan University, Xiangtan, China, in 1988 and 7, respectively. His research interest is focusing on the fabrication and the characteristics of ferroelectric memory. He is with the Key aboratory of ow Dimensional Materials and Application Technology, Ministry of Education, Xiangtan University. Ying Xiong received the B.S. degree in mathematics from Xiangtan University, Xiangtan, China, in 1987. Her research interest is numerical simulation on functional materials and advanced MOSFETs. Jianqiang Huang received the B.S. degree in microelectronics from Xiangtan University, Xiangtan, China, in 1. He is currently focusing on electrical characteristics of advanced MOSFETs. Jiancheng i received the M.S. and Ph.D. degrees from National University of Defense Technology, Changsha, China, in 3 and 1, respectively. He is working on integrated circuit design. Zhuojun Chen received the B.S. degree in microelectronics in 1 from Xiangtan University, China. He is now focusing on SOI device and circuit design. Xiaochen Gu received the M.S. degree and Ph.D. degree in electronic science and technology from National University of Defense Technology, Changsha, China, in 6 and 1 respectively. He is currently focusing on integrated circuit design. Yongguang Xiao received the B.S. degree in microelectronics from Xiangtan University, Xiangtan, China, in 8, where he is currently working toward the Ph.D. degree in microelectronics and solid-state electronics. Yichun Zhou received the M.S. degree from the National University of Defense Technology, Changsha, China, in 1988 and the Ph.D. degree from the Chinese Academy of Sciences, Beijing, China. His research interests include ferroelectric memory devices, etc.