Semiconductor Memories

!"#"$%&'()$*#+%$*,' -"+./"$0 1'!*0"#)'2*+03*.$"4* Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic Semiconductor Memories December 20, 2002

!"#$%&'()*&'*+&, Memory Classification Memory Architectures The Memory Core Periphery Reliability Case Studies

!"#$%&'()%*&+,-"#&+.,/0122$3$%1*$&' Read-W rite M emory Non-Volatile Read-W rite Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM Mask-Programmed Programmable (PROM) SRAM FIFO FLASH DRAM LIFO Shift Register CAM

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!"#$%&'(%)*+,"),-%".'/")$0"%1 M bits M bits S 0 S 1 S 2 Word 0 Word 1 Word 2 Storage cell A 0 A 1 S 0 Word 0 Word 1 Word 2 Storage cell words N S N 2 2 WordN2 2 A K 2 1 Decoder WordN2 2 S N 2 1 WordN2 1 K 5 log 2 N WordN2 1 Input-Output (M bits) Input-Output (M bits) Intuitive architecture for N x M memory Too many select signals: N words == N select signals Decoder reduces the number of select signals K = log 2 N

!""#$%&'"()'("*+,-*./"$,!")01'*)'("* Problem: ASPECT RATIO or HEIGHT >> WIDTH Amplify swing to rail-to-rail amplitude Selects appropriate word

!"#$%$&'"&%()*#+,$-).$&'"/#&/0$# Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings

!"#$%&'()#)*+,'-..%$/01"2 DRAM Timing Multiplexed Adressing SRAM Timing Self-timed

!"#$%&'()*+",-.)*/"((0 BL BL BL 1 WL WL V DD WL BL BL BL 0 WL WL WL GND Diode ROM MOS ROM 1 MOS ROM 2

!"#$%"&$&"! V DD Pull-up devices WL[0] GND WL [1] WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3]

!"#$%"&$&"!$'()*+, Cell (9.5 x 7 ) Programmming using the Active Layer Only Polysilicon Metal1 Diffusion Metal1 on Diffusion

!"#$%&%'$("! V DD Pull-up devices BL[0] BL[1] BL[2] BL[3] WL[0] WL[1] WL[2] WL[3] All word lines high by default with exception of selected row

!"#$%&%'$("!$)*+,-. Cell (8 x 7 ) Programmming using the Metal-1 Layer Only No contact to VDD or GND necessary; drastically reduced cell size Loss in performance compared to NOR ROM Polysilicon Diffusion Metal1 on Diffusion

!"!#$%&'$()*+,- Cell (5 x 6 ) Programmming using Implants O nly Polysilicon Threshold-altering implant Metal1 on Diffusion

!"#$"%&'()*+,$-*.'("*!"/%0 WL Driver Polysilicon word line Metal word line (a) Driving the word line from both sides Metal bypass WL K cells (b) Using a metal bypass Polysilicon word line (c) Use silicides

!"#$%&"'#()*+,)-+.).+* f pre V DD Precharge devices WL [0] WL [1] GND WL [2] GND WL [3] BL [0] BL [1] BL [2] BL [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design.

!"#$%"&'()&*+,*-".)*/ 01*+2&"'()#3$3'(*+(.'#/)/(".+425,678 Source Floating gate Gate Drain D t ox G n + Substrate p t ox n +_ S Device cross-section Schematic symbol

!"#$%&'()*$%+,-.$'/&/%#.,0.#(.$11&'( 20 V 0 V 5 V 10 V 5 V 20 V 2 5 V 0 V 2 2.5 V 5 V S D S D S D Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T.

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!"#$#%&''()#* Floating gate Source Gate Drain I 20 30 nm n 1 Substrate p n 1 10 nm -10 V 10 V V GD FLOTOX transistor Fowler-Nordheim I-V characteristic

!!"#$%&'()) BL WL V DD Absolute threshold control is hard Unprogrammed transistor might be depletion 2 transistor cell

!"#$%&''()*+ Control gate Floating gate erasure n 1 source programming p- substrate Thin tunneling oxide n 1 drain

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!"!#$%&'()$*+,-./ Word line(poly) Unit Cell Gate ONO Gate Oxide FG Source line (Diff. Layer) Courtesy Toshiba

!"!#$%&'()$*+,-./ Select transistor Word lines Active area ST I Bit line contact Source line contact Courtesy Toshiba

!"#$#%&'$()&(%)*+,*-&#&'.+,.&"'.#$&*/01

!"#$%&'()"*+",-'(".*/!0+1 STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended

!"#$%&'('#)$*+,-.*./0,*+122* WL V DD M 2 M 4 Q M Q M 5 6 M 1 M 3 BL BL

!"#$%&'( )*+,-.( V DD M2 M4 Q Q M1 M3 M5 M6 GND WL BL BL

!"#$#%&'(")*+&,-.!/0-1"** V DD WL R L R L M 3 Q Q M 4 BL M 1 M 2 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem

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!"#$%&'(')*$+,-./+0122 Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance V = VBL V PRE = V BIT V PRE C S C S ------------ + C BL Voltage swing is small; typically around 250 mv.

!"#$%&'((%)*+',-./012+ 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. 1 is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than V DD

!"#$"%&'(%)("*+,-.# V BL V(1) V PRE DV(1) Sense amp activated Word line activated V(0) t

!"#$%&'($)*++ Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Layout Polysilicon plate M 1 word line Uses Polysilicon-Diffusion Capacitance Expensive in Area

!"#$%&"#' Decoders Sense Amplifiers Input/Output Buffers Control / Timing Circuitry

!"#$%&'"(&)* Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder

!"#$%$&'"&%()*#&+,#$- Multi-stage implementation improves performance WL 1 WL 0 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 NAND decoder using 2-input pre-decoders

!"#$%&'(!)'*+),- Precharge devices GND GND V DD WL 3 V DD WL 3 WL 2 V DD WL 2 WL 1 WL 0 V DD WL 1 WL 0 V DD A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 2-input NOR decoder 2-input NAND decoder

!"#$%&'(%)**"'+)$*#*',+(-)*./(0,1&2$( /.0,/.+ BL 0 BL 1 BL 2 BL 3 A 0 S 0 S 1 S 2 A 1 S 3 2-input NOR decoder Advantages: speed (t pd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count D