MOS Capacitors Prof. Ali M. Niknejad Prof. Rikky Muller

Similar documents
Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) Prof. Ali M. Niknejad Prof. Rikky Muller

Lecture 11: MOS Transistor

Lecture 12: MOS Capacitors, transistors. Context

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2005 Microelectronic Devices and Circuits

EE 560 MOS TRANSISTOR THEORY

Department of Electrical and Computer Engineering, Cornell University. ECE 3150: Microelectronics. Spring Due on March 01, 2018 at 7:00 PM

FIELD-EFFECT TRANSISTORS

EE105 - Spring 2007 Microelectronic Devices and Circuits. Structure and Symbol of MOSFET. MOS Capacitor. Metal-Oxide-Semiconductor (MOS) Capacitor

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)

Announcements. EE105 - Fall 2005 Microelectronic Devices and Circuits. Lecture Material. MOS CV Curve. MOSFET Cross Section

Lecture 6 PN Junction and MOS Electrostatics(III) Metal-Oxide-Semiconductor Structure

Interim Exam 1 5AIB0 Sensing, Computing, Actuating , Location AUD 11

Gauss Law. 2. Gauss s Law: connects charge and field 3. Applications of Gauss s Law

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

Parallel plate capacitor. Last time. Parallel plate capacitor. What is the potential difference? What is the capacitance? Quick Quiz "V = 1 C Q

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lecture 15: MOS Transistor models: Body effects, SPICE models. Context. In the last lecture, we discussed the modes of operation of a MOS FET:

University of Pennsylvania Department of Electrical Engineering. ESE 570 Midterm Exam March 14, 2013 FORMULAS AND DATA

ECE321 Electronics I

Demonstration of Ohm s Law Electromotive force (EMF), internal resistance and potential difference Power and Energy Applications of Ohm s Law

Induction and Inductance

Lecture 15 OUTLINE. MOSFET structure & operation (qualitative) Review of electrostatics The (N)MOS capacitor

EECS130 Integrated Circuit Devices

Electrical Characteristics of MOS Devices

EEC 118 Lecture #2: MOSFET Structure and Basic Operation. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

Chapter 26 - Capacitance

EECS130 Integrated Circuit Devices

Preamble. Flow and Fluid Velocity. In this section of my lectures we will be. To do this we will use as an analogy

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

MOSFET: Introduction

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

(Refer Slide Time: 2:34) L C V

Section 12: Intro to Devices

RELUCTANCE The resistance of a material to the flow of charge (current) is determined for electric circuits by the equation

! MOS Capacitances. " Extrinsic. " Intrinsic. ! Lumped Capacitance Model. ! First Order Capacitor Summary. ! Capacitance Implications

EECS130 Integrated Circuit Devices

Lecture 23: Negative Resistance Osc, Differential Osc, and VCOs

CHAPTER 5 MOS FIELD-EFFECT TRANSISTORS

ECE 305 Exam 5 SOLUTIONS: Spring 2015 April 17, 2015 Mark Lundstrom Purdue University

Lecture 7 - PN Junction and MOS Electrostatics (IV) Electrostatics of Metal-Oxide-Semiconductor Structure. September 29, 2005

Chapter 2 MOS Transistor theory

MOS Transistor Theory

Semiconductor Integrated Process Design (MS 635)

ESE 570 MOS TRANSISTOR THEORY Part 1. Kenneth R. Laker, University of Pennsylvania, updated 5Feb15

ECEN474/704: (Analog) VLSI Circuit Design Spring 2018

ECE 340 Lecture 39 : MOS Capacitor II

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.

MOS Transistor Properties Review

ELEC 3908, Physical Electronics, Lecture 23. The MOSFET Square Law Model

Chapter 2 CMOS Transistor Theory. Jin-Fu Li Department of Electrical Engineering National Central University Jungli, Taiwan

Lecture 04 Review of MOSFET

Sure Shot 2016 Electric Current By M K Ezaz

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

The Three terminal MOS structure. Semiconductor Devices: Operation and Modeling 115

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Section 12: Intro to Devices

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

Dept. of Materials Science and Engineering. Electrical Properties Of Materials

Related Topics Maxwell s equations, electrical eddy field, magnetic field of coils, coil, magnetic flux, induced voltage

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

MOS Transistor I-V Characteristics and Parasitics

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

EE115C Winter 2017 Digital Electronic Circuits. Lecture 3: MOS RC Model, CMOS Manufacturing

Homework Assignment No. 1 - Solutions

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.

Classification of Solids

Check course home page periodically for announcements. Homework 2 is due TODAY by 5pm In 240 Cory

ECE-305: Fall 2017 Metal Oxide Semiconductor Devices

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Lecture 3: CMOS Transistor Theory

Introduction to CMOS VLSI. Chapter 2: CMOS Transistor Theory. Harris, 2004 Updated by Li Chen, Outline

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

The Devices: MOS Transistors

Extensive reading materials on reserve, including

6.012 Electronic Devices and Circuits Spring 2005

Midterm I - Solutions

VLSI Design The MOS Transistor

ECS 40, Fall 2008 Prof. Chang-Hasnain Test #3 Version A

an introduction to Semiconductor Devices

Microelectronics Part 1: Main CMOS circuits design rules

Lecture 4: CMOS Transistor Theory

6.012 Electronic Devices and Circuits

Lecture 22 - The Si surface and the Metal-Oxide-Semiconductor Structure (cont.) April 2, 2007

Lecture 7 MOS Capacitor

PN Junction and MOS structure

UNIVERSITY OF CALIFORNIA, BERKELEY College of Engineering Department of Electrical Engineering and Computer Sciences

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

MOS CAPACITOR AND MOSFET

Lecture 6 - PN Junction and MOS Electrostatics (III) Electrostatics of pn Junction under Bias February 27, 2001

ECE-305: Fall 2017 MOS Capacitors and Transistors

CMOS Devices. PN junctions and diodes NMOS and PMOS transistors Resistors Capacitors Inductors Bipolar transistors

Week 3, Lectures 6-8, Jan 29 Feb 2, 2001

EEC 116 Lecture #3: CMOS Inverters MOS Scaling. Rajeevan Amirtharajah University of California, Davis Jeff Parkhurst Intel Corporation

The Gradual Channel Approximation for the MOSFET:

and V DS V GS V T (the saturation region) I DS = k 2 (V GS V T )2 (1+ V DS )

Microelectronic Devices and Circuits Lecture 9 - MOS Capacitors I - Outline Announcements Problem set 5 -

Transcription:

EECS 105 Spring 2017, Modue 3 MOS Capacitors Prof. Ai M. Niknejad Prof. Rikky Muer Department of EECS University of Caifornia, Berkeey

Announcements Prof. Rikky Muer Wecome to the second haf of EE105! Professor Muer wi be ecturing Midterm 1 handed back today Mean = Median = Standard Dev = Midterm 2 on Thursday, March 23 in ecture Attend discussion sessions! They are hepfu for homework, exam reviews and topics not covered in ecture. 2 University of Caifornia, Berkeey

MOS Capacitor Prof. Rikky Muer Gate (n + poy) Body (p-type substrate) εs = 11.7ε 0 0 x Oxide (SiO 2 ) ε = 3.9ε 0 ery Thin! t ~1nm 3 MOS = Meta Oxide Semiconductor Sandwich of conductors separated by an insuator Meta is more commony a heaviy doped poysiicon (poy-si) ayer n + or p + ayer Was meta (e.g. A) unti ~1970 but changed to poy-si due to high temperature processing. After 2008, meta gates have been reintroduced! Learn more about MOS process technoogy in EE130 & EE143 NMOS à p-type substrate, PMOS à n-type substrate University of Caifornia, Berkeey

Meta-Oxide-Semi Junction Prof. Rikky Muer Gate (n + poy) Body (p-type substrate) 4 Under therma equiibrium, the n-type poy gate is at a higher potentia than the p-type substrate φ p = kt q n N a φ n poy,n + = kt i q n N d,poy n 550m i No current can fow because of the insuator but this potentia difference is accompanied with an eectric fied Fieds terminate on charge! University of Caifornia, Berkeey

Fieds and Charge at Equiibrium Prof. Rikky Muer + + B ++++++++++++++++++ X d 0 Body (p-type substrate) E 5 At equiibrium there is an eectric fied from the gate to the body Need a positive charge on the gate, negative charge in substrate Since body is p-type, negative charges in the body come from a depetion region University of Caifornia, Berkeey

Prof. Rikky Muer Fat Band otage, GB = FB FB < 0 + Q ( = ) = 0 G GB FB Body (p-type substrate) 6 If we appy a bias, we can compensate for this buit-in potentia = ( φ φ ) FB In this case the charge on the gate goes to zero and the depetion region disappears In soid-state physics ingo, the energy bands are fat under this condition n + p University of Caifornia, Berkeey

Prof. Rikky Muer Fat Band otage, GB = FB 7 University of Caifornia, Berkeey

Prof. Rikky Muer Accumuation, GB < FB Q = C ( ) G GB FB GB < FB + - ++++++++++++++++++ Q B = Q G Body (p-type substrate) If we further decrease the potentia beyond the fat-band condition, we essentiay have a parae pate capacitor Penty of hoes and eectrons are avaiabe to charge up the pates Negative bias attracts hoes under gate 8 University of Caifornia, Berkeey

Prof. Rikky Muer Accumuation, GB < FB 9 University of Caifornia, Berkeey

Prof. Rikky Muer Depetion, GB > FB GB > + + + + + + + + + + + FB Body (p-type substrate) Q ( ) = Q G GB B Q = qn X ( ) B a d GB Simiar to equiibrium, the potentia in the gate is higher than the body Body charge is made up of the depetion region ions Potentia drop across the body and depetion region 10 University of Caifornia, Berkeey

Prof. Rikky Muer Depetion, GB > FB 11 University of Caifornia, Berkeey

Prof. Rikky Muer Inversion, GB > T GB = T + + + + + + + + + + + φ s Body (p-type substrate) 12 As we further increase the gate votage, eventuay the surface potentia increases to a point where the eectron density at the surface equas the background ion density qφs kt s i a n = ne = N φs = φp At this point, the depetion region stops growing and the extra charge is provided by the inversion charge at surface Inversion meaning that the surface is effectivey n-type University of Caifornia, Berkeey

Prof. Rikky Muer Inversion, GB > T 13 University of Caifornia, Berkeey

Threshod otage Prof. Rikky Muer The threshod votage is defined as the gate-body votage that causes the surface to change from p- type to n-type For this condition, the surface potentia has to equa the negative of the p-type potentia We can derive that this votage is equa to: 1 Tn = FB 2φp + 2 qεs Na( 2 φp) C 14 University of Caifornia, Berkeey

Prof. Rikky Muer Recap Accumuation: GB < FB Q = C ( ) G GB FB GB < FB + Q B = Q G ++++++++++++++++++ Body (p-type substrate) Essentiay a parae pate capacitor Capacitance is determined by ide thickness 15 University of Caifornia, Berkeey

Prof. Rikky Muer Recap Depetion: FB < GB < T GB > + FB + + + + + + + + + + Q ( ) = Q G GB B Body (p-type substrate) Q = qn X ( ) B a d GB Positive charge on gate terminates on negative charges in depetion region Potentia drop across the ide and depetion region Charge has a square-root dependence on appied bias 16 University of Caifornia, Berkeey

Prof. Rikky Muer Recap Inversion: GB > T φ s GB = T + + + + + + + + + + + Body (p-type substrate) qφs kt s = i = a n ne N 17 The surface potentia increases to a point where the eectron density at the surface equas the background ion density At this point, the depetion region stops growing and the extra charge is provided by the inversion charge (eectrons) at the surface University of Caifornia, Berkeey

Q- Curve for MOS Capacitor Prof. Rikky Muer Q G depetion Q B,max Q ( ) N GB FB Tn ( ) GB In accumuation, the charge is simpy proportiona to the appies gate-body bias In inversion, the same is true In depetion, the charge grows sower since the votage is appied over a depetion region 18 University of Caifornia, Berkeey

MOS C Curve Prof. Rikky Muer Q G C C C Q ( ) N GB Q B,max ( ) GB GB FB Tn FB Tn Sma-signa capacitance is sope of Q- curve Capacitance is constant in accumuation and inversion Capacitance in the depetion region is smaest Capacitance is non-inear in depetion 19 University of Caifornia, Berkeey

C- Curve Equivaent Circuits Prof. Rikky Muer Accumuation Depetion Inversion C C C dep C 20 ε s CdepC C Cdep = C Ctot = = = xdep Cdep + C Cdep ε s t 1+ 1+ C ε x dep In accumuation mode the capacitance is just due to the votage drop across t In depetion region, the votage drop is across the ide and the depetion region In inversion the incrementa charge comes from the inversion ayer (depetion region stops growing). University of Caifornia, Berkeey

Numerica Exampe Prof. Rikky Muer MOS Capacitor with p-type substrate: 16 3 t = 20nm = 5 10 cm Cacuate fat-band: N a = ( φ φ ) = (550 ( 402)) = 0.95 FB n + Cacuate threshod votage: p 13 ε 3.45 10 F/cm C = = -6 t 2 10 cm 1 Tn = FB 2φp + 2 qεs Na( 2 φp) C Tn 19 12 16 2 1.6 10 1.04 10 5 10 2 0.4 =.95 2( 0.4) + = 0.52 C 21 University of Caifornia, Berkeey

Num Exampe: Eectric Fied in Oxide Prof. Rikky Muer Appy a gate-to-body votage: GB = 2.5 < FB Device is in accumuation The entire votage drop is across the ide: E GB + φ + φ n p 2.5 + 0.55 ( 0.4) = = = = 8 10 t t 5 6 2 10 cm The charge in the substrate (body) consist of hoes: 22 Q = C ( ) = 2.67 10 C/cm B GB FB 7 2 University of Caifornia, Berkeey