ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff " Depletion " Inversion " Threshold Voltage Penn ESE 570 Spring 018 Khanna CMOS Layers! Standard nwell Process " Active (Diffusion) (Drain/Source regions) " Polysilicon (Gate Terminals) " Metal 1, Metal, Metal3 " Poly Contact (connects metal 1 to polysilicon) " Active Contact (connects metal 1 to active) " Via (connects metal to metal 1) " nwell (PMOS bulk region) " n Select (used with active to create ntype diffusion) " p Select (used with active to create ptype diffusion) CMOS Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs 3 4 CMOS Process Enhancements HighK dielectric! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! Devices " Multiple thresholds (High and low V t ) " Highk gate dielectrics " FinFET SiO Dielectric Poly gate MOSFET Dielectric constant3.9 HighK Dielectric Metal gate MOSFET Dielectric constant0 5 6 1
HighK dielectric Survey nm 3D FinFET Transistor Wong/IBM J. of R&D, V46N/3P133 168, 00 7 Highk gate dielectric TriGate transistors with multiple fins connected together increases total drive strength for higher performance http://download.intel.com/newsroom/kits/nm/pdfs/nmdetails_presentation.pdf 8 CMOS Process Enhancements! Interconnect " Metal Interconnect (up to 8 metal levels) " Copper Interconnect (upper two or more levels) " Polysilicon (two or more levels, also for high quality capacitors) " Stacked contacts and vias! Circuit Elements " Resistors " Capacitors " BJTs! Devices " Multiple thresholds (High and low V t ) " Highk gate dielectrics " FinFET! Silicon on insulator process (SOI) " Fabricate on insulator for high speed/low leakage Semiconductor Physics 9 10 Silicon Lattice! Cartoon twodimensional view Energy State View Energy Valance Band all states filled 11 1
Energy State View Energy State View Conduction Band all states empty Conduction Band all states empty Energy Energy Band Gap Valance Band all states filled Valance Band all states filled 13 14 Band Gap and Conduction Doping Insulator 8ev E c Metal OR E c E v! Add impurities to Silicon Lattice " Replace a Si atom at a lattice site with another! E.g. add a Group 15 element " E.g. P (Phosphorus) E v E v E c Semiconductor 1.1ev E c E v 15 16 Doping with P Doped Band Gaps! End up with extra electrons " Donor electrons! Not tightly bound to atom " Low energy to displace " Easy for these electrons to move! Addition of donor electrons makes more metallic " Easier to conduct Semiconductor 0.045ev 1.1ev E c E D E v 17 18 3
Doping with B! End up with electron vacancies Holes " Acceptor electron sites! Easy for electrons to shift into these sites " Low energy to displace " Easy for the electrons to move " Movement of an electron best viewed as movement of hole Doped Band Gaps! Addition of acceptor sites makes more metallic " Easier to conduct Semiconductor E c 0.045ev 1.1ev E A E v 19 0 MOSFETs MOSFET! Donor doping " Excess electrons " Negative or Ntype material " NFET! Acceptor doping " Excess holes " Positive or Ptype material " PFET! Semiconductor can act like metal or insulator " Depends on doping! Use field to modulate conduction state of semiconductor + + + + + 1 MOS Capacitor Charge MOS Field?! MOS gatetosubstrate capacitor " Charge across MOS cap induce efield! What does capacitor field do to the Donordoped semiconductor channel? + + + + + + + + gate drain source semiconductor No field 3 4 4
MOS Field?! What does capacitor field do to the Donordoped semiconductor channel? MOS Field?! What does capacitor field do to the Donordoped semiconductor channel? No field + + + + V cap >0 No field + + + + V cap >0 + + + + + V gs >0 5 6 MOS Field Effect Field Effect?! Charge on capacitor " Attract or repel charges to form channel " Modulates conduction " Positive " Attracts carriers " Negative? + + + + + " Repel carriers! Effect of positive field on Acceptordoped Silicon? No field + + + + 7 8 Field Effect? Field Effect?! Effect of positive field on Acceptordoped Silicon?! Effect of positive field on Acceptordoped Silicon? No field + + + + + + + + V cap >0 No field + + + + + + + + V cap >0 + + + + + V gs >0 No conduction 9 30 5
Field Effect?! Effect of negative field on Acceptordoped Silicon? Field Effect?! Effect of negative field on Acceptordoped Silicon? No field + + + + + + + + V cap <0 No field + + + + + + + + V cap <0 + + + + + V gs >0 31 3 TwoTerminal MOS Structure MOS Physics nmos GATE MOS capacitor Si Oxide interface n+ n+ 34 TwoTerminal MOS Structure TwoTerminal MOS Structure GATE GATE Si Oxide interface Si Oxide interface n+ n+ n+ n+! Equilibrium (Mass action law) " Product of hole and electron densities is constant at equilibrium " n 0 p 0 n i n i 1.45x10 10 cm 3 35! n 0 p 0 n i n i 1.45x10 10 cm 3! Let substrate be uniformly doped with concentration 36 6
TwoTerminal MOS Structure TwoTerminal MOS Structure GATE GATE Si Oxide interface Si Oxide interface n+ n+ n+ n+! n 0 p 0 n i n i 1.45x10 10 cm 3! Let substrate be uniformly doped with concentration " p p0 # n p0 n i / 37! n 0 p 0 n i n i 1.45x10 10 cm 3! Let substrate be uniformly doped with concentration " p p0 # n p0 n i / If Ntype doped substrate: n n0 N D # p n0 n i /N D 38 Ptype Doped Semiconductor Band Gap Ptype Doped Semiconductor Band Gap Free space Electron affinity of silicon Free space Conduction band Intrinsic Fermi level E i E C E V Conduction band Intrinsic Fermi level Fermi level Valence band! qφ and E are in units of energy electronvolts (ev); where 1 ev 1.6 x 10 19 J.! 1 ev corresponds to energy acquired by a free electron that is accelerated by an electric potential of one volt. Fermi level Valence band! Φ and V corresponds to potential difference in volts. 39 40 Ptype Doped Semiconductor Band Gap MOS Capacitor Energy Bands Free space Conduction band E i E C E V Intrinsic Fermi level Fermi level Valence band Fermi potential: E E F i Φ q Fp kt q ln n i 41 4 7
MOS System Band Diagram! Three components put in physical contact " Fermi levels must line up MOS Capacitor with External Bias! Three Regions of Operation (w/ V B 0): " Accumulation Region V G < 0 " Depletion Region V G > 0, small " Inversion Region V G, large 43 44 Accumulation Region Accumulation Region Energy Bands! Holes " Accumulate at the siliconoxide interface! Electrons " Near surface repelled into silicon bulk Accumulation V G < 0 E Fm qv G E Fp E Fm qφ S Si surface Band bending due to V G < 0 qφ(x) q E Fp! Interface accumulated with mobile carriers (holes) 0 x 45 46 Depletion Region Depletion Region Energy Bands! Holes " Near siliconoxide interface repelled into silicon bulk! Electrons " Left behind at interface Depletion V G > 0 (small) qv G E Fp E Fm E Fm qφ S Si surface Band bending due to V G > 0 qφ(x) q E Fp! Interface depleted of mobile carriers (holes) 0 x d x 47 48 8
Depletion Region Depletion Region Φ F kt q ln n i < 0 6 mv at room T Φ F kt q ln n i < 0 6 mv at room T Φ Φ S Surface potential Bulk potential Φ Φ S Surface potential Bulk potential dq q dx dφ x dq Mobile hole charge density (per unit area) in thin layer below surface Potential required to displace dq by distance x 49 50 Depletion Region Depletion Region Φ F kt q ln n i < 0 6 mv at room T Φ F kt q ln n i < 0 6 mv at room T Φ Φ S Surface potential Bulk potential Φ Φ S Surface potential Bulk potential dφ q x dx dq q dx dφ x dq Mobile hole charge density (per unit area) in thin layer below surface Potential required to displace dq by distance x dφ q x dx 51 dφ Φ S x d x d 0 q x q dx q N x A d 5 Depletion Region Depletion Region Φ F kt q ln n i < 0 6 mv at room T Φ F kt q ln n i < 0 6 mv at room T Φ Φ S Surface potential Bulk potential Φ Φ S Surface potential Bulk potential dφ q x dx x d q dφ Φ S x d 0 q x dx q N x A d Q q x d x d q Q q q q 53 54 9
Inversion Region Inversion Region Energy Bands! Holes " Repelled deeper into silicon bulk! Electrons " Attracted to siliconoxide interface V G Inversion V G 0 > 0 qv G E Fp E Fm qφ S Si surface q E Fp! Inversion condition " When Φ S Φ F " Density of mobile electrons at surface density of mobile carriers in bulk E Fm 0 x dm x 55 56 Inversion Region Band Diagram Demo! Inversion condition " When Φ S Φ F " Density of mobile electrons at surface density of mobile carriers in bulk V G x dm q q Q q q 57 http://demonstrations.wolfram.com/appliedvoltageonanidealmoscapacitor/ 58 MOS Capacitor with External Bias! Three Regions of Operation: " Accumulation Region V G < 0 (Cutoff) " Depletion Region V G > 0, small (Subthreshold) " Inversion Region V G, large (Above Threshold) terminal MOS Cap # 3terminal nmos V G VS V G V D depletion region Cutoff/Subthreshold Above threshold Penn ESE 570 Spring 017 Khanna 59 60 10
nmos MOS cap + source/drain Threshold Voltage! For V SB 0, the threshold voltage is denoted as 0 or 0n,p V SB 0 V S V G V D 0 Φ F Q B0 " Φ GC : Work function difference between gate and channel " Metal Gate: Φ GC Φ F (substrate) Φ M " Poly Gate: Φ GC Φ F (substrate) Φ F (gate) " Q OX : Fixed positive charge density at interface " Q OX qn OX C/cm " C OX : Gate oxide capacitance per unit area " C OX ε OX / " Φ GC : Bulk fermi potential " Q B0 : Depletion region charge density at inversion " Q B0 q Φ F 61 6 Threshold Voltage Threshold Voltage! For V SB 0, the threshold voltage is denoted as 0 or 0n,p " Φ GC : Work function difference between gate and channel " Metal Gate: Φ GC Φ F (substrate) Φ M " Poly Gate: Φ GC Φ F (substrate) Φ F (gate) " Q OX : Fixed positive charge density at interface " Q OX qn OX C/cm " C OX : Gate oxide capacitance per unit area " C OX ε OX / " Φ GC : Bulk fermi potential 0 Φ F Q B0 " Q B0 : Depletion region charge density at inversion for V SB 0 for V SB! 0 0 Φ F Q B0 Φ F Q B Φ F Q B0 Q B Q B0 0 Q B Q B0 " Q B0 q Φ F 63 64 Threshold Voltage Threshold Voltage for V SB 0 0 Φ F Q B0! Be careful with signs! for V SB! 0 γ Φ F Q B Φ F Q B0 Q B Q B0 0 Q B Q B0 ( ) Q Q B B0 q Φ F V SB Φ F 0 +γ ( Φ F V SB Φ F ) Q q Φ F 65 Nchannel Pchannel ϕ F negative positive Q B0,Q B negative positive ϒ positive negative V SB 0 0 0 positive (0n ) negative (0p ) 66 11
Threshold Voltage Big Idea! 3 operation regions " Cutoff " Depletion " Inversion! Threshold voltage " Defined by onset of inversion " Doping and V SB change V SB 67 68 Admin! HW due Thursday, 1/5 " Submit in canvas 69 1