Heat Removal of a Protection Chip after Surge Pulse Tom Graf Hochschule Luzern T&A Technikumstrasse 21 CH-6048 Horw Switzerland

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Heat Removal of a Protection Chip after Surge Pulse Tom Graf Hochschule Luzern T&A Technikumstrasse 21 CH-6048 Horw Switzerland 1 / 23

Abstract EMC protection elements experienced significant heating after surge impulses (253 W). The thermal behavior of the protection elements was modeled with the method of finite elements (FEM). COMSOL Multiphysics Heat Transfer Module T Equation solved: cp k T Q t The FEM results led to a compact model to allow for design and simulation with simpler tools. The company HMT used our results for a new series of protection elements. Sensor circuit and protection elements are now integrated in a single ASIC design. 2 / 23

Test Chip 30 FEM model and ASIC design of a test chip of Zener protection elements. Heat is dissipated in the "Zener-A-bands". FEM 3 / 23

Surge Pulse 300 250 253 W power (W) 200 150 100 50 Spice simulation of surge pulse ISO 7637-2 (Automotive: 24 V, 240 mj) 0 10 s 100 s 1 ms 10 ms time 0.00001 0.0001 0.001 0.01 time (s) ISO 7637-2 dissipates most heat of all studied standards 4 / 23

Model Data 5 / 23

Surface Temperature T ( C) Si Cu P in = 253W no scribe line no bond wires air and radiation included bond pads included air loss: P h A T T air surf amb P air 0.03 W T ground = 20 C P in = 253W, stationary 1115 C epoxy Extremely large steady state temperatures are reached! 6 / 23

Radiation W/m 2 radiation loss: P A T T 4 4 rad B surf amb radiative area: A = 5.47 10 6 m 2 P rad 0.13 W P in = 253W, stationary Minor heat removal via air and radiation 7 / 23

Heat Channels stationary T max is governed by contact to base 8 / 23

Epoxy Resistance stationary Decrease of contact resistance by a factor 10 reduces T max considerably! 9 / 23

Ab Initio 1D-Model FEM 10 / 23

Test Chip 30 20 chip dimensions in m 940 660 oxide boxes Zener structure, "oval" ABC 3640 A,B,C Zener bands 150 protection element A B C GDS 20 212 FEM 11 / 23

p-n Heat heat 12 / 23

Details of TC30 Zener structure, "oval" 13 / 23

Layer Data >95% sheet resistance of Al: ρ/d = 2.8 10 8 /1 10 6 = 30 mω/ thermal conductivity of titanium 22W/(m K); layer sheet resistance Ω/ is that of not pure Al 14 / 23

Layer Structure 15 / 23

Detailed Model detailed structure at chip corner,... including three metal layers BC: T ground = 20 C coarse test chip model 16 / 23

Heat Input 60 m PT2 PT2 PT1 0.3W 0.03W 50 m PT1 17 / 23

Active Layer Temp. T ( C) Coarse model Detailed model stationary T ( C) Dissipation level 18 / 23

Oxide Barrier stationary T ( C) Oxide layers and trenches form thermal barriers! 19 / 23

Heat Step transient 160 140 120 100 80 PT1 60 40 T/ t 60 C/μs 20 10 μs 12 μs 14 μs 9.0E-06 1.0E-05 1.1E-05 1.2E-05 1.3E-05 1.4E-05 1.5E-05 Very fast initial Temp. increase! 20 / 23

Compact Model t t R1 C1 R2 C2 1 1 TJ t TG T e T e T transient 1 2 3 T1 T2 T3 Rtot R1 R2 R3 P BC: T J (t= ) = 1225 C (FEM) Parameter Value Unit P 253 W T J =T G +T 1 +T 2 +T 3 1225 C T 3 = P R 3 48 K R 3 "oxide trench" 0.19 K / W T 2 = P R 2 199 K 2 = R 2 C 2 1.8 10 5 s C 2 (fit) "active silicon" 2.3 10 5 J / K R 2 (fit) "buried oxide" 0.79 K / W T 1 = P R 1 958 K 1 = R 1 C 1 4.2 10 3 s C 1 (fit) "die + epoxy" 1.1 10 3 J / K R 1 (fit) "die + epoxy" 3.79 K / W 21 / 23

Temperature evolution of the bulk silicon and the junction during a 2.0 A surge impulse-equivalent (triangular shape). Time axis is 50 s / div. transient Validation Note the high junction temperature of 153 C after mere 20 s and the ultra fast measurement! The mechanism of heat flux and temperature evolution of the test chip is essentially understood. Material and geometry data of similar chips allow for prediction of the temperature evolution prior to FEM simulations. 22 / 23

Conclusions The maximum temperature is governed by the die attach. Heat flux through bond-wires or by conduction or radiation to air is negligible. Equation solved: Oxide trenches in the active silicon layer and the buried oxide cause efficient thermal insulation. We were able to measure the initial temperature rise after a heat step emulating surge pulse ISO 7637-2: The junction temperature increases by 60 K / s. A compact model based on exponential fitting reproduces the temperature evolution of the FEM simulation accurately. 23 / 23

Ab Initio Model To emulate the FEM results a Spice model was created. The model consists of the active chip layer (top) and the wafer handle (bottom). Two-layer model: Ab initio R and C P in = 253W top layer b.o. wafer epoxy socket R th (K/W) 0.03 0.11 0.45 2.94 0.15 C th (J/K) 6.1 10 5 0 1.3 10 3 0 2.3 10 3 1 2 1400 1200 T ( C) 1 2 R 1 = 0.14 K/W C 1 = 6.1E-05 J/K τ 1 = 8.2E-06 s T j1 R 2 = 3.51 K/W C 2 = 3.6E-03 J/K τ 2 = 0.013 s T j2 = 922 K P v = 253 W 1000 800 600 400 200 FEM Tj2, ab initio spice model 0 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 921 t (s) 24 / 23

2 au Excel Fit The FEM thermal simulation (blue) can be fitted with two exponential functions (pink). The linear thermal equations should allow to predict the surge pulse behavior prior to FEM simulations. parameters: R 1 = 0.92 K/W R 2 3.85 K/W C 1 = 9.0E-06 J/K C 2 1.1E-03 J/K τ 1 = 8.2E-06 s τ 2 4.1E-03 s T j1 = 231 K T j2 973 K P v = 253 W T A = 293K 20 C Boundary conditions (fixed parameters) were T A = 20 C, T j, t= = 1225 C (FEM) and R tot = R 1 + R 2 = (T j1 + T j2 )/P v. The three fit parameters were R 1, C 1 and C 2. T P R, T P R j1 v 1 j2 v 2 1400 T ( C) Tj 1200 Pv C1 R1 1000 800 C2 R2 TA 600 FEM calculation 400 EXCEL fit, 2 τau 200 0 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 time (s) t t R C R C j j1 j1 j2 j2 A 1 1 2 2 T (t) T T e T T e T 25 / 23

Seal Ring 10μm to Zener 250μm thick Si 20μm 26 / 23

Layer Thickness 10.0μm 9.0μm 7.0μm Metal 3, AlSiCu, 2μm Oxide, 0.9μm Roger Bostock: Al 3 1μm SiO 2 3 0.7μm surface ratio = oxid : via(m3-m2) none 6.1μm Metal 2, AlSiCu, 1μm 5.1μm Oxide, 0.9μm surface ratio = oxid : via(m2-m1) = 4:1 4.2μm Metal 1, AlSiCu, 0.7μm 3.5μm Oxide, 0.77(+0.53)μm surface ratio = oxid : via(m1-p) = 2:1 2.5μm Si, N-Well, 2μm 0.5μm P-N Heat 0 0.5μm 20.0μm Buried Oxide, 0.5μm Si Handle, 250μm, polished 27 / 23

Dimensions x,y = 9.6μm s = 13.6μm Area ratio = oxid : via(m2-m1) = 4:1 Area ratio = oxid : via(m3-m2) = almost inexistent x,y = 3μm s = 4.2μm 4μm 0.8μm Trench, 7 10.9μm Surface area ratio = 5.4μm 0.4μm 0.8μm 9.7μm 20.4μm 53.2μm Cont, 19 130μm 9.6μm 73μm 75μm oxid : via(m1-p) = 2:1 Metall 1, 20 11.9μm 5.8μm 110μm 28 / 23

Layer Model k W/(m K) ρ kg/m 3 C p J/(kg K) 5.7μm Oxide, 1μm 1.38 2203 703 Al + 10% Oxide, 2μm 144 2650 880 Oxide, 0.9μm 1.38 2203 703 3.7μm Al + 10% Oxide, 1μm Oxide + 20% Al, 0.9μm 144 99.5 2650 2410 880 780 33 2300 740 2.7μm Al + 10% Oxide, 0.7μm 144 2650 880 2.0μm 1.5μm Oxide + 30% Al, 1μm P-N Heat 54 2370 770 163 2230 703 Si, N-Well, 2μm 0.5μm 0 20.0μm Buried Oxide, 0.5μm Si Handle, 250μm, polished 29 / 23