Reversible Logic s proved by Landauer, using traditional irreversible gates leads to energy dissipation, Bennett showed that for power not be dissipated in the circuit it is necessary that arbitrary circuit can be build from reversible gates.
Reversible logic Reversible are circuits (gates) that have the same number of inputs and outputs and have one-toone mapping between vectors of inputs and outputs; thus the vector of input states can be always reconstructed from the vector of output states. INPUTS OUTPUTS 000 000 001 001 Feedback 010 not 100 allowed 011 101 100 010 Fan-out not allowed 101 110 110 011 111 111
Quantum versus reversible computing Quantum Computing is a coming revolution after recent demonstrations of quantum computers, there is no doubt about this fact. They are reversible. Top world universities, companies and government institutions are in a race. Reversible computing is the step-by-step way of scaling current computer technologies and is the path to future computing technologies, which all happen to use reversible logic. In addition, Reversible Computing will become mandatory because of the necessity to decrease power consumption
But what can be done by researchers who have no access to well-funded laboratories, expensive equipment, and elite workshops? Portland Quantum Logic Group is an attempt to give an answer to the above question. We are a group of researchers interested in collaboration on reversible logic, quantum logic, reversible and quantum computing and nanotechnologies. We share information about new developments, we collaborate on developing new methodologies, algorithms and circuits. We discuss theoretical problems and realization issues.
Portland Quantum Logic Group members include: M. Perkowski, G. Greenwood,. l-rabadi,.mishchenko, X. Song and M. Chrzanowska- Jeske from Department of Electrical and Computer Engineering, PSU, B. Massey and S. Mocas from Department of Computer Science of PSU, ndrew Fraser from System Science, PSU, Pawel Kerntopf from Department of Computer Science, Technical University of Warsaw, Warsaw, Poland, Svetlana Yanushkevich and Vlad Shmerko from Department of Electronics of Technical University of Szczecin, Poland, ndrzej Buller from Information Science Division, dvanced Telecommunications Research Institute International (TR), Kyoto, Japan, lan Coppola from Cypress Semiconductor Northwest and Oregon Graduate Institute, Md.Mozammel Huq zad Khan from Department of Computer Science and Engineering, East West University, Bangladesh, Bernd Steinbach from Computer Science Department, Technical University of Freiberg, Germany, Lech Jozwiak from Department of Electronics, Technical University of Eindhoven, Eindhoven, The Netherlands. Radomir Stankovic from University of Nis, Yugoslavia.
Our general goals are: 1. to develop efficient logic synthesis algorithms for reversible logic, and comprehensive theory of reversible logic synthesis, test and verification. 2. to implement reversible Field Programmable Gate rrays (FPGs) in CMOS technology for extremely low power, high testability and self-repair. 3. to create new theoretical algorithms for quantum computing. 4. to help one another to answer difficult research questions. 5. to work together on writing reports, journal and conference papers and software related to the above mentioned areas. 6. to compile a comprehensive list of relevant literature positions and Internet links. 7. to attend conferences and meetings and report about newest research in the world in the areas of reversible and quantum computing
Our current work includes: 1. Designing circuits in in reversible technologies 2. Designing gates in in new reversible technologies. 3. Developing logic, system and layout methodologies for reversible and quantum logic (every quantum logic is is reversible). 4. Designing systems (such as microprocessors) using reversible logic. 5. Developing highly efficient algorithms and computer programs for logic synthesis in in reversible logic. 4. Designing systems (such as microprocessors) using 5. Developing highly efficient algorithms and computer
Our current work includes: 6. Developing test algorithms and design for test methods for reversible technologies. 7. Developing formal verification and validation methods for reversible systems 8. Developing concepts of multiple-valued, fuzzy and continuous reversible logic. 9. Developing highly efficient data representations for reversible logic. 7. Developing formal verification and validation 8. Developing concepts of multiple-valued, fuzzy and 9. Developing highly efficient data representations for
Background
Reversible logic gate with k inputs and k outputs is called a k*k gate. conservative circuit preserves the number of logic values in all combinations. In balanced binary logic the circuit has half of minterms with value 1. In ternary logic one third of minterms have value 0, one third value 1 and one third has value 2 this is preserved from inputs to outputs.
Reversible logic circuit without constants on inputs which includes only reversible gates realizes on all outputs only balanced functions, therefore it can realize non-balanced functions only with garbage outputs. There are reversible circuits (such as Fredkin gate) that are conservative, but not all such circuits are conservative. Not all conservative gates are reversible. In reversible logic, the fanout of every signal, including primary inputs is one. The goal of this paper is to develop a method to build singleoutput reversible logic circuits in regular and non-regular structures, in binary and ternary logic, with minimized number of garbage output signals and gates.
Feynman Gate The 2*2 Feynman gate, called also controled-not or quantum XOR realizes functions P =, Q = @ B, where operator @ denotes EXOR.. When = 0 then Q = B, when = 1 then Q =!B. With B=0 Feynman gate is used as a fan-out gate. Every linear reversible function can be built by composing only 2*2 Feynman gates and inverters With B=0 Feynman gate is used as a fan-out gate.
Controlled NOT gate These three boolean expressions are identical, but lead to different physical realizations. We note, however, that these implementations not only make use of the 1-bit NOT function and the 2-bit CONTROLLED NOT function, but also of the 2-bit exchanger, i.e. the gate that interchanges two logic variables (realizing P = B as well as Q = ). This is an example of a general property: the EXCHNGER, the NOT, and the CONTROLLED NOT form a natural `generating set' for the twenty-four 2-bit reversible gates. More precisely, each reversible 2-bit gate can be synthesized by taking one or zero CONTROLLED NOTs and adding one or zero EXCHNGERs and one or zero NOTs to the left and to the right of it. Note that: neither the EXCHNGE R nor the NOT is a true 2-bit gate, but the CONTROLL ED NOT is one. See Table 4 Table 4: The three generators of the 2- bit reversible gates: (a) EXCHNGER, (b) NOT, (c) CONTROLLED NOT.
Binary Fredkin Gate Fredkin Gate is a fundamental concept in reversible and quantum computing. Every Boolean function can be build from 3 * 3 Fredkin gates: P =, Q = if then C else B, R = if then B else C.
Binary Fredkin Gate The universality of sets of 3*3 conservative gates with respect to all 3*3 reversible gates was considered by Sasao and Kinoshita. They also proved that and arbitrary n-variable function can be implemented by (n+3) * (n+3) circuits using Fredkin gates but their approach leads to long (thus slow and expensive) cascades of gates.
Toffoli Gate The 3 * 3 Toffoli gate is described by these equations: P =, Q = B, R = B @ C, Toffoli gate is an example of two-through gates, because two of its inputs are given to the output.
Kerntopf Gate The Kerntopf gate is described by equations: P = 1 @ @ B @ C @ B, Q = 1 @ B @ B @ C @ BC, R = 1 @ @ B @ C. When C=1 then P = + B, Q = * B, R =!B, so ND/OR gate is realized on outputs P and Q with C as the controlling input value. When C = 0 then P =! *! B, Q = +!B, R = @ B.
Kerntopf Gate Therefore for control input value 0 the gate realizes NND and IMPLICTION on outputs P and Q. s we see, the 3*3 Kerntopf gate is not a onethrough nor a two-through gate. Despite theoretical advantages of Kerntopf gate over classical Fredkin and Toffoli gates, so far there are no published results on optical or CMOS realizations of this gate.
Multi-valued Fredkin Gate MVFG is described by equations: B C D P = Q = B R = C if < B else R = D S = D if < B else S = C >= P Q R S B C D < < B P Q R S
Research on regular structures: Our goals
The fundamental role of Shannon Expansion in binary logic is well known. Shannon Expansion corresponds to a multiplexer gate. In reversible logic, an equivalent of multiplexer is the Fredkin gate. In this paper an equivalent of Shannon Expansion for reversible logic is created for the first time We We show its multiple-valued generalization using a new MV generalization of the Fredkin gate
We introduce regular structures, both planar and three-dimensional, to realize arbitrary functions in binary and multiplevalued reversible logic, respectively. problem in realizing functions in reversible logic is an excessive number of garbage output signals from gates. Our method effectively overcomes this problem. The method can be used in classical and quantum logic as well
Levelized Structures
Standard Lattice Diagrams for continuous, multiple-valued and binary logic
Lattice Structure for Multiple-valued and Binary Logic Patented by Pierzchala and Perkowski 1994/1999 Realizes every binary symmetric function Realizes every nonsymmetric function by repeating variables Realizes piece-wise linear multivalued functions
Lattice Structure for Multiple-valued and Binary Logic Cell has three inputs and two outputs Both outputs have the same function red eyes beard Binary input variables red nose Multi-valued output variable 0 1 Kowalski l-rabadi Piotrowski Perkowski Multiple-valued variables
Lattice Structure for Multiple-valued and Binary Logic Multivalued variables binary Multi-valued output variable Redness of nose in interval [3,4] 0 1 Length of beard an odd number Redness of eyes in intervals [2,4] or [7,9] Kowalski l-rabadi Piotrowski Perkowski
Multivalued input variables Lattice Structure for Multivalued and Binary Logic C<D Multivalued input variables E=G binary >B Multi-valued output variable 0 1 Kowalski l-rabadi Piotrowski Perkowski
Multivalued input variables Lattice Structure for Multivalued and Binary Logic Cell has 4 inputs and 2 outputs Multivalued input variables E G C D E=G B C<D Can we make the cell reversible? >B E<G or G>0 Multi-valued output variable 0 1 C>0 E<G and G<0 Kowalski l-rabadi Piotrowski Perkowski
Control left right output 0 value - value 1 - value value Control output left right left YZ right Control X 00 01 11 10 0 1 3 2 We want to make this cell reversible 0 4 0 0 1 1 5 7 6 Values not separated 1 0 1 1 0 output
output output1 Let us try to repeat control variable in output output1 output Control left right left YZ right Control X 00 01 11 10 0 1 3 2 0 00 00 10 10 Still not separated 1 4 5 7 6 01 11 11 01
output output1 output2 Repeating variables will not help output1 output Control left right left YZ right Control X 00 01 11 10 0 1 3 2 Now it works! 0 000 001 101 100 4 5 7 6 1 010 110 111 011
output1 output output2 Control left right Control left YZ right X 00 01 0 1 11 10 3 2 0 000 001 101 100 This means that we added another MUX 1 4 5 7 6 010 110 111 011 output output1 output2
INPUTS OUTPUTS 000 000 001 001 010 100 011 101 100 010 101 110 110 011 111 111 Permutation gate leftyzright X 00 01 Control 0 1 0 1 4 5 3 2 7 11 10 000 001 101 100 010 110 111 011 6 output output1 output2
. nd we reinvented the Fredkin Gate.!!! But how to use it in a Lattice?
Lattice Structure for Binary Logic F = S 1,3 (,B,C) 0 1 B C 0 1 0 1 S 0 S 1 S 2 S 3
Three-Dimensional Realization of Multiple- Valued Functions using Reversible Logic M. Perkowski,. l-rabadi Rabadi,, P. Kerntopf +,.Mishchenko Mishchenko,, and M. Chrzanowska-Jeske PORTLND QUNTUM LOGIC GROUP
Two-Dimensional Lattice Diagrams for reversible logic
Notation for Fredkin Gates Q R P Q R 0 1 0 1 0 1 P B C B C circuit from two multiplexers Its schematics This is a reversible gate, one of many
Three Types of General Expansions f Forward Shannon 0 1 f 0 f 1 f and f 0 and f 1
Three Types of General Expansions g h 0 1 0 1 (b) g 1 g 1 +h 0 h o g,h and g 1 +h 0 Reverse Shannon
Three Types of General Expansions Reversible Shannon g h 0 1 g, h, and g 0 +h 1 and g 1 +h 0 g 0 +h 1 g 1 +h 0
X YZ X 00 01 0 1 YZ 0 1 11 10 1 0 1 0 3 2 4 5 7 6 - - - - f X Y X YZ X 00 01 0 1 YZ 0 1 garbage garbage 00 01 11 10 0 1 3 2 1 0 1 0 4 5 0 h fg 0 1 hfg fgh Z 7 11 10 1 1 1 6 X g 0 1 gf YZ X 00 01 11 10 0 1 0 1 3 2 - - - - 4 5 7 6 - - - - X garbage YZ YZ X 00 01 11 10 0 1 1 i 0 1 garbage 0 1 3 2 - - - - 4 5 7 6 0 1 1 1 garbage garbage garbage 1 0 1 0
X X YZ YZ X 00 01 0 1 0 1 3 2 1 0 1 0 4 5 7 11 10 0 1 1 1 6 YZ X 00 01 0 1 11 10 0 1 3 2 - - - - 4 5 7 6 - - - - YZ YZ YZ YZ X 00 01 11 10 0 1 3 2 0 - - - - 4 5 7 6 1 - - - - X 00 01 11 10 0 1 3 2 0 1 0 1 0 4 5 7 6 1 - - - - X 00 01 11 10 0 1 3 2 0 - - - - 4 5 7 6 1 0 1 1 1 X 00 01 11 10 0 1 3 2 0 - - - - 4 5 7 6 1 - - - - YYZ YZ YZ YZ YZ Z X 00 01 11 10 0 1 3 2 0 - - - - 4 5 7 6 1 - - - - X 00 01 11 10 0 1 3 2 0 - - 1 0 4 5 7 6 1 - - - - X 00 01 11 10 0 1 3 2 0 1 0 - - 4 5 7 6 1 - - - - X 00 01 11 10 0 1 3 2 0 - - - - 4 5 7 6 1 0 1 - - X 00 01 0 4 1 3 2 - - - - 0 1 5 7 11 10 - - 1 1 6 = 1 YZ YZ YZ YZ X 00 01 11 10 0 1 3 2 0 - - 1-4 5 7 6 1 - - - - X 00 01 11 10 0 1 3 2 0 - - - 0 4 5 7 6 1 - - - - X 00 01 11 10 0 4 1 0 1 3 2 1 5-7 6-1 - - X 00 01 0 4 1 3 2-0 - - 5 7 6 0 - - - 0 1 11 10 =1 =0 =1 =0
Forward Shannon Expansion This graphical method can be easily extended to MV logic; for instance for the ternary logic the Kmap is splitted into three Kmaps; for x i = 0, for x i = 1, and for x i = 2, respectively. Each of these maps has one-third cares and two-thirds don t cares.
cofactor permuter Treating the reversible Shannon Expansion as the cofactor permuter is a useful heuristic to create algorithms. The method to synthesize such Lattices, called Levelized Variable Decomposition Method (for Shannon), presented here, is a special case of a general method of hierarchical decomposition of arbitrary reversible functions into reversible logic gates
cofactor permuter To distinguish this new general decomposition from the wellknown decompositions of shenhurst, Curtis or Shannon, we call it the Multi-purpose Portland Decomposition, the MP-decomposition for short.
Generalization We mapped the logic function to a lattice structure of geometrical connections there is nothing in our method to map to only this kind of structure we can map to any selected regular structure we can also map to a irregular structure with arbitrary connections
Generalizations of Fredkin gate Observe, that this definition of the gate does not specify the type of signals. Thus they can be binary, multi-valued, fuzzy, continuous or complex. The only requirement is that the relation of order (<) is defined on them It is interesting and important that a single reversible gate in binary logic has many generalizations in multiple-valued logic.
Generalizations of Fredkin gate Because it has been shown in [1] that there are many multiple-valued and multi-output (k>3) generalizations of Fredkin gate, the name modified assigned by Picton is not correct. The generalization invented by him we will call the Picton Gate, while generalization of Fredkinlike gates we call new gates.
Generalizations of Fredkin gate The exhaustive list of families of all such permutative multi-valued gates (both Shannonlike and Davio-like) has been presented in [1] and even more families in [18]. These of the new gates that use multiplexers only are similar to the original Fredkin gate but they use multiple-valued multiplexers. Such multiplexers have been already realized in many technologies, including super-pass transistors [9], so building these new gates should be also possible.
Generalizations of Fredkin gate We believe therefore that they are good candidates for future reversible multiple-valued nano-technologies. The new generalization of Fredkin gate using multi-valued logic has additional advantages and is simpler. Let us observe, that equations for the binary 4 * 4 binary Fredkin gate can be rewritten as follows: P =, Q = if =1 then C else if =0 then B, R = if =1 then B else if =0 then D, S = if =1 then D else if =0 then C Now, it can be easily generalized to a 4 * 4 ternary gate as follows: P =, Q = if =2 then B else if =1 then C else if =0 then D, R = if =2 then C else if =1 then D else if =0 then B, S = if =2 then D else if =1 then B else if =0 then C
Three-Dimensional Lattice Diagrams for reversible logic
Q R S P Q R S 0 1 2 0 1 2 0 1 2 P 2D symbol D C B D C B C Q ternary Fredkin gate (c) 3D symbol S D R P B
two-dimensional structure of ternary Fredkin gates x 1 1 x 2 2 3 4 x 3 8 7 6 5
8 x 1 x 2 2 7 x3 x 3 6 x 1 1 3 x 2 4 5 C Q three-dimensional structure of ternary Fredkin gates, corresponding to the previous one S D R B P
The general plan of the previous three-dimensional structure x 3 4 inputs to a cell 4 outputs from a cell x 2 x 1
The general plan of another three-dimensional structure 3 inputs to a cell 3 outputs from a cell Observe, that three dimensional structures can be also created with standard 3*3 Fredkin and binary 4*4 Fredkin gates.
The general plan of yet another three- dimensional structure 3 inputs to a cell 3 outputs from a cell
Reversible Lattice Structure for Binary Logic dvantages regular structure binary Fredkin Gate planar structure (good for Quantum Logic) Disadvantages Variable ordering? Symmetrization? Garbage still exists Easy algorithmic creation Reasonable garbage
Do you remember that there are other binary expansions? Ideas ll Binary Expansions Fredkin = <Var, S, fs> Shannon - S what about these? Flipped Shannon - fs <Var, pd, fpd> Positive Davio - pd <Var, nd, fnd> Negative Davio - nd <Var, nd, pd> Flipped Positive Davio - fpd. Flipped Negative Davio - fnd we checked some of them to work
Do you remember that there are other component functions of reversible gates Ideas ll Binary Balanced Expansions:.. Linear functions - L Negations - N Majorities - M Fredkin = <Var, S, fs> what about these? <N, pd, fpd> <Var, M, fnd> <Var, nd, L>. we checked some of them to work
s you see, this opens a very broad area of research that will lead to invention of new reversible gates and regular structures that use them Easy way to become a pioneer: Investigate all combinations Use genetic programming or other search methods to build structures and map functions to them There is a place for many researchers Nobody does this research But this was only for binary What about multivalued, fuzzy, arithmetic or other logics?
. nd we reinvented the Fredkin Gate.!!! But what about the variant with two control signals?
Multivalued input variables Lattice Structure for Multivalued and Binary Logic Cell has 4 inputs and 4 outputs Cell is reversible! MV and Generalized MV Fredkin C D Multivalued input variables E G Multi-valued output variable B 0 1 waste waste Kowalski l-rabadi Piotrowski Perkowski
Multi-valued logic generates less signals Hence it generates less waste Of course, it generates also less power, less connections and is easier to test
The main open research problem The real-life functions are multi-output. Thus, there exists an opportunity to re-use some waste functions in other output functions This is a tough problem. I do not know now how to solve it! We need some group creativity
Generalized Multi-valued Fredkin Gate Select other function of two variables < < B Select other pairs of VR-type and NOTtype functions B C D P Q R S Select other pairs of MUX-type functions
Generalized Multi-valued Fredkin Gate The number of these gates is astronomical We need both computer generation and some intelligence, simply generating them all would be a nonsense Very wide area of research It will give hints to gate designers what to look for
The general levelized method can assume any structure of the layout, thus any order and choice of input signals of successive Reversible Shannon expansions. ssuming other type of structure, cascade or non-planar lattice with intersecting signals, this other type of structure would be created. For arbitrary structures, however, the method requires small modification: if the structure is too constrained, the structural equations have no solutions or the algorithm loops.
This happens, for instance, when a Maitra Cascade structure is assumed for a function that is not Maitrarealizable. It happens also when we assume a levelized circuit of too narrow a bandwidth Thus the algorithm must be modified to deal with these special cases. Finally, our general approach will work also for irregular structures. In such case, any pair of signals can be the inputs to the Reversible Shannon Expansion, regardless of their order. The signals are paired to give the smallest evaluated total complexity for the level.
rbitrary symmetric function can be realized in a lattice without repeated variables. rbitrary (non-symmetric) function can be realized in a lattice with repeated variables (so-called symmetrization). Similar property exist for the presented method. This method terminates for arbitrary function, assuming that the variables are repeated in levels. Thus, if the leafs of the lattice are not constants after expanding for all input variables, some of these variables are used again in new levels of expansions, which we call variable repetition. Interestingly, the functions that do not require variable repetition in the Reversible Shannon Lattices are not symmetric functions. We work on the characterization of the functions realizable in these structures without repetitions and respective synthesis algorithms.
We can impose during joining the structure of the three dimensional lattice. Such lattice is typical for some crystals. There are also several other three-dimensional structures corresponding to other types of bonds or constraints that exist in Nature (for example, quantum dot computers). This leads to very many new circuit types, which are reversible and multi-valued generalizations of Shannon Lattices, Kronecker Lattices, Fat Trees, and many other structures introduced in the past.
Conclusions and Future Work New concepts: (1) Reversible Shannon Expansion for k*k binary Fredkin Gates (k>2), (2) planar Reversible Fredkin Lattice structures for logic based on binary 3 * 3 Fredkin gates, (3) Three-dimensional Reversible Fredkin Lattice structures for ternary logic based on 4 * 4 ternary new gates. We plan to design these gates in CMOS and Optical technologies.
Conclusions and Future Work fundamental idea of this paper is the use of three-dimensional space for reversible logic Several realizations of reversible and quantum logic, such as for instance quantum dots, involve a geometrical space. For instance, in the quantum dot model this space is two-dimensional. Here we propose to create three-dimensional regular structures, because our physical world is three dimensional.
Conclusions and Future Work Thus, three dimensional regular structures provide the best use of space. Creating our theoretical model, we hope that some day a way to build such structures in matter, possibly at the quantum level, will be invented.
Symmetric functions
Good Use of two Multi-valued Fredkin Gates to create MIN/MX gate B 0 1 >= >= MIN(,B) MX(,B) Min/max gate MIN(,B) MX(,B) Max/min gate MX(,B) MIN(,B)
MX/MIN gate in binary case Max/min gate MX(,B) MIN(,B) B f2 f6 f1 f3 Can be added in our future work, but is not necessary for this paper
regular regular outputs Property Even without ability of realizing any symmetric function of two variables one can realize arbitrary single-output symmetric function of any number of variables: by building a regular structure from MX/MIN gates and next applying EXORing operations to find single-value symmetric coefficients and next OR gates to sum them Single Index Unate interval symmetric symmetric functions functions inputs regular,simple Regular symmetric structure EXOR level EXOR level
Every Binary Symmetric Function can be composed of MIN/MX gates: Example for three variables B Max/Min gate MX(,B) MIN(,B) =*B =+B C MX(,B,C) = (+B)+C = Max/Min gate S 1,2,3 (,B,C) C(+B) S 2,3 (,B,C) = (*B) + C(+B) B 00 01 11 10 C 0 1 0 1 1 2 2 3 1 2 Max/Min gate MIN(,B,C) = (*B)*C = S 3 (,B,C) Indices of symmetric binary functions of 3 variables
Every single index Symmetric Function can be created by EXOR-ing last level gates of the previous regular expansion structure C B Max/Min gate MX(,B) MIN(,B) =+B Max/Min gate S 1,2,3 (,B,C) C(+B) S 1 (,B,C) =*B S 2,3 (,B,C) Max/Min gate S 3 (,B,C) S 2 (,B,C)
Example for four variables B Max/Min gate MX(,B) MIN(,B) MIN(,B) =*B =+B C Max/Min gate MX(,B,C) = (+B)+C = S 1,2,3 (,B,C) C(+B) D MX(,B,C,D) = +B+C+D = S 1,2,,3,4 (,B,C) Max/Min gate Max/Min gate S 2,3 (,B,C) = (*B) + C(+B) MIN(,B,C) = (*B)*C = Max/Min gate S,2.3.4 (,B,C,D) S 3 (,B,C) Max/Min gate S 3,4 (,B,C,D) MIN(,B,C,D) = *B*C*D = S 4 (,B,C,D)
Example for four variables, EXOR level added B Max/M in gate MX(,B) MIN(,B) MIN(,B) =*B =+B C MX(,B,C) = (+B)+C = S 1,2,3 (,B,C) Max/M in gate C(+B) D MX(,B,C,D) = +B+C+D = S 1,2,,3,4 (,B,C) Max/M in gate S 1 (,B,C,D) Max/M in gate S 2,3 (,B,C) = (*B) + C(+B) MIN(,B,C) = (*B)*C = Max/M in gate S,2.3.4 (,B,C,D) S 2 (,B,C,D) S 3 (,B,C) Max/M in gate S 3,4 (,B,C,D) S 3 (,B,C,D) S 4 (,B,C,D) MIN(,B,C,D) = *B*C*D = S 4 (,B,C,D) Now it is obvious that any multi-output function can be created by OR-ing the outputs of EXOR level
Now we extend to Reversible Logic B Max/M in gate MX(,B) MIN(,B) MIN(,B) =*B =+B C MX(,B,C) = (+B)+C = S 1,2,3 (,B,C) Max/M in gate C(+B) D MX(,B,C,D) = +B+C+D = S 1,2,,3,4 (,B,C) Max/M in gate S 1 (,B,C,D) S 2,3,4 (,B,C,D) Max/M in gate S 2,3 (,B,C) = (*B) + C(+B) MIN(,B,C) = (*B)*C = Max/M in gate S,2.3.4 (,B,C,D) S 2 (,B,C,D) S 3,4 (,B,C,D) S 3 (,B,C) Max/M in gate S 3,4 (,B,C,D) S 3 (,B,C,D) S 4 (,B,C,D) MIN(,B,C,D) = *B*C*D = S 4 (,B,C,D) Denotes Feynman (controlled NOT) gate Denotes fan-out gate
B Max/M in gate MX(,B) MIN(,B) MIN(,B) =*B =+B Theorem for Binary Reversible Logic C MX(,B,C) = (+B)+C = S 1,2,3 (,B,C) Max/M in gate C(+B) D MX(,B,C,D) = +B+C+D = S 1,2,,3,4 (,B,C) Max/M in gate S 1 (,B,C,D) S 2,3,4 (,B,C,D) Max/M in gate S 2,3 (,B,C) = (*B) + C(+B) MIN(,B,C) = (*B)*C = Max/M in gate S,2.3.4 (,B,C,D) S 2 (,B,C,D) S 3,4 (,B,C,D) S 3 (,B,C) Max/M in gate S 3,4 (,B,C,D) S 3 (,B,C,D) S 4 (,B,C,D) MIN(,B,C,D) = *B*C*D = S 4 (,B,C,D) Theorem 1: Every positive unate (symmetric ) function of 2 variables can be realized in 1 gate Every positive unate function of 3 variables can be realized in 1+2 gates Every positive unate function of 4 variables can be realized in 1+2+3 gates Every positive unate symmetric function of n variables can be realized in 1+2+.. n-1 = n(n-1)/2 MX/MIN gates
NOT FINISHED HERE B Max/M in gate MX(,B) MIN(,B) MIN(,B) =*B =+B Theorems for Binary Reversible Logic C MX(,B,C) = (+B)+C = S 1,2,3 (,B,C) Max/M in gate C(+B) D MX(,B,C,D) = +B+C+D = S 1,2,,3,4 (,B,C) Max/M in gate S 1 (,B,C,D) S 2,3,4 (,B,C,D) Max/M in gate S 2,3 (,B,C) = (*B) + C(+B) MIN(,B,C) = (*B)*C = Max/M in gate S,2.3.4 (,B,C,D) S 2 (,B,C,D) S 3,4 (,B,C,D) S 3 (,B,C) Max/M in gate S 3,4 (,B,C,D) S 3 (,B,C,D) S 4 (,B,C,D) MIN(,B,C,D) = *B*C*D = S 4 (,B,C,D) Theorem 2: Every single index totally symmetric function of n variables can be realized in n(n-1)/2 MX/MIN gates, n-2 fan-out gates and n-1 Feynman gates. Theorem 3: Every single-output totally symmetric function of n variables can be realized in n(n-1)/2 MX/MIN gates, n-2 fan-out gates, n-1 Feynman gates and XXX? OR gates.
Theorems for Binary Reversible Logic rbitrary symmetric function can be created by exoring single indices S 1 (,B,C,D) S 2,3,4 (,B,C,D) S 2 (,B,C,D) S 3,4 (,B,C,D) S 2 (,B,C,D) S 3 (,B,C,D) S 1 @S 2 =s 1,2 S 4 (,B,C,D) S 4 S 1,2 @S 4 =s 1,2,4 Next functions
Synthesis from (p)kfdds
Previous levels f 1 f 2 f 3 f 4... c i Other same level * + * +... * + * +... k 1 k 2 k 3 k 4 k 5 k 6 next levels
Previous levels f 1 f 2 f 3 f 4... * + * + Other same level... * + * + c i... k 1 k 2 k 3 k 4 k 5 k 6 next levels
Compositions and Decompositions
dders One possible implementation of a half adder B CCN CN xor B (Sum) 0 and B (Carry) Feynman Toffoli
How to build the Half-dder? B 0 CCN B Toffoli CN Feynman xor B (Sum) and B (Carry) B xor 0 YZ X 00 01 0 0 1 11 10 3 2 Product-like 4 5 7 6 1 Sum-like
Can we do this systematically? B 0 CCN B Toffoli CN Feynman xor B (Sum) and B (Carry) B xor B * B B xor 0 B 00 01 11 10 Mapping of a half-adder 00 10 01 10 This is what we would like to have But this is not reversible,
The simplest way to separate them is to add variable Can we do this systematically? B 0 CCN B Toffoli CN Feynman xor B (Sum) and B (Carry) B xor B * B B xor 0 B 00 01 11 10 Mapping of a half-adder 00 10 01 10
Can we do this systematically? B 0 CCN B Toffoli CN Feynman xor B (Sum) and B (Carry) B xor B * B B xor 0 B 00 01 11 10 Mapping of a half-adder 000 010 101 110 This is what we would like to have But this is not reversible, because more outputs than inputs
Can we do this systematically? B 0 CCN B Toffoli CN Feynman xor B (Sum) and B (Carry) B C xor B * B xor C B xor 0 Mapping of a half-adder C B YZ X 00 01 11 10 0 0 1 3 2 000 010 101 110 1 4 5 7 6 001 011 100 111 Now function is reversible of,b,c arguments Positive Davio Gate
We invented a new reversible gate with three inputs and three outputs B C But it is not Toffoli gate + xor B * + * B xor C B C Feynman xor B * B xor C Toffoli B C + * + * B xor C xor B
We showed that the new gate can be composed from Toffoli and Feynman Gates B C xor B * B xor C Because Toffoli gate is universal, every gate can be designed from it. But, generating a big waste of outputs Here we showed that we can generate the new gate only from two gates with only one waste of outputs waste of outputs should be the efficiency measure of the method
dders B 0 One possible implementation of a full adder CN CCN CCN CN XOR B Sum C-in C-out
dders B 0 C- in CCN CCN CN CN XOR B Sum C- out 0 adder
nother Systematic Method
(a) (b) (c) B 00 01 11 10 00 10 01 10 B 00 01 11 10 000 010 101 110 C YZ X 00 01 0 1 B 0 1 4 5 R,P,Q 3 2 7 11 10 000 010 101 110 001 011 100 111 R,P,Q Needs separation P,Q 6 C=0: P=@B, Q=B B C P=@B, Q=B, R= added to separate P=@B, Q=B, R= (d) R= P= @ B Q=B @ C
Decomposing with Kerntopf s Gate C=1 B Q=B P=+B R=!B CN f=b (carry) g= @ B (Sum) Garbage Feynman Kerntopf
Decomposing with Toffoli s Gate B 0 CCN B Toffoli CN Feynman R= P= @ B (Sum) Q=B (Carry) B @ 0
daptations of functional decomposition methods
......... H H H (a) G... G... G... (b) shenhurst/curtis like reversible decompositions (c)
(a) (b) a...... 1 a n b 1 b m...... a 1 a b m 1 b n Bi-Decomposition-like reversible decompositions