PHP37N6LT, PHB37N6LT, PHD37N6LT FEATURES SYMBOL QUICK REFERENCE DATA Trench technology d V DSS = 55 V Very low on-state resistance Fast switching I D = 37 A Stable off-state characteristics High thermal cycling performance g R DS(ON) 35 mω (V GS = 5 V) Low thermal resistance R DS(ON) 3 mω (V GS = V) s GENERAL DESCRIPTION N-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using trench technology. The device has very low on-state resistance. It is intended for use in dc to dc converters and general purpose switching applications. The PHP37N6LT is supplied in the SOT78 (TOAB) conventional leaded package. The PHB37N6LT is supplied in the SOT44 surface mounting package. The PHD37N6LT is supplied in the SOT48 surface mounting package. PINNING SOT78 (TOAB) SOT44 SOT48 PIN DESCRIPTION gate tab tab tab drain 3 source tab drain 3 3 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 34) SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V DSS Drain-source voltage T j = 5 C to 75 C - 55 V V DGR Drain-gate voltage T j = 5 C to 75 C; R GS = kω - 55 V V GS Gate-source voltage - ± 3 V I D Continuous drain current T mb = 5 C - 37 A T mb = C - 6 A I DM Pulsed drain current T mb = 5 C - 48 A P D Total power dissipation T mb = 5 C - W T j, T stg Operating junction and - 55 75 C storage temperature It is not possible to make connection to pin of the SOT48 or SOT44 packages. September 998 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT THERMAL RESISTANCES SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT R th j-mb Thermal resistance junction -.5 K/W to mounting base R th j-a Thermal resistance junction SOT78 package, in free air 6 - K/W to ambient SOT44 and SOT48 packages, pcb 5 - K/W mounted, minimum footprint ESD LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT V C Electrostatic discharge Human body model ( pf,.5 kω) - kv capacitor voltage, all pins ELECTRICAL CHARACTERISTICS T j = 5 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT V (BR)DSS Drain-source breakdown V GS = V; I D =.5 ma; 55 - - V voltage T j = -55 C 5 - - V V (BR)GSS Gate-source breakdown I G = ± ma; - - V voltage V GS(TO) Gate threshold voltage V DS = V GS ; I D = ma..5. V T j = 75 C.5 - - V T j = -55 C - -.3 V R DS(ON) Drain-source on-state V GS = 5 V; I D = 7 A - 8 35 mω resistance V GS = V; I D = 7 A - 6 3 mω T j = 75 C - - 74 mω g fs Forward transconductance V DS = 5 V; I D = 5 A 4 - S I GSS Gate source leakage current V GS = ±5 V; V DS = V -. µa T j = 75 C - - µa I DSS Zero gate voltage drain V DS = 55 V; V GS = V; -.5 µa current T j = 75 C - - 5 µa Q g(tot) Total gate charge I D = 3 A; V DD = 44 V; V GS = 5 V -.5 - nc Q gs Gate-source charge - 6 - nc Q gd Gate-drain (Miller) charge - - nc t d on Turn-on delay time V DD = 3 V; I D = 5 A; - 4 ns t r Turn-on rise time V GS = 5 V; R G = Ω - 77 ns t d off Turn-off delay time Resistive load - 55 8 ns t f Turn-off fall time - 48 65 ns L d Internal drain inductance Measured from tab to centre of die - 3.5 - nh L d Internal drain inductance Measured from drain lead to centre of die - 4.5 - nh (SOT78 package only) L s Internal source inductance Measured from source lead to source - 7.5 - nh bond pad C iss Input capacitance V GS = V; V DS = 5 V; f = MHz - 5 4 pf C oss Output capacitance - 5 45 pf C rss Feedback capacitance - 3 5 pf September 998 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS T j = 5 C unless otherwise specified SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT I S Continuous source current - - 37 A (body diode) I SM Pulsed source current (body - - 48 A diode) V SD Diode forward voltage I F = 5 A; V GS = V -.95. V I F = 34 A; V GS = V -. - V t rr Reverse recovery time I F = 34 A; -di F /dt = A/µs; - 4 - ns Q rr Reverse recovery charge V GS = - V; V R = 3 V -.6 - µc AVALANCHE LIMITING VALUE SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT W DSS Drain-source non-repetitive I D = A; V DD 5 V; V GS = 5 V; - 45 mj unclamped inductive turn-off R GS = 5 Ω; T mb = 5 C energy 9 8 7 6 5 4 3 PD% Normalised Power Derating 4 6 8 4 6 8 Tmb / C Fig.. Normalised power dissipation. PD% = P D /P D 5 C = f(t mb ) 9 8 7 6 5 4 3 ID% Normalised Current Derating 4 6 8 4 6 8 Tmb / C Fig.. Normalised continuous drain current. ID% = I D /I D 5 C = f(t mb ); conditions: V GS 5 V September 998 3 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT 45 RDS(ON)/mOhm ID/A VGS/V = 4 RDS(ON) = VDS/ID tp = us 4 4. 4.4 DC us us ms ms ms VDS/V Fig.3. Safe operating area. T mb = 5 C I D & I DM = f(v DS ); I DM single pulse; parameter t p 35 3 5 3 ID/A 4 5 6 Fig.6. Typical on-state resistance, T j = 5 C. R DS(ON) = f(i D ); parameter V GS 4.6 4.8 5 ZTH/ (K/W) 7 ID/A 6.5. 5 4...5. P D tp T D = T tp t 3..E-6.. t/s Fig.4. Transient thermal impedance. Z th j-mb = f(t); parameter D = t p /T Tj/C = 75 5 3 4 5 6 7 VGS/V Fig.7. Typical transfer characteristics. I D = f(v GS ) ; conditions: V DS = 5 V; parameter T j Drain current, ID (A) 7 8 6 VGS = 6. V 5.6 5. 4.6 Transconductance, gfs (S) 3 5 4 4. 3.6 3. 5 4 6 8 Drain-source voltage, VDS (V) Fig.5. Typical output characteristics, T j = 5 C. I D = f(v DS ); parameter V GS 5 3 4 5 6 7 Drain current, ID (A) Fig.8. Typical transconductance, T j = 5 C. g fs = f(i D ); conditions: V DS = 5 V September 998 4 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT a.5 BUK959-6 Rds(on) normlised to 5degC.5..5 Thousands pf.5. Ciss.5.5 - -5 5 5 Tmb / degc Fig.9. Normalised drain-source on-state resistance. a = R DS(ON) /R DS(ON)5 C = f(t j ); I D = 7 A; V GS = 5 V Coss Crss.. VDS/V Fig.. Typical capacitances, C iss, C oss, C rss. C = f(v DS ); conditions: V GS = V; f = MHz VGS(TO) / V.5 max. typ..5 BUK959-6 6 VGS/V 5 4 VDS = 4V VDS = 44V min. 3.5 - -5 5 5 Tj / C Fig.. Gate threshold voltage. V GS(TO) = f(t j ); conditions: I D = ma; V DS = V GS 5 5 5 QG/nC Fig.3. Typical turn-on gate-charge characteristics. V GS = f(q G ); conditions: I D = 3 A; parameter V DS E- Sub-Threshold Conduction IF/A E- 8 E-3 % typ 98% 6 Tj/C = 75 5 E-4 4 E-5 E-5.5.5.5 3 Fig.. Sub-threshold drain current. I D = f(v GS) ; conditions: T j = 5 C; V DS = V GS.5.5 VSDS/V Fig.4. Typical reverse diode current. I F = f(v SDS ); conditions: V GS = V; parameter T j September 998 5 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT 9 8 7 6 5 4 3 WDSS% 4 6 8 4 6 8 Tmb / C Fig.5. Normalised avalanche energy rating. W DSS % = f(t mb ); conditions: I D = A VGS L VDS T.U.T. RGS R shunt + - Fig.6. Avalanche energy test circuit. W DSS =.5 LI D BV DSS /(BV DSS V DD ) VDD -ID/ September 998 6 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT MECHANICAL DATA Dimensions in mm Net Mass: g 4,5 max,3 max 3,7,3,8 5,9 min 5,8 max 3, max not tinned,3 max (x) 3,54,54 3, 3,5 min,9 max (3x),6,4 Fig.7. SOT78 (TOAB); pin connected to mounting base. Notes. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide.. Refer to mounting instructions for SOT78 (TO) envelopes. 3. Epoxy meets UL94 V at /8". September 998 7 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT MECHANICAL DATA Dimensions in mm Net Mass:.4 g.3 max 4.5 max.4 max max 5.4.5.54 (x).85 max (x) Fig.8. SOT44 : centre pin connected to mounting base..5 MOUNTING INSTRUCTIONS Dimensions in mm.5 9. 7.5. 3.8 Fig.9. SOT44 : soldering pattern for surface mounting. Notes. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide.. Epoxy meets UL94 V at /8". 5.8 September 998 8 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT MECHANICAL DATA Dimensions in mm : Net Mass:.4 g seating plane 6.73 max tab..38 max.93 max 5.4 6. max.4 max 4 min 4.6.5 min.5.85 (x) 3.8 max (x).3.5 Fig.. SOT48 : centre pin connected to mounting base. MOUNTING INSTRUCTIONS Dimensions in mm 7. 7..5.5.5 4.57 Fig.. SOT48 : soldering pattern for surface mounting. Notes. Observe the general handling precautions for electrostatic-discharge sensitive devices (ESDs) to prevent damage to MOS gate oxide.. Epoxy meets UL94 V at /8". September 998 9 Rev.4
PHP37N6LT, PHB37N6LT, PHD37N6LT DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 34). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 998 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. September 998 Rev.4