DATA SHEET. HEF4894B 12-stage shift-and-store register LED driver. For a complete data sheet, please also download: INTEGRATED CIRCUITS

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Transcription:

INTEGRTED CIRCUITS DT SHEET For a complete data sheet, please also download: The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC 12-stage shift-and-store register LED driver File under Integrated Circuits, IC04 January 1995

PPLICTIONS utomotive Industrial GENERL DESCRIPTION The is a 12 stage serial shift register having a storage latch associated with each stage for strobing data from the serial input to parallel LED driver outputs O 0 to O 11. Data is shifted on positive-going clock transitions. The data in each shift register stage is transferred to the storage register when the strobe (STR) input is HIGH. Data in the storage register appears at the outputs whenever the output enable (EO) signal is HIGH. Two serial outputs (O s and O s ) are available for cascading a number of devices. Data is available at O s on positive-going clock edges to allow high-speed operation in cascaded systems in which the clock rise time is fast. The same serial information is available at O s on the next negative-going clock edge and provides cascading devices when the clock rise time is slow. ORDERING ND PCKGE INFORMTION TYPE PCKGES NUMBER PINS PIN POSITION MTERIL CODE T 20 SO plastic SO20/SOT163 P 20 DIL plastic DIL20/SOT146 PINNING PIN SYMBOL NME ND FUNCTION 1 STR strobe input 2 D data input 3 CP clock input 4, 5, 6, 7, 8, 9, 18, O 0 to O 11 parallel outputs (open drain) 17, 16, 15, 14, 13 10 V ss ground 11, 12 O s,o s serial outputs 19 EO output enable input 20 positive supply voltage FMILY DT See Family Specifications except for: Rating for DC current into any open-drain output: 40 m. I DD LIMITS category MSI: see Family Specifications. Preliminary pin assignment. Fig.1 Pinning diagram. Fig.2 Functional diagram. January 1995 2

Fig.3 Logic diagram. FUNCTION TBLE INPUTS PRLLEL OUTPUTS SERIL OUTPUTS CP EO STR D O 0 O n O S O S L X X Z Z O 10 nc Fig.4 One D-latch. L X X Z Z nc O 11 H L X nc nc O 10 nc H H L Z O n 1 O 10 nc H H H L O n 1 O 10 nc H H H nc nc nc O 11 Notes 1. H = HIGH state (the more positive voltage) 2. L = LOW state (the less positive voltage) 3. X = state is immaterial 4. = positive-going transition 5. = negative-going transition 6. Z = high impedance OFF state 7. nc = no change 8. O 11 = the information in the twelfth shift register stage. t the positive clock edge the information in the 10 th register stage is transferred to the 11 th register stage and the O s output. January 1995 3

DC CHRCTERISTICS V SS =0 V. T amb ( C) PRMETER SYMBOL 40 + 25 + 85 UNIT CONDITIONS MIN. MX. MIN. MX. MIN. MX. output voltage 5 V OL 0.75 0.75 1.5 V V I =V SS or ; LOW; O n 10 0.75 0.75 1.5 I o < 20 m 15 0.75 0.75 1.5 output leakage 5 I OZH 2 2 15 µ V o = 15 V current; HIGH; O n 10 2 2 15 15 2 2 15 C CHRCTERISTICS V SS = 0 V; T amb =25 C; input transition times 20 ns. PRMETER TYPICL FORMUL FOR P (µw) Dynamic power 5 1200 f i + (f o C L ) V 2 DD where: dissipation per package 10 5550 f i + (f o C L ) V 2 DD R load = (P) 15 15000 f i + (f o C L ) V 2 DD f i = input frequency (MHz), f o = output frequency (MHz), C L = load capacitance (pf), (f o C L ) = sum of outputs = supply voltage C CHRCTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns. PRMETER SYMBOL TYP. MX. UNIT TYPICL EXTRPOLTION FORMUL Propagation delay 5 160 320 132 ns + (0.55 ns/pf) C L CP to O s 10 t PHL 65 130 ns 53 ns + (0.23 ns/pf) C L HIGH to LOW 15 45 90 37 ns + (0.16 ns/pf) C L Propagation delay 5 130 260 102 ns + (0.55 ns/pf) C L CP to O s 10 t PLH 55 110 ns 44 ns + (0.23 ns/pf) C L LOW to HIGH 15 40 80 32 ns + (0.16 ns/pf) C L Propagation delay 5 120 240 92 ns + (0.55 ns/pf) C L CP to O s 10 t PHL 50 100 ns 39 ns + (0.23 ns/pf) C L HIGH to LOW 15 40 80 32 ns + (0.16 ns/pf) C L Propagation delay 5 130 260 102 ns + (0.55 ns/pf) C L CP to O s 10 t PLH 60 120 ns 49 ns + (0.23 ns/pf) C L LOW to HIGH 15 45 90 37 ns + (0.16 ns/pf) C L January 1995 4

PRMETER SYMBOL TYP. MX. UNIT TYPICL EXTRPOLTION FORMUL Propagation delay 5 240 480 CP to O n 10 t PZL 80 160 ns see note 1 OFF to LOW 15 55 110 Propagation delay 5 170 340 CP to O n 10 t PLZ 75 150 ns see note 1 LOW to OFF 15 60 120 Propagation delay 5 140 280 STR to O n 10 t PZL 70 140 ns see note 1 OFF to LOW 15 55 110 Propagation delay 5 100 200 STR to O n 10 t PLZ 40 100 ns see note 1 LOW to OFF 15 35 70 Output transition 5 85 170 35 ns + (1.0 ns/pf) C L time; O s,o s 10 t THL 40 80 ns 19 ns + (0.42 ns/pf) C L HIGH to LOW 15 30 60 16 ns + (0.28 ns/pf) C L Output transition 5 85 170 35 ns + (1.0 ns/pf) C L time; O s,o s 10 t TLH 40 80 ns 19 ns + (0.42 ns/pf) C L LOW to HIGH 15 30 60 16 ns + (0.28 ns/pf) C L Note 1. Definition of symbol equivalent to 3-state outputs. C CHRCTERISTICS V SS = 0 V; T amb =25 C; C L = 50 pf; input transition times 20 ns. PRMETER SYMBOL MIN. TYP. MX. UNIT output enable time 5 t PZL 100 200 ns EO to O n 10 55 110 OFF to LOW 15 50 100 output disable time 5 t PLZ 80 160 ns EO to O n 10 40 80 LOW to OFF 15 30 60 minimum clock pulse width 5 t WCPL 60 30 ns LOW 10 30 15 15 24 12 minimum strobe pulse width 5 t WSTRH 80 40 ns HIGH 10 60 30 15 24 12 January 1995 5

PRMETER SYMBOL MIN. TYP. MX. UNIT set-up time 5 t su 60 30 ns D to CP 10 20 10 15 15 5 hold time 5 t hold 5 15 ns D to CP 10 20 5 15 20 5 Maximum clock pulse frequency 5 f max 5 10 MHz 10 11 22 15 14 28 Fig.5 Timing diagram. January 1995 6

PPLICTION INFORMTION n example of applications for the is: Serial-to-parallel converting LED driver Fig.6 LED driver register. January 1995 7

PDF: 1999 pr 16 Philips Semiconductors Package outline DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1 D M E seating plane 2 L 1 Z 20 e b b 1 11 w M c (e ) 1 M H pin 1 index E 1 10 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H 4.2 0.51 3.2 0.17 0.020 0.13 1.73 1.30 0.068 0.051 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 26.92 26.54 1.060 1.045 6.40 6.22 0.25 0.24 2.54 7.62 0.10 0.30 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 8.3 0.39 0.33 w 0.254 0.01 (1) Z max. 2.0 0.078 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT146-1 SC603 92-11-17 95-05-24

PDF: 1999 pr 16 Philips Semiconductors Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E X c y H E v M Z 20 11 Q 2 1 ( ) 3 pin 1 index L L p θ 1 e b p 10 w M detail X 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2.65 0.10 1 2 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 0.30 0.10 0.012 0.004 2.45 2.25 0.096 0.089 0.25 0.01 0.49 0.36 0.019 0.014 0.32 0.23 0.013 0.009 13.0 12.6 0.51 0.49 7.6 7.4 0.30 0.29 1.27 0.050 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 10.65 10.00 0.419 0.394 1.4 0.055 1.1 0.4 0.043 0.016 1.1 1.0 0.043 0.039 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.9 0.4 o 8 o 0.035 0 0.016 OUTLINE VERSION REFERENCES IEC JEDEC EIJ EUROPEN PROJECTION ISSUE DTE SOT163-1 075E04 MS-013C 95-01-24 97-05-22