ΗΜΥ 307 ΨΗΦΙΑΚΑ ΟΛΟΚΛΗΡΩΜΕΝΑ ΚΥΚΛΩΜΑΤΑ Εαρινό Εξάμηνο 2018 ΔΙΑΛΕΞΗ 3: Το MOS Τρανζίστορ ΧΑΡΗΣ ΘΕΟΧΑΡΙΔΗΣ (ttheocharides@ucy.ac.cy) [Προσαρμογή από Rabaey s Digital Integrated Circuits, 2002, J. Rabaey et al. ]
Overview of Last Lecture - Metrics l Functionality l Cost NRE (fixed) costs - design effort RE (variable) costs - cost of parts, assembly, test l Reliability, robustness Noise margins Noise immunity l Performance Speed (delay) Power consumption; energy l Time-to-market ΗΜΥ307 Δ3 MOS Transistor.2 Θεοχαρίδης, ΗΜΥ, 2018
Design Abstraction Levels - Review SYSTEM + MODULE GATE CIRCUIT V in V out S n+ G DEVICE D n+ ΗΜΥ307 Δ3 MOS Transistor.3 Θεοχαρίδης, ΗΜΥ, 2018
Introduction v Early 20 th century, vacuum tube was used for the amplifier and switch. Vacuum Tube Radio ENIAC, the first general-purpose electronic computer, contains 17,468 vacuum tubes. l However, Vacuum Tube is too big, fragile, and energy-consuming. Transistor solved this problem. ΗΜΥ307 Δ3 MOS Transistor.4 Θεοχαρίδης, ΗΜΥ, 2018
Transistors Transistors of various type & size BJT (PNP) Electrical Diagram Representation First Transistor Model, 1947 Used in all modern electronics FET Transistor BJT Transistor ΗΜΥ307 Δ3 MOS Transistor.5 Θεοχαρίδης, ΗΜΥ, 2018
l tran sis tor a semiconductor device that amplifies, oscillates, or switches the flow of current between two terminals by varying the current or voltage between one of the terminals and a third. (www.dictionary.com) www.coltecnica.com ΗΜΥ307 Δ3 MOS Transistor.6 Θεοχαρίδης, ΗΜΥ, 2018
Ø Basic Purpose [1] To electronically switch (no moving parts) a signal on or off (high/low) [2] To amplify signals Ø Role in Modern Electronics Basic building blocks for all modern electronics Microprocessors, Microcontrollers, Computers, Digital watches, Digital Logic Circuits, Cell Phones. Microprocessor PC & Cell Phones Motor Controllers Headphones ΗΜΥ307 Δ3 MOS Transistor.7 Θεοχαρίδης, ΗΜΥ, 2018
Reason for Transistor s Invention: Early 20 th century, vacuum tube were used as signal amplifiers & switches. Vacuum Tube Radios ENIAC : 17, 468 vacuum tubes Use of vacuum tube* resulted in extremely large, fragile, energy inefficient, and expensive electronics. Evolution of electronics required device that was small, light weight, robust, reliable, cheap to manufacture, energy efficient *Vacuum tube advantages: operation at higher voltages (10K region vs. 1K region of transistors); high power, high frequency operation (over-the-air TV broadcasting) better suited for vacuum tubes; and silicon transistors more vulnerable to electromagnetic pulses than vacuum tubes ΗΜΥ307 Δ3 MOS Transistor.8 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Invention of Transistor l Invention In 1947, John Bardeen, Walter Brattain, and William Schockly, researchers at Bell Lab, invented Transistor. They found Transistor Effect: when electrical contacts were applied to a crystal of germanium, the output power was larger than the input. John Bardeen, Walter Brattain, and William Schockly In 1956, they were awarded the Nobel Prize in physics. First model of Transistor, 1947 ΗΜΥ307 Δ3 MOS Transistor.9 Θεοχαρίδης, ΗΜΥ, 2018
A Brief History - Invention of the Transistor n Vacuum tubes ruled in first half of 20 th century Large, expensive, power-hungry, unreliable n 1947: first point contact transistor (3 terminal devices) n Shockley, Bardeen and Brattain at Bell Labs ΗΜΥ307 Δ3 MOS Transistor.10 Θεοχαρίδης, ΗΜΥ, 2018
A Brief History, contd.. q 1958: First integrated circuit n n n Flip-flop using two transistors Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor Kilby s IC smithsonianchips.si.edu/ augarten/ ΗΜΥ307 Δ3 MOS Transistor.11 Θεοχαρίδης, ΗΜΥ, 2018
A Brief History, contd. n First Planer IC built in 1961 n 2003 n Intel Pentium 4 µprocessor (55 million transistors) n 512 Mbit DRAM (> 0.5 billion transistors) n 53% compound annual growth rate over 45 years n No other technology has grown so fast so long n Driven by miniaturization of transistors n Smaller is cheaper, faster, lower in power! n Revolutionary effects on society ΗΜΥ307 Δ3 MOS Transistor.12 Θεοχαρίδης, ΗΜΥ, 2018
MOS Integrated Circuits q 1970 s processes usually had only nmos transistors Inexpensive, but consume power while idle q 1980s-present: CMOS processes for low idle power Intel 1101 256-bit SRAM Intel 4004 4-bit µproc ΗΜΥ307 Δ3 MOS Transistor.13 Θεοχαρίδης, ΗΜΥ, 2018
Pentium 4 Processor http://www.intel.com/intel/intelis/museum/online/hist_micro/hof/index.htm ΗΜΥ307 Δ3 MOS Transistor.14 Θεοχαρίδης, ΗΜΥ, 2018
Size Matters! Modern transistors are few microns wide and approximately 0.1 micron or less in length Human hair is 80-90 microns in diameter Ref: http://micro.magnet.fsu.edu/creatures/technical/sizematters.html ΗΜΥ307 Δ3 MOS Transistor.15 Θεοχαρίδης, ΗΜΥ, 2018
Infinite possibilities V mv groun d ΗΜΥ307 Δ3 MOS Transistor.16 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Definition of Transistor A transistor is a three-terminal semiconductor device that amplifies or switches the flow of current between two terminals by varying the current or voltage between one of the terminals and a third. ΗΜΥ307 Δ3 MOS Transistor.17 Θεοχαρίδης, ΗΜΥ, 2018
Digression: Silicon Semiconductors l l l Modern electronic chips are built mostly on silicon substrates Silicon is a Group IV semiconducting material crystal lattice: covalent bonds hold each atom to four neighbors Si Si Si Si Si Si Si Si Si http://onlineheavytheory.net/silicon.html ΗΜΥ307 Δ3 MOS Transistor.18 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Semiconductor l Semiconductor is a material that has an electrical resistivity between that of a conductor and an insulator. has a few charge carriers( holes or free electrons). the conductivity increases by adding impurities or dopants(doping). Silicon is used in most commercial semiconductors ΗΜΥ307 Δ3 MOS Transistor.19 Θεοχαρίδης, ΗΜΥ, 2018
Transistor Manufacturing Process Doping: Process of introducing impure elements (dopants) into semiconductor wafers to form regions of differing electrical conductivity. ØDoping impurities into a pure semiconductor will increase conductivity. ØDoping results in an N-Type or P-Type semiconductor. High-Temp Furnace Pure Wafers Ion Implanter Wafer Refinement Doped Wafers ΗΜΥ307 Δ3 MOS Transistor.20 Θεοχαρίδης, ΗΜΥ, 2018
Dopants l Silicon is a semiconductor at room temperature l Pure silicon has few free carriers and conducts poorly l Adding dopants increases the conductivity drastically l Dopant from Group V (e.g. As, P): extra electron (ntype) l Dopant from Group III (e.g. B, Al): missing electron, called hole (p-type) Si Si - Si Si Si + Si Si + As Si Si B - Si Si Si Si Si Si Si ΗΜΥ307 Δ3 MOS Transistor.21 Θεοχαρίδης, ΗΜΥ, 2018
p-n Junctions l First semiconductor (two terminal) devices l A junction between p-type and n-type semiconductor forms a diode. l Current flows only in one direction p-type n-type anode cathode ΗΜΥ307 Δ3 MOS Transistor.22 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Doping v Doping: add neighboring elements to the semiconductor to make it electropositive or electronegative n P(positive)-type doping is adding Acceptor impurities (from Group III) to the semiconductor in order to increase holes. n Ex: Silicon doped with Boron n N(negative)-type doping is adding Donor impurities (from Group V) with more electrons in order to increase free electrons. n Ex: Silicon doped with Phosphorous Add Group III(Boron) Add Group V (Phosphorous) ΗΜΥ307 Δ3 MOS Transistor.23 Θεοχαρίδης, ΗΜΥ, 2018
Effect of Doping on Semi-Conductors P-Type Semiconductors : Positively charged Semiconductor Dopant Material: Boron, Aluminum, Gallium Effect of Dopant: Creates holes (positive charges where electrons have been removed) in lattice structure ΗΜΥ307 Δ3 MOS Transistor.24 Θεοχαρίδης, ΗΜΥ, 2018
Effect of Doping on Semi-Conductors N-Type Semiconductors : Negatively charged Semiconductor Dopant Material: Phosphorous, Arsenic, Antimony (Sb) Effect of Dopant: Added unbound electrons create negative charge in lattice structure ØRemember: Dopant is added to same piece of semiconductor material ØResulting Material: Single, solid material called P-N Junction ΗΜΥ307 Δ3 MOS Transistor.25 Θεοχαρίδης, ΗΜΥ, 2018
Introduction P-N Junction v PN Junction n is a junction formed by P-type and N-type semiconductors together in very close contact. n n n What happens at the junction? Thin depletion region forms near junction at an equilibrium condition (Zero bias) Near the p n interface, electrons from N diffuses into P, leaving positively charged ions in N region; holes from P diffuses into N, leaving negatively charged ions in P region Ions exhibit a force which inhibits further carriers flow across the P-N Junction unless a forward bias external voltage is applied ΗΜΥ307 Δ3 MOS Transistor.26 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Forward and Reverse Bias l Forward bias -V pumps electrons into the N-region. +V pumps more holes into the P-region. Excess of charge in P and N region will apply pressure on the depletion region and will make it shrink. current flows v Reverse bias n n n n -V sucked out electrons from N-region. +V sucked out holes from P-region. The depletion layer widens and it occupies the entire diode(p-n). current doesn t flow ΗΜΥ307 Δ3 MOS Transistor.27 Θεοχαρίδης, ΗΜΥ, 2018
Electrical Switching on P-N Junction ØApplying External Voltage of Forward Biasing polarity facilitates motion of free electrons of Reverse Biasing polarity impedes motion of free electrons Forward Biasing Circuit is On Current is Flowing Reverse Biasing Circuit is Off Current not Flowing ΗΜΥ307 Δ3 MOS Transistor.28 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Transistor l Transistor is comprised by two P-N junctions: Base- Collector junction and Base-Emitter junction. ΗΜΥ307 Δ3 MOS Transistor.29 Θεοχαρίδης, ΗΜΥ, 2018
Finally combining all concepts ØSemiconductor -> Doping -> P-N Junction -> Depletion Region ØOne P-N Junction can control current flow via an external voltage ØTwo P-N junctions (bipolar junction transistor, BJT) can control current flow and amplify the current flow. ØAlso, if a resistor is attached to the output, the resulting voltage output is much greater than the applied voltage, due to amplified current. Example at end. ΗΜΥ307 Δ3 MOS Transistor.30 Θεοχαρίδης, ΗΜΥ, 2018
Introduction Types of Transistor l Transistor are categorized by Semiconductor material: germanium, silicon, gallium arsenide, etc. Structure: BJT, FET, IGFET (MOSFET), IGBT Polarity: NPN, PNP (BJTs); N-channel, P-channel (FETs) Maximum power rating: low, medium, high Maximum operating frequency: low, medium, high Application: switch, audio, high voltage, etc. Physical packaging: through hole, surface mount, ball grid array, etc. Amplification factor v General Purpose Transistors n n n Bipolar Junction Transistor (BJT) Field Effect Transistors (FET) Power Transistors NPN BJT n-channel JFET ΗΜΥ307 Δ3 MOS Transistor.31 Θεοχαρίδης, ΗΜΥ, 2018
Transistor Types n Bipolar (junction) transistors n npn or pnp silicon structure n Small current into very thin base layer controls large currents between emitter and collector n Base currents limit integration density n Metal Oxide Semiconductor Field Effect Transistors n nmos and pmos MOSFETS n Voltage applied to insulated gate controls current between source and drain n Low power allows very high integration n First patent in the 20s in USA and Germany n Not widely used until the 60s but mostly late 70s ΗΜΥ307 Δ3 MOS Transistor.32 Θεοχαρίδης, ΗΜΥ, 2018
Introduction A bipolar junction transistor (BJT) is a three terminal semiconductor device in which the operation depends on the interaction of both majority and minority carriers and hence the name Bipolar. It is used in amplifier and oscillator circuits, and as a switch in digital circuit. It has wide applications in computers, satellites and other modern communication system. ΗΜΥ307 Δ3 MOS Transistor.33 Θεοχαρίδης, ΗΜΥ, 2018
Structure and Symbols ΗΜΥ307 Δ3 MOS Transistor.34 Θεοχαρίδης, ΗΜΥ, 2018
Three Regions in BJT Ø Emitter is heavily doped so that it can inject a large number of charge carriers into the base. Ø Base is lightly doped and very thin, therefore it passes most of the injected charge carriers from the emitter into the collector. Ø Collector is moderately doped and larger in size, so that it collects the major portion of the majority carriers supplied by the emitter. ΗΜΥ307 Δ3 MOS Transistor.35 Θεοχαρίδης, ΗΜΥ, 2018
Device: The MOS Transistor Gate oxide Source n+ Polysilicon Gate Drain n+ Field-Oxide (SiO 2 ) p substrate p+ stopper Bulk contact CROSS-SECTION of NMOS Transistor ΗΜΥ307 Δ3 MOS Transistor.36 Θεοχαρίδης, ΗΜΥ, 2018
Field Effect Transistor, FET ΗΜΥ307 Δ3 MOS Transistor.37 Θεοχαρίδης, ΗΜΥ, 2018
What makes a FET? 3 terminal device with: Drain Source Gate The body has contacts at the ends: the drain and source Gate surrounds the body and can induce a channel by use of electric field FET Input voltage controls output current BJT Input current controls output current Gate Base Controls flow of current Drain Collector Current goes out here Source Emitter Current comes in here ΗΜΥ307 Δ3 MOS Transistor.38 Θεοχαρίδης, ΗΜΥ, 2018
What is a FET? Semiconductor device that uses electric field to control current, thus, the channel conductivity. Unipolar transistor involving single carrier type operation, in contrast to BJT. Relies on PNP or NPN junctions to allow current flow Performs same functions as a BJT; amplifier and switch. FET ΗΜΥ307 Δ3 MOS Transistor.39 Θεοχαρίδης, ΗΜΥ, 2018
How does a MOSFET work? nmos device in enhancement mode Equilibrium energy band diagram l Structure: Device formed on lightly doped p-type substrate. Source and drain are heavily doped with n-type. Oxide layer separates gate from Si surface. Result: N-P-N type, nmos. Operation: V GS > V th ΗΜΥ307 Δ3 MOS Transistor.40 Θεοχαρίδης, ΗΜΥ, 2018
Circuit: The CMOS Inverter V DD V in V out C L NEXT Lecture! ΗΜΥ307 Δ3 MOS Transistor.41 Θεοχαρίδης, ΗΜΥ, 2018
MOS Transistors l l Four terminal device: gate, source, drain, body Gate oxide body stack looks like a capacitor Gate and body are conductors (body is also called the substrate) SiO 2 (oxide) is a good insulator (separates the gate from the body Called metal oxide semiconductor (MOS) capacitor, even though gate is mostly made of poly-crystalline silicon (polysilicon) Source Gate Drain Polysilicon Polysilicon Source Gate Drain SiO 2 SiO 2 n+ n+ p+ p+ p bulk Si n bulk Si NMOS PMOS ΗΜΥ307 Δ3 MOS Transistor.42 Θεοχαρίδης, ΗΜΥ, 2018
I D (ma) Review: Reverse Bias Diode l The ideal diode equation (for both forward and reverse-bias conditions) is + V D - I D = I S (e V D / f T 1) where V D is the voltage applied to the junction a forward-bias lowers the potential barrier allowing carriers to flow across the diode junction a reverse-bias raises the potential barrier and the diode becomes nonconducting f T = kt/q = 26mV at 300K -0.5 I S is the saturation current of the diode 2.5 1.5 0.5-1 -0.75-0.5-0.25 0 0.25 0.5 0.75 1 V D (V) ΗΜΥ307 Δ3 MOS Transistor.43 Θεοχαρίδης, ΗΜΥ, 2018
The MOS Transistor Polysilicon Aluminum ΗΜΥ307 Δ3 MOS Transistor.44 Θεοχαρίδης, ΗΜΥ, 2018
A weird picture ΗΜΥ307 Δ3 MOS Transistor.45 Θεοχαρίδης, ΗΜΥ, 2018
The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers Source n+ W Polysilicon Gate L Gate oxide Drain n+ Field-Oxide (SiO 2 ) p substrate p+ stopper Bulk (Body) p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers ΗΜΥ307 Δ3 MOS Transistor.46 Θεοχαρίδης, ΗΜΥ, 2018
But it s true J ΗΜΥ307 Δ3 MOS Transistor.47 Θεοχαρίδης, ΗΜΥ, 2018
Switch Model of NMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 0 ) Closed (on) (Gate = 1 ) R on V GS < V T V GS > V T ΗΜΥ307 Δ3 MOS Transistor.48 Θεοχαρίδης, ΗΜΥ, 2018
Switch Model of PMOS Transistor V GS Gate Source (of carriers) Drain (of carriers) Open (off) (Gate = 1 ) Closed (on) (Gate = 0 ) R on V GS > V DD V T V GS < V DD V T ΗΜΥ307 Δ3 MOS Transistor.49 Θεοχαρίδης, ΗΜΥ, 2018
Threshold Voltage Concept S V GS + - G D n+ n+ n channel p substrate depletion region B The value of V GS where strong inversion occurs is called the threshold voltage, V T ΗΜΥ307 Δ3 MOS Transistor.50 Θεοχαρίδης, ΗΜΥ, 2018
The Threshold Voltage where V T = V T0 + g(ö -2f F + V SB - Ö -2f F ) V T0 is the threshold voltage at V SB = 0 and is mostly a function of the manufacturing process Difference in work-function between gate and substrate material, oxide thickness, Fermi voltage, charge of impurities trapped at the surface, dosage of implanted ions, etc. V SB is the source-bulk voltage f F = -f T ln(n A /n i ) is the Fermi potential (f T = kt/q = 26mV at 300K is the thermal voltage; N A is the acceptor ion concentration; n i» 1.5x10 10 cm -3 at 300K is the intrinsic carrier concentration in pure silicon) g = Ö(2qe si N A )/C ox is the body-effect coefficient (impact of changes in V SB ) (e si =1.053x10-10 F/m is the permittivity of silicon; C ox = e ox /t ox is the gate oxide capacitance with e ox =3.5x10-11 F/m) ΗΜΥ307 Δ3 MOS Transistor.51 Θεοχαρίδης, ΗΜΥ, 2018
V T (V) The Body Effect 0.9 0.85 0.8 0.75 0.7 0.65 0.6 0.55 0.5 0.45 0.4-2.5-2 -1.5-1 -0.5 0 V BS (V) V SB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) A negative bias causes V T to increase from 0.45V to 0.85V ΗΜΥ307 Δ3 MOS Transistor.52 Θεοχαρίδης, ΗΜΥ, 2018
Transistor/switch/amplifier a 3 terminal device Source Vein Artery Valve Gate Drain Dam Laser Heart Emitter Collector Ion Channel Base BJT MOSFET Axonal conduction ΗΜΥ307 Δ3 MOS Transistor.53 Θεοχαρίδης, ΗΜΥ, 2018
All of these share a feature with Output current can toggle between large and small (Switching à Digital logic; create 0s and 1s) Small change in valve (3 rd terminal) creates Large change in output between 1 st and 2 nd terminal (Amplification à Analog applications; Turn 0.5 à 50) ΗΜΥ307 Δ3 MOS Transistor.54 Θεοχαρίδης, ΗΜΥ, 2018
Recall: History! http://www.computerhistory.org/semiconductor/timeline.html#1940s ΗΜΥ307 Δ3 MOS Transistor.55 Θεοχαρίδης, ΗΜΥ, 2018
Recall p-n junction P N N P W + - V appl > 0 W + - V appl < 0 Forward bias, + on P, - on N (Shrink W, V bi ) Allow holes to jump over barrier into N region as minority carriers I Reverse bias, + on N, - on P (Expand W, V bi ) Remove holes and electrons away from depletion region I V V ΗΜΥ307 Δ3 MOS Transistor.56 Θεοχαρίδης, ΗΜΥ, 2018
Bipolar Junction Transistors: Basics Bias Mode E-B Junction C-B Junction Saturation Forward Forward Active Forward Reverse Inverted Reverse Forward Cutoff Reverse Reverse ΗΜΥ307 Δ3 MOS Transistor.57 Θεοχαρίδης, ΗΜΥ, 2018
PNP transistor amplifier action IN (small) OUT (large) ΗΜΥ307 Δ3 MOS Transistor.58 Θεοχαρίδης, ΗΜΥ, 2018
So: MOS Transistor in Linear Mode Assuming V GS > V T S V GS G D V DS I D n+ - V(x) + n+ x B The current is a linear function of both V GS and V DS ΗΜΥ307 Δ3 MOS Transistor.59 Θεοχαρίδης, ΗΜΥ, 2018
Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron) l When V DS V GS V T where I D = k n W/L [(V GS V T )V DS V DS2 /2] k n = µ n C ox = µ n e ox /t ox = is the process transconductance parameter (µ n is the carrier mobility (m 2 /Vsec)) k n = k n W/L is the gain factor of the device For small V DS, there is a linear dependence between V DS and I D, hence the name resistive or linear region ΗΜΥ307 Δ3 MOS Transistor.60 Θεοχαρίδης, ΗΜΥ, 2018
Transistor in Saturation Mode Assuming V GS > V T S V GS G V DS V DS > V GS - V T D I D n+ - V GS - V + n+ T B Pinch-off The current remains constant (saturates). ΗΜΥ307 Δ3 MOS Transistor.61 Θεοχαρίδης, ΗΜΥ, 2018
Voltage-Current Relation: Saturation Mode For long channel devices l When V DS ³ V GS V T I D = k n /2 W/L [(V GS V T ) 2 ] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS V T l However, the effective length of the conductive channel is modulated by the applied V DS, so I D = I D (1 + lv DS ) where l is the channel-length modulation (varies with the inverse of the channel length) ΗΜΥ307 Δ3 MOS Transistor.62 Θεοχαρίδης, ΗΜΥ, 2018
Current Determinates l For a fixed V DS and V GS (> V T ), I DS is a function of the distance between the source and drain L the channel width W the threshold voltage V T the thickness of the SiO 2 t ox the dielectric of the gate insulator (SiO 2 ) e ox the carrier mobility for nfets: µ n = 500 cm 2 /V-sec for pfets: µ p = 180 cm 2 /V-sec ΗΜΥ307 Δ3 MOS Transistor.63 Θεοχαρίδης, ΗΜΥ, 2018
Long Channel I-V Plot (NMOS) 6 X 10-4 V GS = 2.5V 5 V DS = V GS - V T I D (A) 4 3 2 1 Linear V GS = 2.0V Saturation V GS = 1.5V V GS = 1.0V Quadratic dependence 0 cut-off 0 0.5 1 1.5 2 2.5 V DS (V) NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V ΗΜΥ307 Δ3 MOS Transistor.64 Θεοχαρίδης, ΗΜΥ, 2018
Short Channel Effects 10 u n (m/s) Behavior of short channel device mainly due to 5 Constant mobility (slope = µ) u sat =10 5 Constant velocity Velocity saturation the velocity of the carriers saturates due to scattering (collisions suffered by the carriers) 0 x c = 0 1.5 3 x(v/µm) For an NMOS device with L of.25µm, only a couple of volts difference between D and S are needed to reach velocity saturation ΗΜΥ307 Δ3 MOS Transistor.65 Θεοχαρίδης, ΗΜΥ, 2018
Voltage-Current Relation: Velocity Saturation For short channel devices l Linear: When V DS V GS V T I D = k(v DS ) k n W/L [(V GS V T )V DS V DS2 /2] where k(v) = 1/(1 + (V/x c L)) is a measure of the degree of velocity saturation l Saturation: When V DS = V DSAT ³ V GS V T I DSat = k(v DSAT ) k n W/L [(V GS V T )V DSAT V DSAT2 /2] ΗΜΥ307 Δ3 MOS Transistor.66 Θεοχαρίδης, ΗΜΥ, 2018
Velocity Saturation Effects 0 V GS = V DD 10 Long V DSAT V GS -V T channel devices Short channel devices For short channel devices and large enough V GS V T V DSAT < V GS V T so the device enters saturation before V DS reaches V GS V T and operates more often in saturation I DSAT has a linear dependence wrt V GS so a reduced amount of current is delivered for a given control voltage ΗΜΥ307 Δ3 MOS Transistor.67 Θεοχαρίδης, ΗΜΥ, 2018
Short Channel I-V Plot (NMOS) 2.5 2 X 10-4 Early Velocity Saturation V GS = 2.5V I D (A) 1.5 1 0.5 Linear Saturation V GS = 2.0V V GS = 1.5V V GS = 1.0V Linear dependence 0 0 0.5 1 1.5 2 2.5 V DS (V) NMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = 0.4V ΗΜΥ307 Δ3 MOS Transistor.68 Θεοχαρίδης, ΗΜΥ, 2018
MOS I D -V GS Characteristics I D (A) 6 5 4 3 2 1 0 X 10-4 long-channel quadratic short-channel linear 0 0.5 1 1.5 2 2.5 V GS (V) Linear (short-channel) versus quadratic (longchannel) dependence of I D on V GS in saturation Velocity-saturation causes the shortchannel device to saturate at substantially smaller values of V DS resulting in a substantial drop in current drive (for V DS = 2.5V, W/L = 1.5) ΗΜΥ307 Δ3 MOS Transistor.69 Θεοχαρίδης, ΗΜΥ, 2018
Short Channel I-V Plot (PMOS) All polarities of all voltages and currents are reversed -2 V DS (V) -1 0 0 V GS = -1.0V -0.2 V GS = -1.5V V GS = -2.0V -0.4-0.6-0.8 I D (A) V GS = -2.5V -1 X 10-4 PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V ΗΜΥ307 Δ3 MOS Transistor.70 Θεοχαρίδης, ΗΜΥ, 2018
The MOS Current-Source Model G I D = 0 for V GS V T 0 S I D D I D = k W/L [(V GS V T )V min V min2 /2](1+lV DS ) for V GS V T ³ 0 B with V min = min(v GS V T, V DS, V DSAT ) and V GT = V GS - V T Determined by the voltages at the four terminals and a set of five device parameters V T0 (V) g(v 0.5 ) V DSAT (V) k (A/V 2 ) l(v -1 ) NMOS 0.43 0.4 0.63 115 x 10-6 0.06 PMOS -0.4-0.4-1 -30 x 10-6 -0.1 ΗΜΥ307 Δ3 MOS Transistor.71 Θεοχαρίδης, ΗΜΥ, 2018
The Transistor Modeled as a Switch R eq (Ohm) 7 6 5 4 3 2 x10 5 S V GS ³ V T R on D Modeled as a switch with infinite off resistance and a finite on resistance, R on Resistance inversely proportional to W/L (doubling W halves R on ) 1 0 0.5 1 1.5 2 2.5 (for V GS = V DD, V DS = V DD V DD /2) V DD (V) For V DD >>V T +V DSAT /2, R on independent of V DD Once V DD approaches V T, R on increases dramatically V DD (V) 1 1.5 2 2.5 NMOS(kW) 35 19 15 13 PMOS (kw) 115 55 38 31 R on (for W/L = 1) For larger devices divide R eq by W/L ΗΜΥ307 Δ3 MOS Transistor.72 Θεοχαρίδης, ΗΜΥ, 2018
Other (Submicron) MOS Transistor Concerns l Velocity saturation l Subthreshold conduction Transistor is already partially conducting for voltages below V T l Threshold variations In long-channel devices, the threshold is a function of the length (for low V DS ) In short-channel devices, there is a drain-induced threshold barrier lowering at the upper end of the V DS range (for low L) l Parasitic resistances resistances associated with the source and drain contacts l Latch-up During a latchup when one of the transistors is conducting, the other one begins conducting too. They both keep each other in saturation for as long as the structure is forward-biased and some current flows through it - which usually means until a power-down. S R S G R D D ΗΜΥ307 Δ3 MOS Transistor.73 Θεοχαρίδης, ΗΜΥ, 2018
Subthreshold Conductance 10-2 I D (A) 10-12 Subthreshold exponential region V T Linear region Quadratic region Transition from ON to OFF is gradual (decays exponentially) Current roll-off (slope factor) is also affected by increase in temperature S = n (kt/q) ln (10) (typical values 60 to 100 mv/decade) 0 0.5 1 1.5 2 2.5 V GS (V) I D ~ I S e (qv GS /nkt) where n ³ 1 Has repercussions in dynamic circuits and for power consumption ΗΜΥ307 Δ3 MOS Transistor.74 Θεοχαρίδης, ΗΜΥ, 2018
Subthreshold I D vs V GS I D = I S e (qv GS /nkt) (1 - e (qv DS /kt) )(1 + lv DS ) V DS from 0 to 0.5V ΗΜΥ307 Δ3 MOS Transistor.75 Θεοχαρίδης, ΗΜΥ, 2018
Subthreshold I D vs V DS I D = I S e (qv GS /nkt) (1 - e (qv DS /kt) )(1 + lv DS ) V GS from 0 to 0.3V ΗΜΥ307 Δ3 MOS Transistor.76 Θεοχαρίδης, ΗΜΥ, 2018
Threshold Variations V T V T Long-channel threshold Low V DS threshold Threshold as a function of the length (for low V DS ) L V DS Drain-induced barrier lowering (for low L) ΗΜΥ307 Δ3 MOS Transistor.77 Θεοχαρίδης, ΗΜΥ, 2018
Friday: The CMOS Inverter V DD V in V out C L ΗΜΥ307 Δ3 MOS Transistor.78 Θεοχαρίδης, ΗΜΥ, 2018