ECE 425 Midterm Overview Fall 2017
Overview q Midterm (20% of total grade) Oct 24 th 3:30-5:00pm in class q Materials Lecture 1 through 11 MP0, MP1 HW1, HW2 Practice exam q Rules 1 page of cheat sheet, Closed book Scientific calculator only, No other electronics ECE425 Intro VLSI System Design Slide 2
Lecture 1 Overview of VLSI: Complexity, Wires, and Switches Slides courtesy of Deming Chen Some slides courtesy of Ken Yang (UCLA) and David Harris (Harvey Mudd) ECE425 Intro VLSI System Design
Transistors The voltage on the gate (poly connection) controls the current that flows between the source and drain (diffusion terminals). The transistor model is often displayed by drawing its currentvoltage curve. We will talk about more later. 6 0 0 5 0 0 gate I d s ( u A ) 4 0 0 3 0 0 drain I DS source 2 0 0 1 0 0 0 0 0. 5 1 1. 5 2 2. 5 V d s ( V ) ECE425 Intro VLSI System Design
Design Levels q q Specification what the system (or component) is supposed to do Architecture high-level design of component q q q Circuit transistor circuits to realize logic elements Device behavior of individual circuit elements Layout state defined logic partitioned into major blocks geometry used to define and connect circuit elements q Logic q Process gates, flip-flops, and the connections between them steps used to define circuit elements ECE425 Intro VLSI System Design
Lecture 2: IC Fabrication Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
nmos Transistor q Four terminals: gate, source, drain, body q Gate oxide body stack looks like a capacitor Gate and body are conductors SiO 2 (oxide) is a very good insulator Called metal oxide semiconductor (MOS) capacitor Even though gate is Source Gate Drain no longer made of metal Polysilicon SiO 2 n+ n+ p bulk Si ECE425 Intro VLSI System Design Slide 7
Transistors as Switches q We can view MOS transistors as electrically controlled switches q Voltage at gate controls path from source to drain g = 0 g = 1 nmos g d d OFF d ON s s s d d d pmos g ON OFF s s s ECE425 Intro VLSI System Design Slide 8
CMOS Inverter A Y 0 1 1 0 A Y V DD ON A=0 Y=1 OFF GND ECE425 Intro VLSI System Design Slide 9
Inverter Cross-section q Typically use p-type substrate for nmos transistors q Requires n-well for body of pmos transistors A GND Y V DD SiO 2 n+ diffusion n+ n+ p+ p substrate n well p+ p+ diffusion polysilicon metal1 nmos transistor pmos transistor ECE425 Intro VLSI System Design Slide 10
Inverter Mask Set q Transistors and wires are defined by masks q Cross-section taken along dashed line A Y GND V DD substrate tap nmos transistor pmos transistor well tap ECE425 Intro VLSI System Design Slide 11
Lecture 3: Circuits & Layout Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Complementary CMOS q Complementary CMOS logic gates nmos pull-down network pmos pull-up network a.k.a. static CMOS inputs pmos pull-up network output Pull-up OFF Pull-down OFF Z (float) 1 Pull-up ON nmos pull-down network Pull-down ON 0 X (crowbar) 1: 13 Circuits & Layout Intro VLSI System Design
Series and Parallel q nmos: 1 = ON q pmos: 0 = ON g1 g2 a b a 0 0 b a 0 1 b a 1 0 b a 1 1 b q Series: both must be ON q Parallel: either can be ON (a) g1 g2 a b OFF OFF OFF ON a a a a 0 0 1 1 0 1 0 1 b b b b (b) ON OFF OFF OFF a a a a a g1 g2 0 0 0 1 1 0 1 1 b b b b b (c) OFF ON ON ON a a a a a g1 g2 0 0 0 1 1 0 1 1 b b b b b (d) ON ON ON OFF 1: 14 Circuits & Layout Intro VLSI System Design
Conduction Complement q Complementary CMOS gates always produce 0 or 1 q Ex: NAND gate Series nmos: Y=0 when both inputs are 1 Thus Y=1 when either input is 0 Requires parallel pmos q Rule of Conduction Complements Pull-up network is complement of pull-down Parallel -> series, series -> parallel A B Y 1: 15 Circuits & Layout Intro VLSI System Design
Compound Gates q Compound gates can do any inverting function q Ex: Y = A B+ C D (AND-AND-OR-INVERT, AOI22) A C A C B D B D (a) (b) (c) A B C D (d) C A D B C A A B D B C D Y A B C D (f) Y (e) 1: 16 Circuits & Layout Intro VLSI System Design
Pass Transistors q Transistors can be used as switches s g d s s g = 0 g = 1 d d Input g = 1 Output 0 strong 0 g = 1 1 degraded 1 g s g = 0 d Input g = 0 Output 0 degraded 0 s d s g = 1 d 1 g = 0 strong 1 1: Circuits & Layout Intro VLSI System Design 17
D Latch q When CLK = 1, latch is transparent D flows through to Q like a buffer q When CLK = 0, the latch is opaque Q holds its old value independent of D q a.k.a. transparent latch or level-sensitive latch CLK CLK D Latch Q D Q 1: 18 Circuits & Layout Intro VLSI System Design
D Flip-flop q When CLK rises, D is copied to Q q At all other times, Q holds its value q a.k.a. positive edge-triggered flip-flop, master-slave flip-flop CLK CLK D D Flop Q Q 1: 19 Circuits & Layout Intro VLSI System Design
Gate Layout q Layout can be very time consuming Design gates to fit together nicely Build a library of standard cells q Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts 1: 20 Circuits & Layout Intro VLSI System Design
Example: NAND3 q Horizontal n-diffusion and p-diffusion strips q Vertical polysilicon gates q Metal1 V DD rail at top q Metal1 GND rail at bottom q 32 λ by 40 λ 1: 21 Circuits & Layout Intro VLSI System Design
Stick Diagrams q Stick diagrams help plan layout quickly Need not be to scale Draw with color pencils or dry-erase markers V DD A V DD A B C metal1 c poly ndiff Y Y pdiff contact GND INV GND NAND3 1: 22 Circuits & Layout Intro VLSI System Design
Wiring Tracks q A wiring track is the space required for a wire 4 λ width, 4 λ spacing from neighbor = 8 λ pitch q Transistors also consume one wiring track q Estimate area by counting wiring tracks Multiply by 8 to express in λ 1: 23 Circuits & Layout Intro VLSI System Design
Lecture 4: MIPS Processor Example Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Design Partitioning q Architecture: User s perspective, what does it do? Instruction set, registers MIPS, x86, Alpha, PIC, ARM, q Microarchitecture Single cycle, multcycle, pipelined, superscalar? q Logic: how are functional blocks constructed Ripple carry, carry lookahead, carry select adders q Circuit: how are transistors used Complementary CMOS, pass transistors, domino q Physical: chip layout Datapaths, memories, random logic MIPS Processor Example Intro VLSI System Design 25
Instruction Encoding q 32-bit instruction encoding Requires four cycles to fetch on 8-bit datapath format example encoding 6 5 5 5 5 6 R add $rd, $ra, $rb 0 ra rb rd 0 funct 6 5 5 16 I beq $ra, $rb, imm op ra rb imm 6 26 J j dest op dest MIPS Processor Example Intro VLSI System Design 26
Logic Design q Start at top level Hierarchically decompose MIPS into units q Top-level interface crystal oscillator 2-phase clock generator ph1 ph2 reset MIPS processor memread memwrite adr writedata memdata 8 8 8 external memory MIPS Processor Example Intro VLSI System Design 27
Circuit Design q How should logic be implemented? NANDs and NORs vs. ANDs and ORs? Fan-in and fan-out? How wide should transistors be? q These choices affect speed, area, power q Logic synthesis makes these choices for you Good enough for many applications Hand-crafted circuits are still better MIPS Processor Example Intro VLSI System Design 28
Gate-level Netlist module carry(input a, b, c, output cout) wire x, y, z; and g1(x, a, b); and g2(y, a, c); and g3(z, b, c); or g4(cout, x, y, z); endmodule a b a c b c g1 g2 g3 x y z g4 cout MIPS Processor Example Intro VLSI System Design 29
Transistor-Level Netlist module carry(input a, b, c, output cout) wire i1, i2, i3, i4, cn; tranif1 n1(i1, 0, a); tranif1 n2(i1, 0, b); tranif1 n3(cn, i1, c); tranif1 n4(i2, 0, b); tranif1 n5(cn, i2, a); tranif0 p1(i3, 1, a); tranif0 p2(i3, 1, b); tranif0 p3(cn, i3, c); tranif0 p4(i4, 1, b); tranif0 p5(cn, i4, a); tranif1 n6(cout, 0, cn); tranif0 p6(cout, 1, cn); endmodule a a p1 c c n1 b p3 n3 b p2 i3 i1 n2 b a a b p4 i4 p5 cn n5 i2 n4 p6 n6 cout MIPS Processor Example Intro VLSI System Design 30
Standard Cells q Uniform cell height q Uniform well height q M1 V DD and GND rails q M2 Access to I/Os q Well / substrate taps q Exploits regularity MIPS Processor Example Intro VLSI System Design 31
Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Introduction q So far, we have treated transistors as ideal switches q An ON transistor passes a finite amount of current Depends on terminal voltages Derive current-voltage (I-V) relationships q Transistor gate, source, drain all have capacitance I = C (ΔV/Δt) -> Δt = (C/I) ΔV Capacitance and current determine speed CMOS Transistor Theory Intro VLSI System Design 33
Terminal Voltages q Mode of operation depends on V g, V d, V s V gs = V g V s V gd = V g V d V gs - + V g + V gd - q q q V ds = V d V s = V gs - V V gd s Source and drain are symmetric diffusion terminals By convention, source is terminal at lower voltage Hence V ds 0 nmos body is grounded. First assume source is 0 too. Three regions of operation Cutoff Linear Saturation - V + ds V d CMOS Transistor Theory Intro VLSI System Design 34
nmos I-V Summary q Shockley 1 st order transistor models CMOS Transistor Theory Intro VLSI System Design 35
Example q Use 0.6 µm process From AMI Semiconductor t ox = 100 Å µ = 350 cm 2 /V*s V t = 0.7 V q Plot I ds vs. V ds V gs = 0, 1, 2, 3, 4, 5 Use W/L = 4/2 λ 14 W 3.9 8.85 10 W W β = µcox = ( 350) 120 µa/v L 8 = 100 10 L L I ds (ma) 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 2 V ds V gs = 5 V gs = 4 V gs = 3 V gs = 2 V gs = 1 CMOS Transistor Theory Intro VLSI System Design 36
pmos I-V q All dopings and voltages are inverted for pmos Source is the more positive terminal q Mobility µ p is determined by holes Typically 2-3x lower than that of electrons µ n 120 cm 2 /V s in AMI 0.6 µm process q Thus pmos must be wider to provide same current In this class, assume µ n / µ p = 2 I ds (ma) 0-0.2-0.4-0.6 V gs = -4 V gs = -3 V gs = -2 V gs = -5-0.8-5 -4-3 -2-1 0 V ds V gs = -1 CMOS Transistor Theory Intro VLSI System Design 37
Ideal vs. Simulated nmos I-V Plot q 65 nm IBM process, V DD = 1.0 V I ds (ma) 1200 1000 800 Simulated Ideal V gs = 1.0 Velocity saturation & Mobility degradation: I on lower than ideal model predicts I on = 747 ma @ Channel length modulation: V gs = V ds = V DD Saturation current increases with V ds V gs = 1.0 600 400 Velocity saturation & Mobility degradation: Saturation current increases less than quadratically with V gs V gs = 0.8 V gs = 0.8 200 V gs = 0.6 V gs = 0.6 V gs = 0.4 0 0 0.2 0.4 0.6 0.8 1 V ds Nonideal Transistor Theory Intro VLSI System Design 38
Threshold Voltage Effects q V t is V gs for which the channel starts to invert q Ideal models assumed V t is constant q Really depends (weakly) on almost everything else: Body voltage: Body Effect Drain voltage: Drain-Induced Barrier Lowering Channel length: Short Channel Effect Nonideal Transistor Theory Intro VLSI System Design 39
Body Effect q q q q Body is a fourth transistor terminal V sb affects the charge required to invert the channel Increasing V s or decreasing V b increases V t ( ) V = V + γ φ + V φ t t0 s sb s φ s = surface potential at threshold N A φ s = 2vT ln n i Depends on doping level N A And intrinsic carrier concentration n i γ = body effect coefficient γ t ox = 2qεsiN A = εox 2qε N C si ox A Nonideal Transistor Theory Intro VLSI System Design 40
Leakage q What about current in cutoff? q Simulated results q What differs? Current doesn t go to 0 in cutoff Nonideal Transistor Theory Intro VLSI System Design 41
Subthreshold Leakage q q q Subthreshold leakage exponential with V gs Vgs Vt 0 + ηvds kγvsb Vds e 1 e nvt vt Ids = Ids0 n is process dependent typically 1.3-1.7 Rewrite relative to I off on log scale q S 100 mv/decade @ room temperature Intro VLSI System Design 42 Nonideal Transistor Theory
Parameter Variation q Transistors have uncertainty in parameters Process: L eff, V t, t ox of nmos and pmos Vary around typical (T) values q Fast (F) L eff : short V t : low t ox : thin q Slow (S): opposite q Not all parameters are independent for nmos and pmos slow fast pmos slow SF SS TT nmos FF FS fast Nonideal Transistor Theory Intro VLSI System Design 43
Lecture 6: DC & Transient Response Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Pass Transistors q We have assumed source is grounded q What if source > 0? e.g. pass transistor passing V DD q V g = V DD If V s > V DD -V t, V gs < V t Hence transistor would turn itself off V DD V DD q nmos pass transistors pull no higher than V DD -V tn Called a degraded 1 Approach degraded value slowly (low I ds ) q pmos pass transistors pull no lower than V tp q Transmission gates are needed to pass both 0 and 1 DC and Transient Response Intro VLSI System Design 45
DC Response q DC Response: V out vs. V in for a gate q Ex: Inverter When V in = 0 -> V out = V DD When V in = V DD -> V out = 0 In between, V out depends on transistor size and current By KCL, must settle such that I dsn = I dsp We could solve equations V in But graphical solution gives more insight V DD I dsp I dsn V out DC and Transient Response Intro VLSI System Design 46
nmos Operation Cutoff Linear Saturated V gsn < V tn V in < V tn V gsn > V tn V in > V tn V dsn < V gsn V tn V out < V in - V tn V gsn > V tn V in > V tn V dsn > V gsn V tn V out > V in - V tn V DD V gsn = V in I dsp V dsn = V out V in I dsn V out DC and Transient Response Intro VLSI System Design 47
pmos Operation Cutoff Linear Saturated V gsp > V tp V in > V DD + V tp V gsp < V tp V in < V DD + V tp V dsp > V gsp V tp V out > V in - V tp V gsp < V tp V in < V DD + V tp V dsp < V gsp V tp V out < V in - V tp V DD V gsp = V in - V DD V tp < 0 V dsp = V out - V DD V in I dsp I dsn V out DC and Transient Response Intro VLSI System Design 48
I-V Characteristics q Make pmos is wider than nmos such that β n = β p V gsn5 I dsn V gsn4 -V dsp V gsn3 V gsp1 V gsp2 -V DD 0 V DD V gsn2 V gsn1 V gsp3 V dsn V gsp4 -I dsp V gsp5 DC and Transient Response Intro VLSI System Design 49
Operating Regions q Revisit transistor operating regions V DD V in V out Region nmos pmos A Cutoff Linear B Saturation Linear C Saturation Saturation D Linear Saturation E Linear Cutoff V out V DD A B 0 C D E V tn V DD /2 V DD +V tp V in V DD Intro VLSI System Design 50 DC and Transient Response
Beta Ratio q If β p / β n 1, switching point will move from V DD /2 q Called skewed gate q Other gates: collapse into equivalent inverter V DD V out β p 0.1 β = n β p 10 β = n 2 1 0.5 0 V in V DD DC and Transient Response Intro VLSI System Design 51
Transient Response q DC analysis tells us V out if V in is constant q Transient analysis tells us V out (t) if V in (t) changes Requires solving differential equations q Input is usually considered to be a step or ramp From 0 to V DD or vice versa DC and Transient Response Intro VLSI System Design 52
Delay Definitions q q q q q t pdr : rising propagation delay From input to rising output crossing V DD /2 t pdf : falling propagation delay From input to falling output crossing V DD /2 t pd : average propagation delay t pd = (t pdr + t pdf )/2 t r : rise time From output crossing 0.2 V DD to 0.8 V DD t f : fall time From output crossing 0.8 V DD to 0.2 V DD DC and Transient Response Intro VLSI System Design 53
Delay Definitions q t cdr : rising contamination delay From input to rising output crossing V DD /2 q t cdf : falling contamination delay From input to falling output crossing V DD /2 q t cd : average contamination delay t pd = (t cdr + t cdf )/2 DC and Transient Response Intro VLSI System Design 54
Delay Estimation q We would like to be able to easily estimate delay Not as accurate as simulation But easier to ask What if? q The step response usually looks like a 1 st order RC response with a decaying exponential. q Use RC delay models to estimate delay C = total capacitance on output node Use effective resistance R So that t pd = RC q Characterize transistors by finding their effective R Depends on average current as gate switches DC and Transient Response Intro VLSI System Design 55
RC Delay Model q Use equivalent circuits for MOS transistors Ideal switch + capacitance and ON resistance Unit nmos has resistance R, capacitance C Unit pmos has resistance 2R, capacitance C q Capacitance proportional to width q Resistance inversely proportional to width g d k s g R/k kc d s kc kc DC and Transient Response Intro VLSI System Design 56 g d k s g kc s d 2R/k kc kc
Inverter Delay Estimate q Estimate the delay of a fanout-of-1 inverter R 2C A 2 1 Y 2 1 R 2C C Y 2C C R 2C C 2C C C d = 6RC DC and Transient Response Intro VLSI System Design 57
3-input NAND Caps q Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2C 2C 2C 2C 2 2 2 2C 2C 5C 5C 5C 3C 3C 3C 3 3 3 2C 2C 9C 3C 3C 3C 3C DC and Transient Response Intro VLSI System Design 58
Elmore Delay q ON transistors look like resistors q Pullup or pulldown network modeled as RC ladder q Elmore delay of RC ladder t R C pd i to source i nodes i = RC + R + R C +... + R + R +... + R C ( ) ( ) 1 1 1 2 2 1 2 R 1 R 2 R 3 R N N N C 1 C 2 C 3 C N DC and Transient Response Intro VLSI System Design 59
Example: 3-input NAND q Estimate worst-case rising and falling delay of 3-input NAND driving h identical gates. 2 2 2 3 h copies 3 3 n 1 9C n 2 3C 3C Y 5hC tpdr ( 9 5 ) = + h RC pdf ( 3 R R R R R R )( ) ( 3 3 )( 3 3) ( 9 5 ) ( 3 3 3) ( 12 5h) RC t = C + C + + + h C + + = + DC and Transient Response Intro VLSI System Design 60
Delay Components q Delay has two parts Parasitic delay 9 or 12 RC Independent of load Effort delay 5h RC Proportional to load capacitance DC and Transient Response Intro VLSI System Design 61
Lecture 7: SPICE Simulation Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Lecture 8: Logic Effort and Combinational Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Delay in a Logic Gate q q q q q q Express delays in process-independent unit d = Delay has two components: d = f + p τ = 3RC f: effort delay = gh (a.k.a. stage effort) Again has two components g: logical effort Measures relative ability of gate to deliver current g 1 for inverter h: electrical effort = C out / C in Ratio of output to input capacitance Sometimes called fanout p: parasitic delay Represents delay of gate driving no load Set by internal parasitic capacitance d abs τ 3 ps in 65 nm process 60 ps in 0.6 µm process Logical Effort Intro VLSI System Design 64
Computing Logical Effort q DEF: Logical effort is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same output current. q Measure from delay vs. fanout plots q Or estimate by counting transistor widths A 2 1 Y A B 2 2 2 2 Y A B 4 4 1 1 Y C in = 3 g = 3/3 C in = 4 g = 4/3 C in = 5 g = 5/3 Logical Effort Intro VLSI System Design 65
Catalog of Gates q Logical effort of common gates Gate type Number of inputs 1 2 3 4 n Inverter 1 NAND 4/3 5/3 6/3 (n+2)/3 NOR 5/3 7/3 9/3 (2n+1)/3 Tristate / mux 2 2 2 2 2 XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8 Logical Effort Intro VLSI System Design 66
Catalog of Gates q Parasitic delay of common gates In multiples of p inv ( 1) Gate type Inverter 1 Number of inputs 1 2 3 4 n NAND 2 3 4 n NOR 2 3 4 n Tristate / mux 2 4 6 8 2n XOR, XNOR 4 6 8 Logical Effort Intro VLSI System Design 67
Multistage Logic Networks q Logical effort generalizes to multistage networks q Path Logical Effort q Path Electrical Effort q Path Effort G= g i H = C C out-path in-path F = f = gh i i i 10 g 1 = 1 h 1 = x/10 x g 2 = 5/3 h 2 = y/x y g 3 = 4/3 h 3 = z/y z g 4 = 1 h 4 = 20/z 20 q Can we write F = GH? Logical Effort Intro VLSI System Design 68
Paths that Branch q No! Consider paths that branch: G = 1 H = 90 / 5 = 18 5 15 90 GH = 18 h 1 = (15 +15) / 5 = 6 h 2 = 90 / 15 = 6 15 90 F = g 1 g 2 h 1 h 2 = 36 = 2GH Logical Effort Intro VLSI System Design 69
Branching Effort q Introduce branching effort Accounts for branching between stages in path b = C on path B= b i C C on path off path q Now we compute the path effort F = GBH + Note: h i = BH Logical Effort Intro VLSI System Design 70
Designing Fast Circuits = i = F + D d D P q Delay is smallest when each stage bears same effort fˆ = gh = F i i 1 N q Thus minimum delay of N stage path is 1 N D = NF + P q This is a key result of logical effort Find fastest possible delay Doesn t require calculating gate sizes Logical Effort Intro VLSI System Design 71
Gate Sizes q How wide should the gates be for least delay? fˆ = gh = g C = in i C C out in gc i fˆ out i q Working backward, apply capacitance transformation to find input capacitance of each gate given load it drives. q Check work by verifying input cap spec is met. Logical Effort Intro VLSI System Design 72
Example: 3-stage path q Select gate sizes x and y for least delay from A to B x x y 45 A 8 x y B 45 Logical Effort Intro VLSI System Design 73
Example: 3-stage path x A y x 45 8 x y B 45 Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27 Electrical Effort H = 45/8 Branching Effort B = 3 * 2 = 6 Path Effort F = GBH = 125 ˆ 3 = F = 5 Best Stage Effort Parasitic Delay P = 2 + 3 + 2 = 7 f Delay D = 3*5 + 7 = 22 = 4.4 FO4 Logical Effort Intro VLSI System Design 74
Input Order q Our parasitic delay model was too simple Calculate parasitic delay for Y falling If A arrives latest? 2τ If B arrives latest? 2.33τ 2 2 Y A B 2 2 x 6C 2C Combinational Circuits Intro VLSI System Design 75
Asymmetric Gates q Asymmetric gates favor one input over another q Ex: suppose input A of a NAND gate is most critical Use smaller transistor on A (less capacitance) Boost size of noncritical input So total resistance is same q g A = 10/9 q g B = 2 reset q g total = g A + g B = 28/9 q Asymmetric gate approaches g = 1 on critical input q But total logical effort goes up A reset A 2 2 4/3 4 Y Y Combinational Circuits Intro VLSI System Design 76
Skewed Gates q Skewed gates favor one edge over another q Ex: suppose rising output of inverter is most critical Downsize noncritical nmos transistor HI-skew inverter unskewed inverter (equal rise resistance) unskewed inverter (equal fall resistance) A 2 1/2 Y A 2 1 Y A 1 1/2 Y q Calculate logical effort by comparing to unskewed inverter with same effective resistance on that edge. g u = 2.5 / 3 = 5/6 g d = 2.5 / 1.5 = 5/3 Combinational Circuits Intro VLSI System Design 77
Lecture 9: Sequential Circuit Design Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Sequencing q Combinational logic output depends on current inputs q Sequential logic output depends on current and previous inputs Requires separating previous, current, future Called state or tokens Ex: FSM, pipeline clk clk clk clk in CL out CL CL Finite State Machine Pipeline Sequential Circuits Intro VLSI System Design 79
Timing Diagrams Contamination and Propagation Delays t pd Logic Prop. Delay A Combinational Logic Y A Y t cd t pd t cd t pcq t ccq Logic Cont. Delay Latch/Flop Clk->Q Prop. Delay Latch/Flop Clk->Q Cont. Delay D clk Flop Q clk D t setup t hold t pcq t pdq Latch D->Q Prop. Delay Q t ccq t cdq t setup t hold Latch D->Q Cont. Delay Latch/Flop Setup Time Latch/Flop Hold Time D clk Latch Q clk D Q t setup t hold t t ccq pcq t cdq t pdq Sequential Circuits Intro VLSI System Design 80
Max-Delay: Flip-Flops ( setup ) tpd Tc t + tpcq 14243 sequencing overhead clk F1 Q1 Combinational Logic D2 clk F2 T c clk t pcq t setup Q1 t pd D2 Sequential Circuits Intro VLSI System Design 81
Min-Delay: Flip-Flops Q1 t t t CL cd hold ccq clk F1 clk D2 F2 clk Q1 t ccq t cd D2 t hold Sequential Circuits Intro VLSI System Design 82
Clock Skew q We have assumed zero clock skew q Clocks really have uncertainty in arrival time Decreases maximum propagation delay Increases minimum contamination delay Decreases time borrowing Sequential Circuits Intro VLSI System Design 83
Skew: Flip-Flops ( setup skew ) tpd Tc tpcq + t + t 144424443 t t t + t cd hold sequencing overhead ccq skew clk Q1 clk F1 Q1 t pcq Combinational Logic T c t pdq D2 t setup clk F2 t skew D2 clk F1 Q1 CL clk D2 F2 t skew clk t hold Q1 t ccq D2 t cd Sequential Circuits Intro VLSI System Design 84
Summary q Flip-Flops: Very easy to use, supported by all tools q 2-Phase Transparent Latches: Lots of skew tolerance and time borrowing q Pulsed Latches: Fast, some skew tol & borrow, hold time risk Sequential Circuits Intro VLSI System Design 85
Lecture 10: Wires Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Introduction q Chips are mostly made of wires called interconnect In stick diagram, wires set size Transistors are little things under the wires Many layers of wires q Wires are as important as transistors Speed Power Noise q Alternating layers run orthogonally Wires Intro VLSI System Design 87
Wire Geometry q Pitch = w + s q Aspect ratio: AR = t/w Old processes had AR << 1 Modern processes have AR 2 Pack in many skinny wires w s l t h Wires Intro VLSI System Design 88
Lumped Element Models q Wires are a distributed system Approximate with lumped element models N segments R R/N R/N R/N R/N C C/N C/N C/N C/N R R R/2 R/2 C C/2 C/2 C L-model π-model T-model q 3-segment π-model is accurate to 3% in simulation q L-model needs 100 segments for same accuracy! q Use single segment π-model for Elmore delay Wires Intro VLSI System Design 89
Wire Resistance q ρ = resistivity (Ω*m) ρ l l R = = R W t w w q R o = sheet resistance (Ω/o) o is a dimensionless unit(!) q Count number of squares R = R o * (# of squares) l w l l w w t t 1 Rectangular Block R = R (L/W) Ω 4 Rectangular Blocks R = R (2L/2W) Ω = R (L/W) Ω Wires Intro VLSI System Design 90
Wire Capacitance q Wire has capacitance per unit length To neighbors To layers above and below q C total = C top + C bot + 2C adj s w layer n+1 h 2 C top t layer n h 1 C bot C adj layer n-1 Wires Intro VLSI System Design 91
Capacitance Formula q Capacitance of a line without neighbors can be approximated as C tot w w t = εoxl + 0.77 + 1.06 + 1.06 h h h 0.25 0.5 q This empirical formula is accurate to 6% for AR < 3.3 Intro VLSI System Design 92 Wires
Diffusion & Polysilicon q Diffusion capacitance is very high (1-2 ff/µm) Comparable to gate capacitance Diffusion also has high resistance Avoid using diffusion runners for wires! q Polysilicon has lower C but high R Use for transistor gates Occasionally for very short wires between gates Wires Intro VLSI System Design 93
Wire RC Delay q Estimate the delay of a 10x inverter driving a 2x inverter at the end of the 1 mm wire. Assume wire capacitance is 0.2 ff/µm and that a unit-sized inverter has R = 10 KΩ and C = 0.1 ff. t pd = (1000 Ω)(100 ff) + (1000 + 800 Ω)(100 + 0.6 ff) = 281 ps Wires Intro VLSI System Design 94
Repeater Design q How many repeaters should we use? q How large should each one be? q Equivalent Circuit Wire length l/n Wire Capacitance C w *l/n, Resistance R w *l/n Inverter width W (nmos = W, pmos = 2W) Gate Capacitance C *W, Resistance R/W R w ln R/W C w l/2n C w l/2n C'W Wires Intro VLSI System Design 95
Lecture 11: Adders Slides courtesy of Deming Chen Slides based on the initial set from David Harris Intro VLSI System Design
Single-Bit Addition A B Half Adder Full Adder S = A B C S = A B C out C = AgB Cout = MAJ ( A, B, C) out S A B C S A B C out S A B C C out S 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 0 0 1 0 1 0 0 1 1 1 1 0 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 C out Adders Intro VLSI System Design 97
PGK q For a full adder, define what happens to carries (in terms of A and B) Generate: C out = 1 independent of C G = A B Propagate: C out = C P = A B Kill: C out = 0 independent of C K = ~A ~B Adders Intro VLSI System Design 98
Full Adder Design I q Brute force implementation from eqns S = A B C Cout = MAJ ( A, B, C) A A B B C C A A A B C A B C MAJ S C out B C C B B B B C S C B A C C B B A A C out A A A B B Adders Intro VLSI System Design 99
Full Adder Design II q Factor S in terms of C out S = ABC + (A + B + C)(~C out ) q Critical path is usually C to C out in ripple adder A B C MINORITY C out S S C out Adders Intro VLSI System Design 100
Summary Adder architectures offer area / power / delay tradeoffs. Choose the best one for your application. Architecture Classification Logic Levels Max Fanout Tracks Carry-Ripple N-1 1 1 N Cells Carry-Skip n=4 N/4 + 5 2 1 1.25N Carry-Inc. n=4 N/4 + 2 4 1 2N Brent-Kung (L-1, 0, 0) 2log 2 N 1 2 1 2N Sklansky (0, L-1, 0) log 2 N N/2 + 1 1 0.5 Nlog 2 N Kogge-Stone (0, 0, L-1) log 2 N 2 N/2 Nlog 2 N Adders Intro VLSI System Design 101
Homework 1 q Question 2: Carry lookahead adder No shared Euler path for p-/n-network -> Diffusion needs to be broken ECE425 Intro VLSI System Design Slide 102
Homework 1 q Question 1: schematic-to-layout Transistor sizing Stick diagram ECE425 Intro VLSI System Design Slide 103
Homework 2 q Question 4: Logical, path, stage effort, delay, gate sizing ECE425 Intro VLSI System Design Slide 104
Practice Exam q Question 2: Elmore Delay model: worst case rise/fall delay ECE425 Intro VLSI System Design Slide 105
Textbook Chapters q 1.1, 1.3, 1.4.1-1.4.6, 1.5.1-1.5.5, 1.6, 1.7-1.12 q 2.1-2.5 q 4.1-4.3, 4.4.1-4.4.4; 4.5.1 q 6.1-6.2.2; 6.3.1-6.3.3; 6.4.1-6.4.2 q 8.1-8.2 q 9.1-9.2.2 q 10.1-10.3.4 q 11.1-11.2.2.8 ECE425 Intro VLSI System Design Slide 106
Textbook Exercises q 1.16(a-c) q 2.10 q 4.1, 4.3 q 6.3 q 9.7, 9.12 ECE425 Intro VLSI System Design Slide 107