About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd.

Similar documents
IBM B IBM P 8M x 8 12/11 EDO DRAM

IBM IBM M IBM B IBM P 4M x 4 12/10 DRAM

IBM IBM M IBM B IBM P 4M x 4 11/11 EDO DRAM

5V 1M 16 CMOS DRAM (fast-page mode) DQ16 DQ15 DQ14 DQ13 RAS DQ12 DQ11 DQ10 DQ9 OE WE UCAS LCAS LCAS UCAS OE A9 A8 A7 A6 A5 A4

DQ0 DQ1 DQ2 DQ3 NC WE# RAS# A0 A1 A2 A3 A4 A5. x = speed

LH NMOS 256K (256K 1) Dynamic RAM DESCRIPTION

2M x 32 Bit 5V FPM SIMM. Fast Page Mode (FPM) DRAM SIMM S51T04JD Pin 2Mx32 FPM SIMM Unbuffered, 1k Refresh, 5V. General Description.

HM514400B/BL Series HM514400C/CL Series

HB56A1636B/SB-6B/7B/8B

DQ0 DQ1 NC NC NC NC WE# RAS# A0 A1 A2 A3 A4 A5

Vcc DQ1 DQ2 DQ3 DQ4 Vcc DQ5 DQ6 DQ7 DQ8 WE# RAS# A0 A1 A2 A3 Vcc

MB81C4256A-60/-70/-80/-10 CMOS 256K x 4 BIT FAST PAGE MODE DYNAMIC RAM

DRAM MT4LC4M16R6, MT4LC4M16N3. 4 MEG x 16 EDO DRAM

VCC DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 NC NC NC WE# RAS# NC NC A0 A1 A2 A3

3.3 V 256 K 16 CMOS SRAM

5.0 V 256 K 16 CMOS SRAM

DatasheetDirect.com. Visit to get your free datasheets. This datasheet has been downloaded by

5 V 64K X 16 CMOS SRAM

AUSTIN SEMICONDUCTOR, INC. 4 MEG x 1 DRAM RAS *A10. Vcc 2-23

3.3 V 64K X 16 CMOS SRAM

LH5P832. CMOS 256K (32K 8) Pseudo-Static RAM

LH5P8128. CMOS 1M (128K 8) Pseudo-Static RAM PIN CONNECTIONS

April 2004 AS7C3256A

TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7SG02FU IN A GND

TC74HC155AP, TC74HC155AF


MR48V256A GENERAL DESCRIPTION FEATURES PRODUCT FAMILY. PEDR48V256A-06 Issue Date: Oct. 17, 2011

TC74LCX244F,TC74LCX244FW,TC74LCX244FT,TC74LCX244FK

TC74LCX08F,TC74LCX08FN,TC74LCX08FT,TC74LCX08FK

R1RW0416D Series. 4M High Speed SRAM (256-kword 16-bit) Description. Features. REJ03C Z Rev Mar

TC4028BP, TC4028BF TC4028BP/BF. TC4028B BCD-to-Decimal Decoder. Pin Assignment TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic

TC74VCX14FT, TC74VCX14FK

HM534251B Series word 4-bit Multiport CMOS Video RAM

Quad 2-input NAND gate

TC74HC373AP,TC74HC373AF,TC74HC373AFW

TC74VHCT573AF,TC74VHCT573AFW,TC74VHCT573AFT

HM6264A Series. Features. Ordering Information word 8-bit High Speed CMOS Static RAM

HN27C4096G/CC Series. Ordering Information. Features word 16-bit CMOS UV Erasable and Programmable ROM

DS K x 8 Static RAM FEATURES PIN ASSIGNMENT PIN DESCRIPTION

TC4013BP,TC4013BF,TC4013BFN

TC7WB66CFK,TC7WB66CL8X TC7WB67CFK,TC7WB67CL8X

DECODER I/O DATA CIRCUIT CONTROL CIRCUIT

P4C164 ULTRA HIGH SPEED 8K X 8 STATIC CMOS RAMS FEATURES DESCRIPTION. Full CMOS, 6T Cell. Common Data I/O

256K x 16 Static RAM CY7C1041BN. Features. Functional Description

HN27C1024HG/HCC Series

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

Obsolete Product(s) - Obsolete Product(s)

5-stage Johnson decade counter

TC74HC7292AP,TC74HC7292AF

HEF4028B. 1. General description. 2. Features. 3. Applications. 4. Ordering information. BCD to decimal decoder

The 74LVC1G11 provides a single 3-input AND gate.

SRM2264L10/12 CMOS 64K-BIT STATIC RAM. Low Supply Current Access Time 100ns/120ns 8,192 Words 8 Bits, Asynchronous DESCRIPTION

TC74HC74AP,TC74HC74AF,TC74HC74AFN

TC74HC148AP,TC74HC148AF

TC74VHC574F,TC74VHC574FW,TC74VHC574FT,TC74VHC574FK

M74HCT138TTR 3 TO 8 LINE DECODER (INVERTING)

The 74LVC1G02 provides the single 2-input NOR function.

74VHC08 Quad 2-Input AND Gate

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

I/O 8 I/O 15 A13 A 14 BHE WE CE OE BLE

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

TC74VHC573F,TC74VHC573FW,TC74VHC573FT,TC74VHC573FK

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

Maintenance/ Discontinued

74ACT825 8-Bit D-Type Flip-Flop

Obsolete Product(s) - Obsolete Product(s)

Obsolete Product(s) - Obsolete Product(s)

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74AHC259; 74AHCT259. The 74AHC259; 74AHCT259 has four modes of operation:

M74HC20TTR DUAL 4-INPUT NAND GATE

The 74LV08 provides a quad 2-input AND function.

TOSHIBA Field Effect Transistor Silicon N Channel MOS Type SSM6N15FE

74VHC574 74VHCT574 Octal D-Type Flip-Flop with 3-STATE Outputs

4-bit magnitude comparator

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

TOSHIBA Field Effect Transistor Silicon N Channel MOS Type SSM6N44FE. DC I D 100 ma Pulse I DP 200

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

1-Mbit (128K x 8) Static RAM


XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

The 74LV08 provides a quad 2-input AND function.

HN58C66 Series word 8-bit CMOS Electrically Erasable and Programmable CMOS ROM. ADE F (Z) Rev. 6.0 Apr. 12, Description.

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

2-input EXCLUSIVE-OR gate

74LVC1G125-Q100. Bus buffer/line driver; 3-state

SN54HC682, SN74HC682 8-BIT MAGNITUDE COMPARATORS

BCD to 7-segment latch/decoder/driver

74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)

IS61LV K x 16 LOW VOLTAGE CMOS STATIC RAM

TOSHIBA Field Effect Transistor Silicon N Channel MOS Type SSM3K02F

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

7-stage binary ripple counter

TOSHIBA Field-Effect Transistor Silicon N Channel MOS Type (U-MOSⅣ) SSM6N7002BFU. DC I D 200 ma Pulse I DP 800

onlinecomponents.com

TC7WP3125FK, TC7WP3125FC

TC74VHC164F,TC74VHC164FN,TC74VHC164FT,TC74VHC164FK

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop

IS61C K x 16 HIGH-SPEED CMOS STATIC RAM

Transcription:

Dear customers, About the change in the name such as "Oki Electric Industry Co. Ltd." and "OKI" in documents to OKI Semiconductor Co., Ltd. The semiconductor business of Oki Electric Industry Co., Ltd. was succeeded to OKI Semiconductor Co., Ltd. on October 1, 2008. Therefore, please accept that although the terms and marks of "Oki Electric Industry Co., Ltd.", Oki Electric, and "OKI" remain in the documents, they all have been changed to "OKI Semiconductor Co., Ltd.". It is a change of the company name, the company trademark, and the logo, etc., and NOT a content change in documents. October 1, 2008 OKI Semiconductor Co., Ltd. 550-1 Higashiasakawa-cho, Hachioji-shi, Tokyo 193-8550, Japan http://www.okisemi.com/en/

,19,30-Word -Bit DYNAMIC RAM : FAST PAGE MODE TYPE This version: January. 2001 Previous version : Aug. 2000 DESCRIPTION The is a,19,30-word -bit dynamic RAM fabricated in Oki s silicon-gate CMOS technology. The achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/double-layer metal CMOS process. The is available in a 26/2-pin plastic SOJ or 26/2-pin plastic TSOP. FEATURES,19,30-word -bit configuration Single 5V power supply, ±10% tolerance Input : TTL compatible, low input capacitance Output : TTL compatible, 3-state Refresh : 208 cycles/32ms Fast page mode, read modify write capability before refresh, hidden refresh, -only refresh capability Packages 26/2-pin 300mil plastic SOJ (SOJ26/2-P-300-1.27) (Product : -xxsj) 26/2-pin 300mil plastic TSOP (TSOPII26/2-P-300-0.80-K) (Product : -xxts-k) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) Cycle Time t RAC (Min.) Power Dissipation Operating (Max.) 50ns 25ns 13ns 13ns 90ns 550mW 60ns 30ns 15ns 15ns 110ns 95mW 70ns 35ns 20ns 20ns 130ns 0mW Standby (Max.) 5.5mW 1/15

PIN CONFIGURATION (TOP VIEW) V CC DQ1 DQ2 NC 1 2 3 5 6 26 V SS 25 DQ 2 DQ3 23 22 OE 21 A9 V CC DQ1 DQ2 NC 1 2 3 5 6 26 V SS 25 DQ 2 DQ3 23 22 OE 21 A9 A10 8 A0 9 A1 10 A2 11 A3 12 V CC 13 19 A8 18 A7 17 A6 16 A5 15 A 1 V SS A10 8 A0 9 A1 10 A2 11 A3 12 V CC 13 19 A8 18 A7 17 A6 16 A5 15 A 1 V SS 26/2-Pin Plastic SOJ 26/2-Pin Plastic TSOP (K Type) Pin Name A0 A10 DQ1 DQ OE V CC V SS NC Function Address Input Address Strobe Address Strobe Data Input/Data Output Output Enable Write Enable Power Supply (5V) Ground (0V) No Connection Note : The same power supply voltage must be provided to every V CC pin, and the same GND voltage level must be provided to every V SS pin. 2/15

BLOCK DIAGRAM Timing Generator Timing Generator A0 A10 11 Address Buffers Internal Address Counter Refresh Control Clock 11 Decoders Sense Amplifiers Write Clock Generator I/O Selector Output Buffers Input Buffers OE DQ1 DQ 11 Address Buffers 11 Decoders Word Drivers Memory Cells V CC On Chip V BB Generator V SS 3/15

ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Unit Voltage V CC Supply relative to V SS V T 0.5 to V CC +0.5 V Short Circuit Output Current I OS 50 ma Power Dissipation P D* 1 W Operating Temperature T opr 0 to 70 C Storage Temperature T stg 55 to 150 C *: Ta = 25 C RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70 C) Parameter Symbol Min. Typ. Max. Unit Power Supply Voltage V CC.5 5.0 5.5 V V SS 0 0 0 V Input High Voltage 2. V CC + 0.5 *1 V Input Low Voltage 0.5 *2 0.8 V Notes: *1. The input voltage is V CC + 1.0V when the pulse width is less than 20ns (the pulse width is with respect to the point at which V CC is applied). *2. The input voltage is V SS 1.0V when the pulse width is less than 20ns (the pulse width respect to the point at which V SS is applied). PIN CAPACITANCE (Vcc = 5V ± 10%, Ta = 25 C, f = 1 MHz) Parameter Symbol Min. Min. Unit Input Capacitance (A0 A10) C IN1 5 pf Input Capacitance (,,, OE) C IN2 7 pf Output Capacitance (DQ1 DQ) C I/O 7 pf /15

DC CHARACTERISTICS (V CC = 5V ± 10%, Ta = 0 to 70 C) Parameter Symbol Condition MSM511700 F-50 MSM511700 F-60 MSM511700 F-70 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage V OH I OH = 5.0mA 2. V CC 2. V CC 2. V CC V Output Low Voltage V OL I OL =.2mA 0 0. 0 0. 0 0. V Input Leakage Current I LI 0V V I 6.5V; All other pins not under test = 0V 10 10 10 10 10 10 µa Output Leakage Current I LO DQ disable 0V V O V CC 10 10 10 10 10 10 µa Average Power Supply Current (Operating) I CC1, cycling, = Min. 100 90 80 ma 1,2 Power Supply Current (Standby) I CC2, = 2 2 2, V CC 0.2V 1 1 1 ma 1 Average Power Supply Current I CC3 cycling, =, 100 90 80 ma 1,2 (-only Refresh) = Min. Power Supply Current (Standby) =, I CC5 =, DQ = enable 5 5 5 ma 1 Average Power Supply Current ( before Refresh) I CC6 = cycling, before 100 90 80 ma 1,2 Average Power Supply Current (Fast Page Mode) =, I CC7 cycling, t PC = Min. 80 70 60 ma 1,3 Notes: 1. I CC Max. is specified as I CC for output open condition. 2. The address can be changed once or less while =. 3. The address can be changed once or less while =. 5/15

AC CHARACTERISTICS (1/2) Parameter Symbol MSM511700 F-50 (V CC = 5V ± 10%, Ta = 0 to 70 C) Note1,2,3,11,12 MSM511700 F-60 MSM511700 F-70 Min. Max. Min. Max. Min. Max. Unit Note Random Read or Write Cycle Time 90 110 130 ns Read Modify Write Cycle Time t RWC 131 155 185 ns Fast Page Mode Cycle Time t PC 35 0 5 ns Fast Page Mode Read Modify Write Cycle Time t PRWC 76 85 100 ns Access Time from t RAC 50 60 70 ns, 5, 6 Access Time from 13 15 20 ns, 5 Access Time from Address 25 30 35 ns, 6 Access Time from Precharge t CPA 30 35 0 ns Access Time from OE 13 15 20 ns Output Low Impedance Time from to Data Output Buffer Turnoff Delay Time OE to Data Output Buffer Turn-off Delay Time t CLZ 0 0 0 ns t OFF 0 13 0 15 0 20 ns 7 t OEZ 0 13 0 15 0 20 ns 7 Transition Time t T 3 50 3 50 3 50 ns 3 Refresh Period t REF 32 32 32 ms Precharge Time 30 0 50 ns Pulse Width t 50 10,000 60 10,000 70 10,000 ns Pulse Width (Fast Page Mode) t P 50 100,000 60 100,000 70 100,000 ns Hold Time t RSH 13 15 20 ns Hold Time referenced to OE t ROH 13 15 20 ns Precharge Time (Fast Page Mode) t CP 7 10 10 ns Pulse Width t 13 10,000 15 10,000 20 10,000 ns Hold Time t CSH 50 60 70 ns to Precharge Time 5 5 5 ns Hold Time from Precharge t RHCP 30 35 0 ns to Delay Time D 17 37 20 5 20 50 ns 5 to Address Delay Time t RAD 12 25 15 30 15 35 ns 6 Address Set-up Time 0 0 0 ns 6/15

AC CHARACTERISTICS (2/2) Parameter Symbol MSM511700 F-50 (V CC = 5V ± 10%, Ta = 0 to 70 C) Note1,2,3,11,12 MSM511700 F-60 MSM511700 F-70 Min. Max. Min. Max. Min. Max. Unit Note Address Hold Time t RAH 7 10 10 ns Address Set-up Time 0 0 0 ns Address Hold Time 7 10 15 ns Address to Lead Time t RAL 25 30 35 ns Read Command Set-up Time 0 0 0 ns Read Command Hold Time H 0 0 0 ns 8 Read Command Hold Time referenced to t RRH 0 0 0 ns 8 Write Command Set-up Time t WCS 0 0 0 ns 9 Write Command Hold Time t WCH 7 10 15 ns Write Command Pulse Width 7 10 10 ns OE Command Hold Time t OEH 13 15 20 ns Write Command to Lead Time t RWL 13 15 20 ns Write Command to Lead Time t CWL 13 15 20 ns Data-in Set-up Time 0 0 0 ns 10 Data-in Hold Time 7 10 15 ns 10 OE to Data-in Delay Time t OED 13 15 20 ns to Delay Time t CWD 36 0 50 ns 9 Address to Delay Time t AWD 8 55 65 ns 9 to Delay Time t RWD 73 85 100 ns 9 Precharge Delay Time t CPWD 53 60 70 ns 9 Active Delay Time from Precharge to Set-up Time ( before ) to Hold Time ( before ) to Precharge Time ( before ) Hold Time from ( before ) C 5 5 5 ns t CSR 10 10 10 ns t CHR 10 10 10 ns t WRP 10 10 10 ns t WRH 10 10 10 ns to Set-up Time (Test Mode) t WTS 10 10 10 ns to Hold Time (Test Mode) t WTH 10 10 10 ns 7/15

Notes: 1. A start-up delay of 200µs is required after power-up, followed by a minimum of eight initialization cycles (-only refresh or before refresh) before proper device operation is achieved. 2. The AC characteristics assume t T = 5ns. 3. (Min.) and (Max.) are reference levels for measuring input timing signals. Transition times (t T ) are measured between and.. -50 is measured with a load circuit equivalent to 2TTL load and 50pF, and -60/-70 is measured with a load circuit equivalent to 2TTL load and 100pF. 5. Operation within the D (Max.) limit ensures that t RAC (Max.) can be met. D (Max.) is specified as a reference point only. If D is greater than the specified D (Max.) limit, then the access time is controlled by. 6. Operation within the t RAD (Max.) limit ensures that t RAC (Max.) can be met. t RAD (Max.) is specified as a reference point only. If t RAD is greater than the specified t RAD (Max.) limit, then the access time is controlled by. 7. t OFF (Max.) and t OEZ (Max.) define the time at which the output achieved the open circuit condition and are not referenced to output voltage levels. 8. H or t RRH must be satisfied for a read cycle. 9. t WCS, t CWD, t RWD, t AWD and t CPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If t WCS t WCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If t CWD t CWD (Min.), t RWD t RWD (Min.), t AWD t AWD (Min.) and t CPWD t CPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the, leading edges in an early write cycle, and to the leading edge in an OE control write cycle, or a read modify write cycle. 11. The test mode is initiated by performing a and before refresh cycle. This mode is latched and remains in effect until the exit cycle is generated. In a test CA9 and CA10 are not used and each DQ pin now access -bit locations. Since all DQ pins are used, a total 16 data bits can be written in parallel into the memory array. In a read cycle, if data bits are equal, the DQ pin will indicate a high level. If the data bits are not equal, the DQ pin will indicate a low level. The test mode is cleared and the memory device returned to its normal operating state by performing a -only refresh cycle or a before refresh cycle. 12. In a test mode read cycle, the value of access time parameter is delayed for 5ns for the specified value. These parameters should be specified in test mode cycle by adding the above value to the specified value in this data sheet. 8/15

TIMING CHART Read Cycle t t CSH D t RSH t t RAD t RAL t RAH Address t RRH t ROH H OE t RAC t OEZ t OFF DQ V OH V OL Open t CLZ Valid Data-out Write Cycle (Early Write) t t CSH D t RSH t t RAD t RAL t RAH Address t WCS t WCH t CWL t RWL OE DQ Valid Data-in Open 9/15

Read Modify Write Cycle t RWC t D t CSH t RSH t t RAD t RAH t CWL t RWL Address Colum t CWD t RWD t AWD t OEH OE t RAC t OED t OEZ DQ V I/OH V I/OL t CLZ Valid Data-out Valid Data-in 10/15

Fast Page Mode Read Cycle t P t PC t RHCP tcrp D t t CP t t CP t RSH t t RAD t CSH t RAL t RAH Address H H H t RRH OE t RAC t OFF t CPA t OFF t CPA t OFF DQ V OH V OL t CLZ t OEZ Valid Data-out t CLZ Valid Data-out toez t CLZ t OEZ Valid Data-out Fast Page Mode Write Cycle (Early Write) t P t PC t RHPC D t CP t CP t RSH t t t t RAD t CSH t RAL t RAH Address t RWL t CWL t CWL t CWL t WCS t WCH t WCS t WCH t WCS t WCH DQ Valid * Data-in Valid * Data-in Valid * Data-in Note: OE = 11/15

Fast Page Mode Read Modify Write Cycle t CSH t P t PRWC trsh D t t CP t t CP t t RAD t RAH tasc t CWL t CWL t RAL Address t PWD t CWD t CPWD t CWD t CPWD t CWD t CWL t RWL t RAC t AWD t CPA t AWD t AWD t ROH t CPA OE t OED t OEZ t OED t OEZ t OED t OEZ DQ V I/OH V I/OL Out In Out In Out In t CLZ t CLZ t CLZ Note: In = Valid Data-in, Out = Valid Data-out -only Refresh Cycle t C t RAH Address t OFF DQ V OH V OL Open Note:, OE = 12/15

before Refresh Cycle t C t CP t CSR C t CHR t WRP t WRH t WRP t CEZ DQ V OH V OL Open Note: OE, Address = Hidden Refresh Read Cycle t t D t RSH t CHR t RAD t RAH Address t RRH t RAL t REZ t ROH t WRP t WRH t CEZ OE t RAC t OEZ DQ V OH V OL Open tclz Valid Data-out 13/15

Hidden Refresh Write Cycle t t D t RSH t CHR t RAD t RAH Address t RAL t RWL twcs t WCH t WRP t WRH OE DQ Valid Data-in Test Mode-in Cycle t C t CP t CSR t CHR t WTS t WTH t OFF DQ Open Note: OE, Address = 1/15

NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature.. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2000 Oki Electric Industry Co., Ltd. 15/15