EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

Similar documents
INTEGRATED CIRCUITS DATA SHEET. 74HC04; 74HCT04 Hex inverter. Product specification Supersedes data of 1993 Sep Jul 23

INTEGRATED CIRCUITS DATA SHEET. 74HC00; 74HCT00 Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 26.

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at ore.hu.

The 74HC21 provide the 4-input AND function.

74HC245; 74HCT245. Octal bus tranceiver; 3-state. The 74HC245; 74HCT245 is similar to the 74HC640; 74HCT640 but has true (non-inverting) outputs.

Hex inverting Schmitt trigger with 5 V tolerant input

74HC244; 74HCT244. Octal buffer/line driver; 3-state

QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT

Quad bus transceiver; 3-state. The output enable inputs (OEA and OEB) can be used to isolate the buses.

QUICK REFERENCE DATA GND = 0 V; T amb =25 C; t r =t f = 6 ns. TYPICAL SYMBOL PARAMETER CONDITIONS 74HC00 74HCT00 UNIT

74HC273; 74HCT273. Octal D-type flip-flop with reset; positive-edge trigger

74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting

74HC393; 74HCT393. Dual 4-bit binary ripple counter

74HC1G125; 74HCT1G125

74HC General description. 2. Features. Octal D-type flip-flop; positive-edge trigger; 3-state; inverting

8-bit serial-in/parallel-out shift register

8-bit binary counter with output register; 3-state

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

8-channel analog multiplexer/demultiplexer. For operation as a digital multiplexer/demultiplexer, V EE is connected to V SS (typically ground).

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74HC4040; 74HCT stage binary ripple counter. Each counter stage is a static toggle flip-flop.

74HC373; 74HCT General description. 2. Features. Octal D-type transparent latch; 3-state

74HC164; 74HCT bit serial-in, parallel-out shift register

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

DATA SHEET. 74LVC574A Octal D-type flip-flop with 5 V tolerant inputs/outputs; positive edge-trigger; 3-state INTEGRATED CIRCUITS

74HC154; 74HCT to-16 line decoder/demultiplexer

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

74HC238; 74HCT to-8 line decoder/demultiplexer

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

DATA SHEET. 74LVC109 Dual JK flip-flop with set and reset; positive-edge trigger INTEGRATED CIRCUITS

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

The 74LV32 provides a quad 2-input OR function.

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

DATA SHEET. 74LVC16373A; 74LVCH16373A 16-bit D-type transparent latch with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

74HC238; 74HCT to-8 line decoder/demultiplexer

14-stage binary ripple counter

74ALVC bit dual supply translating transciever; 3-state. This device can be used as two 8-bit transceivers or one 16-bit transceiver.

The 74LV08 provides a quad 2-input AND function.

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

INTEGRATED CIRCUITS. PCK2002P 533 MHz PCI-X clock buffer. Product data Supersedes data of 2001 May Dec 13. Philips Semiconductors

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

74HC393; 74HCT393. Dual 4-bit binary ripple counter

DATA SHEET. 74LVC16374A; 74LVCH16374A 16-bit edge triggered D-type flip-flop with 5 V tolerant inputs/outputs; 3-state INTEGRATED CIRCUITS

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

74HC257; 74HCT257. Quad 2-input multiplexer; 3-state

DISCRETE SEMICONDUCTORS DATA SHEET. PMMT591A PNP BISS transistor. Product specification Supersedes data of 2001 Jun 11.

74AHC1G14; 74AHCT1G14

INTEGRATED CIRCUITS. 74LV00 Quad 2-input NAND gate. Product specification Supersedes data of 1998 Apr 13 IC24 Data Handbook.

DATA SHEET. BAS40 series Schottky barrier (double) diodes DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr 28.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:

74HC08; 74HCT General description. 2. Features and benefits. 3. Ordering information. Quad 2-input AND gate

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

INTEGRATED CIRCUITS. 74LV273 Octal D-type flip-flop with reset; positive-edge trigger. Product specification 1997 Apr 07 IC24 Data Handbook

74HC00; 74HCT00. The 74HC00; 74HCT00 provides a quad 2-input NAND function.

74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

2-input EXCLUSIVE-OR gate

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

74HC04; 74HCT General description. 2. Features and benefits. 3. Ordering information. Hex inverter

Octal bus transceiver; 3-state

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Dual 2-to-4 line decoder/demultiplexer

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

74HC3G14; 74HCT3G14. Triple inverting Schmitt trigger. The 74HC3G14; 74HCT3G14 is a high-speed Si-gate CMOS device.

74HC4017; 74HCT4017. Johnson decade counter with 10 decoded outputs

74HC02; 74HCT02. The 74HC02; 74HCT02 provides a quad 2-input NOR function.

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

DATA SHEET. PDTA114E series PNP resistor-equipped transistors; R1 = 10 kω, R2 = 10 kω DISCRETE SEMICONDUCTORS

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

INTEGRATED CIRCUITS. 74LV688 8-bit magnitude comparator. Product specification Supersedes data of 1997 May 15 IC24 Data Handbook.

INTEGRATED CIRCUITS DATA SHEET. 74LVC08A Quad 2-input AND gate. Product specification Supersedes data of 2002 Oct Feb 24

DATA SHEET. PH2369 NPN switching transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1999 Apr Oct 11.

74LVT125; 74LVTH General description. 2. Features. 3. Quick reference data. 3.3 V quad buffer; 3-state

The 74LVC1G11 provides a single 3-input AND gate.

INTEGRATED CIRCUITS. 74LV stage binary ripple counter. Product specification 1998 Jun 23 IC24 Data Handbook

74LV General description. 2. Features. 8-bit addressable latch

74HC08-Q100; 74HCT08-Q100

74AHC1G00; 74AHCT1G00

74HC138; 74HCT to-8 line decoder/demultiplexer; inverting

74HC86; 74HCT86. Quad 2-input EXCLUSIVE-OR gate. The 74HC86; 74HCT86 provides a 2-input EXCLUSIVE-OR function.

74HC574; 74HCT574. Octal D-type flip-flop; positive edge-trigger; 3-state

74HC32-Q100; 74HCT32-Q100

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

INTEGRATED CIRCUITS. 74LVC138A 3-to-8 line decoder/demultiplexer; inverting. Product specification 1998 Apr 28

DISCRETE SEMICONDUCTORS DATA SHEET M3D071. BAT74 Schottky barrier double diode. Product specification Supersedes data of 1996 Mar 19.

74HC20; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NAND gate

74LVU General description. 2. Features. 3. Applications. Hex inverter

3.3 V 16-bit edge-triggered D-type flip-flop with 30 Ω termination resistors; 3-state

74HC139; 74HCT139. Dual 2-to-4 line decoder/demultiplexer

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

DATA SHEET. BSS192 P-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 20

74AHC2G126; 74AHCT2G126

74AHC14-Q100; 74AHCT14-Q100

DATA SHEET. BSN304 N-channel enhancement mode vertical D-MOS transistor DISCRETE SEMICONDUCTORS. Product specification Supersedes data of 1997 Jun 17

The 74LVC1G02 provides the single 2-input NOR function.

74HC132; 74HCT132. Quad 2-input NAND Schmitt trigger

INTEGRATED CIRCUITS. For a complete data sheet, please also download:

Transcription:

EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu.

INTEGRTED CIRCUITS DT SHEET Supersedes data of 1997 ug 26 2003 Oct 30

FETURES pplications: Wave and pulse shapers stable multivibrators Monostable multivibrators. Complies with JEDEC standard no. 7 ESD protection: HBM EI/JESD22-114- exceeds 2000 V MM EI/JESD22-115- exceeds 200 V. Specified from 40 to +85 C and 40 to +125 C. DESCRIPTION The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7. The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. QUICK REFERENCE DT GND = 0 V; T amb =25 C; t r = t f = 6 ns SYMBOL PRMETER CONDITIONS Notes 1. C PD is used to determine the dynamic power dissipation (P D in µw): P D =C PD V CC 2 f i N+Σ(C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz; C L = output load capacitance in pf; V CC = supply voltage in Volts; N = total load switching outputs; Σ(C L V CC 2 f o ) = sum of the outputs. 2. For type 74HC14 the condition is V I = GND to V CC. For type 74HCT14 the condition is V I = GND to V CC 1.5 V. TYPICL t PHL /t PLH propagation delay n to ny C L = 15 pf; V CC = 5 V 12 17 ns C I input capacitance 3.5 3.5 pf C PD power dissipation capacitance per gate notes 1 and 2 7 8 pf HC HCT UNIT 2003 Oct 30 2

FUNCTION TBLE INPUT n L H OUTPUT ny H L Note 1. H = HIGH voltage level; L = LOW voltage level. ORDERING INFORMTION PCKGE TYPE NUMBER TEMPERTURE RNGE PINS PCKGE MTERIL CODE 74HC14D 40 to +125 C 14 SO14 plastic SOT108-1 74HCT14D 40 to +125 C 14 SO14 plastic SOT108-1 74HC14DB 40 to +125 C 14 SSOP14 plastic SOT337-1 74HCT14DB 40 to +125 C 14 SSOP14 plastic SOT337-1 74HC14N 40 to +125 C 14 DIP14 plastic SOT27-1 74HCT14N 40 to +125 C 14 DIP14 plastic SOT27-1 74HC14PW 40 to +125 C 14 TSSOP14 plastic SOT402-1 74HCT14PW 40 to +125 C 14 TSSOP14 plastic SOT402-1 74HC14BQ 40 to +125 C 14 DHVQFN14 plastic SOT762-1 74HCT14BQ 40 to +125 C 14 DHVQFN14 plastic SOT762-1 PINNING PIN SYMBOL DESCRIPTION 1 1 data input 2 1Y data output 3 2 data input 4 2Y data output 5 3 data input 6 3Y data output 7 GND ground (0 V) 8 4Y data output 9 4 data input 10 5Y data output 11 5 data input 12 6Y data output 13 6 data input 14 V CC supply voltage 2003 Oct 30 3

1 1 14 V CC 1 V CC 1 14 1Y 2 13 6 1Y 2 13 6 2 3 12 6Y 2 3 12 6Y 2Y 3 4 5 14 11 10 5 5Y 2Y 4 GND (1) 11 5 3Y 6 9 4 3 5 10 5Y GND 7 8 4Y 3Y 6 9 4 MN839 7 8 Top view GND 4Y MBL760 (1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input. Fig.1 Pin configuration. Fig.2 Pin configuration DHVQFN14. 1 1Y 1 2 1 2 2 2Y 3 4 3 4 3 3Y 5 6 5 6 4 4Y 9 8 9 8 5 5Y 11 10 11 10 13 6 6Y 12 MN840 13 12 MN841 Fig.3 Logic symbol. Fig.4 IEC logic symbol. 2003 Oct 30 4

1 1Y 1 2 2 2Y 3 4 5 3 3Y 6 9 4 4Y 8 11 5 5Y 10 Y MN843 6 6Y 13 12 MN842 Fig.5 Functional diagram. Fig.6 Logic diagram (one Schmitt trigger). 2003 Oct 30 5

RECOMMENDED OPERTING CONDITIONS SYMBOL PRMETER CONDITIONS 74HC14 74HCT14 MIN. TYP. MX. MIN. TYP. MX. V CC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V V I input voltage 0 V CC 0 V CC V V O output voltage 0 V CC 0 V CC V T amb operating ambient temperature see DC and C characteristics per device 40 +25 +85 40 +25 +85 C 40 +125 40 +125 C UNIT LIMITING VLUES In accordance with the bsolute Maximum System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL PRMETER CONDITIONS MIN. MX. UNIT V CC supply voltage 0.5 +7 V I IK input diode current V I < 0.5 V or V I >V CC + 0.5 V ±20 m I OK output diode current V O < 0.5 V or V O >V CC + 0.5 V ±20 m I O Notes output source or sink current 0.5V<V O <V CC + 0.5 V ±25 m I CC ;I GND V CC or GND current 50 m T stg storage temperature 65 +150 C P tot power dissipation T amb = 40 to +125 C DIP14 packages; note 1 750 mw Other packages; note 2 500 mw 1. For DIP14 packages: above 70 C the value of P D derates linearly with 12 mw/k. 2. For SO14 packages: above 70 C the value of P D derates linearly with 8 mw/k. For (T)SSOP14 packages: above 60 C the value of P D derates linearly with 5.5 mw/k. For DHVQFN14 packages: above 60 C the value of P D derates linearly with 4.5 mw/k. 2003 Oct 30 6

DC CHRCTERISTICS Type 74HC14 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL T amb =25 C V OH V OL I LI I CC PRMETER HIGH-level output voltage LOW-level output voltage input leakage current T amb = 40 to +85 C V OH V OL I LI I CC quiescent supply current HIGH-level output voltage LOW-level output voltage input leakage current quiescent supply current TEST CONDITIONS OTHER V CC (V) MIN. TYP. (1) MX. UNIT V I =V IH or V IL I O = 20 µ 2.0 1.9 2.0 V I O = 20 µ 4.5 4.4 4.5 V I O = 20 µ 6.0 5.9 6.0 V I O = 4.0 m 4.5 3.98 4.32 V I O = 5.2 m 6.0 5.48 5.81 V V I =V IH or V IL I O =20µ 2.0 0 0.1 V I O =20µ 4.5 0 0.1 V I O =20µ 6.0 0 0.1 V I O = 4.0 m 4.5 0.15 0.26 V I O = 5.2 m 6.0 0.16 0.26 V V I =V CC or GND 6.0 0.1 µ V I =V CC or GND; I O = 0 6.0 2.0 µ V I =V IH or V IL I O = 20 µ 2.0 1.9 V I O = 20 µ 4.5 4.4 V I O = 20 µ 6.0 5.9 V I O = 4.0 m 4.5 3.84 V I O = 5.2 m 6.0 5.34 V V I =V IH or V IL I O =20µ 2.0 0.1 V I O =20µ 4.5 0.1 V I O =20µ 6.0 0.1 V I O = 4.0 m 4.5 0.33 V I O = 5.2 m 6.0 0.33 V V I =V CC or GND 6.0 1.0 µ V I =V CC or GND; I O = 0 6.0 20 µ 2003 Oct 30 7

T amb = 40 to +125 C V OH V OL I LI SYMBOL I CC Note PRMETER HIGH-level output voltage LOW-level output voltage input leakage current quiescent supply current 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS OTHER V CC (V) MIN. TYP. (1) MX. UNIT V I =V IH or V IL I O = 20 µ 2.0 1.9 V I O = 20 µ 4.5 4.4 V I O = 20 µ 6.0 5.9 V I O = 4.0 m 4.5 3.7 V I O = 5.2 m 6.0 5.2 V V I =V IH or V IL I O =20µ 2.0 0.1 V I O =20µ 4.5 0.1 V I O =20µ 6.0 0.1 V I O = 4.0 m 4.5 0.4 V I O = 5.2 m 6.0 0.4 V V I =V CC or GND 6.0 1.0 µ V I =V CC or GND; I O = 0 6.0 40 µ 2003 Oct 30 8

Type 74HCT14 t recommended operating conditions; voltages are referenced to GND (ground = 0 V). Note SYMBOL T amb =25 C V OH V OL PRMETER HIGH-level output voltage LOW-level output voltage 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS OTHER 2003 Oct 30 9 V CC (V) MIN. TYP. (1) MX. UNIT V I =V IH or V IL I O = 20 µ 4.5 4.4 4.5 V I O = 4.0 m 4.5 3.98 4.32 V V I =V IH or V IL I O =20µ 4.5 0 0.1 V I O = 4.0 m 4.5 0.15 0.26 V I LI input leakage current V I =V CC or GND 5.5 0.1 µ I CC I CC T amb = 40 to +85 C V OH V OL quiescent supply current additional supply current per input HIGH-level output voltage LOW-level output voltage V I =V CC or GND; I O =0 5.5 2.0 µ V I =V CC 2.1 V; I O = 0 4.5 to 5.5 30 108 µ V I =V IH or V IL I O = 20 µ 4.5 4.4 V I O = 4.0 m 4.5 3.84 V V I =V IH or V IL I O =20µ 4.5 0.1 V I O = 4.0 m 4.5 0.33 V I LI input leakage current V I =V CC or GND 5.5 1.0 µ I CC I CC T amb = 40 to +125 C V OH V OL quiescent supply current additional supply current per input HIGH-level output voltage LOW-level output voltage V I =V CC or GND; I O =0 5.5 20 µ V I =V CC 2.1 V; I O = 0 4.5 to 5.5 135 µ V I =V IH or V IL I O = 20 µ 4.5 4.4 V I O = 4.0 m 4.5 3.7 V V I =V IH or V IL I O =20µ 4.5 0.1 V I O = 4.0 m 4.5 0.4 V I LI input leakage current V I =V CC or GND 5.5 1.0 µ I CC I CC quiescent supply current additional supply current per input V I =V CC or GND; I O =0 5.5 40 µ V I =V CC 2.1 V; I O = 0 4.5 to 5.5 147 µ

TRNSFER CHRCTERISTICS Type 74HC t recommended operating conditions; voltages are referenced to GND (ground = 0 V). SYMBOL T amb =25 C; note 1 Note PRMETER 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT V T+ positive-going threshold Figs 7 and 8 2.0 0.7 1.18 1.5 V 4.5 1.7 2.38 3.15 V 6.0 2.1 3.14 4.2 V V T negative-going threshold Figs 7 and 8 2.0 0.3 0.52 0.90 V 4.5 0.9 1.40 2.00 V 6.0 1.2 1.89 2.60 V V H hysteresis (V T+ V T ) Figs 7 and 8 2.0 0.2 0.66 1.0 V T amb = 40 to +85 C 4.5 0.4 0.98 1.4 V 6.0 0.6 1.25 1.6 V V T+ positive-going threshold Figs 7 and 8 2.0 0.7 1.5 V 4.5 1.7 3.15 V 6.0 2.1 4.2 V V T negative-going threshold Figs 7 and 8 2.0 0.3 0.90 V 4.5 0.90 2.00 V 6.0 1.20 2.60 V V H hysteresis (V T+ V T ) Figs 7 and 8 2.0 0.2 1.0 V T amb = 40 to +125 C 4.5 0.4 1.4 V 6.0 0.6 1.6 V V T+ positive-going threshold Figs 7 and 8 2.0 0.7 1.5 V 4.5 1.7 3.15 V 6.0 2.1 4.2 V V T negative-going threshold Figs 7 and 8 2.0 0.30 0.90 V 4.5 0.90 2.00 V 6.0 1.2 2.60 V V H hysteresis (V T+ V T ) Figs 7 and 8 2.0 0.2 1.0 V 4.5 0.4 1.4 V 6.0 0.6 1.6 V 2003 Oct 30 10

Family 74HCT t recommended operating conditions: voltages are referenced to GND (ground = 0 V) Note SYMBOL T amb =25 C; note 1 PRMETER 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT V T+ positive-going threshold Figs 7 and 8 4.5 1.2 1.41 1.9 V 5.5 1.4 1.59 2.1 V V T negative-going threshold Figs 7 and 8 4.5 0.5 0.85 1.2 V 5.5 0.6 0.99 1.4 V V H hysteresis (V T+ V T ) Figs 7 and 8 4.5 0.4 0.56 V T amb = 40 to +85 C 5.5 0.4 0.60 V V T+ positive-going threshold Figs 7 and 8 4.5 1.2 1.9 V 5.5 1.4 2.1 V V T negative-going threshold Figs 7 and 8 4.5 0.5 1.2 V 5.5 0.6 1.4 V V H hysteresis (V T+ V T ) Figs 7 and 8 4.5 0.4 V T amb = 40 to +125 C 5.5 0.4 V V T+ positive-going threshold Figs 7 and 8 4.5 1.2 1.9 V 5.5 1.4 2.1 V V T negative-going threshold Figs 7 and 8 4.5 0.5 1.2 V 5.5 0.6 1.4 V V H hysteresis (V T+ V T ) Figs 7 and 8 4.5 0.4 V 5.5 0.4 V 2003 Oct 30 11

C CHRCTERISTICS Type 74HC GND = 0 V; t f = t f = 6 ns; C L =50pF SYMBOL T amb =25 C; note 1 Note PRMETER 1. ll typical values are measured at T amb =25 C. TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT t PHL /t PLH propagation delay n to ny see Fig.9 2.0 41 125 ns 4.5 15 25 ns 6.0 12 21 ns t THL /t TLH output transition time see Fig.9 2.0 19 75 ns T amb = 40 to +85 C 4.5 7 15 ns 6.0 6 13 ns t PHL /t PLH propagation delay n to ny see Fig.9 2.0 155 ns 4.5 31 ns 6.0 26 ns t THL /t TLH output transition time see Fig.9 2.0 95 ns T amb = 40 to +125 C 4.5 19 ns 6.0 15 ns t PHL /t PLH propagation delay n to ny see Fig.9 2.0 190 ns 4.5 38 ns 6.0 32 ns t THL /t TLH output transition time see Fig.9 2.0 110 ns 4.5 22 ns 6.0 19 ns 2003 Oct 30 12

Type 74HCT GND = 0 V; t r =t f = 6 ns; C L =50pF SYMBOL PRMETER TEST CONDITIONS WVEFORMS V CC (V) MIN. TYP. MX. UNIT T amb =25 C; note 1 t PHL /t PLH propagation delay n to ny see Fig.9 4.5 20 34 ns t THL /t TLH output transition time see Fig.9 4.5 7 15 ns T amb = 40 to +85 C t PHL /t PLH propagation delay n to ny see Fig.9 4.5 43 ns t THL /t TLH output transition time see Fig.9 4.5 19 ns T amb = 40 to +125 C t PHL /t PLH propagation delay n to ny see Fig.9 4.5 51 ns t THL /t TLH output transition time see Fig.9 4.5 22 ns Note 1. ll typical values are measured at T amb =25 C. TRNSFER CHRCTERISTIC WVEFORMS V O V T+ V I V H V T V T VH V T+ MN844 MN845 V I V O V T+ and V T are between limits of 20% and 70%. Fig.7 Transfer characteristic. Fig.8 The definitions of V T+,V T and V H. 2003 Oct 30 13

50 I CC (µ) MN846 1.0 I CC (m) MN847 40 0.8 30 0.6 20 0.4 10 0.2 0 0 0.4 0.8 1.2 1.6 2.0 V I (V) 0 0 1 2 3 4 5 V I (V) V CC =2V. Fig.9 Typical 74HC14 transfer characteristics. V CC = 4.5 V. Fig.10 Typical 74HC14 transfer characteristics. 1.0 I CC (m) MN848 1.5 I CC (m) MN849 0.8 1.2 0.6 0.9 0.4 0.6 0.2 0.3 0 0 1.2 2.4 3.6 4.8 6.0 V I (V) 0 0 1 2 3 4 5 V I (V) V CC =6V. Fig.11 Typical 74HC14 transfer characteristics. V CC = 4.5 V. Fig.12 Typical 74HCT14 transfer characteristics. 2003 Oct 30 14

1.8 handbook, I halfpage CC (m) 1.5 MN850 1.2 0.9 0.6 0.3 0 0 1 2 3 4 5 6 V I (V) V CC = 5.5 V. Fig.13 Typical 74HCT14 transfer characteristics. C WVEFORMS V I n input GND V M V M t PHL t PLH V OH ny output V OL 90% V M V M 10% t THL t TLH MN722 74HC14: V M = 50%; V I = GND to V CC. 74HCT14: V M = 1.3 V; V I = GND to 3.0 V. Fig.14 The input (n) to output (ny) propagation delays and output transitions times. 2003 Oct 30 15

handbook, full pagewidth PULSE GENERTOR V I R T V CC D.U.T. V O C L = 50 pf S1 R L = 1 kω V CC open GND MN742 TEST t PLH /t PHL t PLZ /t PZL t PHZ /t PZH S1 open V CC GND Definitions for test circuit: R L = Load resistor. C L = load capacitance including jig and probe capacitance. R T = termination resistance should be equal to the output impedance Z o of the pulse generator. Fig.15 Load circuitry for switching times. 2003 Oct 30 16

PPLICTION INFORMTION The slow input rise and fall times cause additional power dissipation. This can be calculated using the following formula: P ad =f i (t r I CC(V) +t f I CC(V) ) V CC. Where: P ad = additional power dissipation (µw); f i = input frequency (MHz); t r = input rise time (µs); 10% to 90%; t f = input fall time (µs); 10% to 90%; I CC(V) = average additional supply current (µ). I CC(V) differs with positive or negative input transitions, as shown in Figs 16 and 17. For 74HC/HCT14 used in a relaxation oscillator circuit, see Fig.18. Note to application information ll values given are typical unless otherwise specified. 400 I CC(V) (µ) 300 200 100 positive - going edge MN852 negative - going edge 0 0 2 4 V 6 CC (V) Linear change of V I between 0.1V CC to 0.9V CC Fig.16 verage I CC for 74HC14 Schmitt trigger devices. 400 I CC(V) (µ) MN853 300 positive - going egde edge R 200 C 100 negative - going egde edge MN854 0 0 2 4 V 6 CC (V) Linear change of V I between 0.1V CC to 0.9V CC. Fig.17 verage I CC for HCT Schmitt trigger devices. 1 1 74HC14 : f = -- ------------------ T 0.8 RC 1 1 74HCT14 : f = -- --------------------- T 0.67 RC Fig.18 Relaxation oscillator using 74HC/HCT14. 2003 Oct 30 17

PCKGE OUTLINES SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E X c y H E v M Z 14 8 Q pin 1 index 2 1 ( ) 3 θ L p 1 7 L e b p w M detail X 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note max. 1.75 1 2 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 0.25 0.10 0.069 0.010 0.004 1.45 1.25 0.057 0.049 0.25 0.01 0.49 0.36 0.019 0.014 0.25 0.19 0.0100 0.0075 8.75 8.55 0.35 0.34 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 4.0 3.8 0.16 0.15 1.27 0.05 6.2 5.8 0.244 0.228 1.05 0.041 1.0 0.4 0.039 0.016 0.7 0.6 0.028 0.024 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.7 0.3 o 8 o 0.028 0 0.012 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT108-1 076E06 MS-012 99-12-27 03-02-19 2003 Oct 30 18

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1 D M E seating plane 2 L 1 Z 14 e b b 1 8 w M c (e ) 1 M H pin 1 index E 1 7 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 1 2 (1) (1) min. max. b b 1 c D E e e 1 L M E M H 4.2 0.51 3.2 0.17 0.02 0.13 1.73 1.13 0.068 0.044 0.53 0.38 0.021 0.015 0.36 0.23 0.014 0.009 19.50 18.55 0.77 0.73 6.48 6.20 0.26 0.24 2.54 7.62 0.1 0.3 3.60 3.05 0.14 0.12 8.25 7.80 0.32 0.31 10.0 8.3 0.39 0.33 w 0.254 0.01 (1) Z max. 2.2 0.087 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT27-1 050G04 MO-001 SC-501-14 99-12-27 03-02-13 2003 Oct 30 19

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 D E X c y H E v M Z 14 8 pin 1 index 2 1 Q ( ) 3 θ 1 7 e b p w M L detail X L p 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 2 3 b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT402-1 MO-153 EUROPEN PROJECTION ISSUE DTE 99-12-27 03-02-18 2003 Oct 30 20

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm SOT762-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 6 v M w M C C B y 1 C C y L 1 7 E h e 14 8 13 9 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) E h e e1 L v w y y 1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT762-1 - - - MO-241 - - - EUROPEN PROJECTION ISSUE DTE 02-10-17 03-01-27 2003 Oct 30 21

DT SHEET STTUS LEVEL Notes DT SHEET STTUS (1) PRODUCT STTUS (2)(3) DEFINITION I Objective data Development This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data Production This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the bsolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. pplication information pplications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status Production ), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2003 Oct 30 22

a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Koninklijke Philips Electronics N.V. 2003 SC75 ll rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 613508/03/pp23 Date of release: 2003 Oct 30 Document order number: 9397 750 10497