74LVC541A-Q100. Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

Similar documents
74LVC07A-Q100. Hex buffer with open-drain outputs

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state

74HC4050-Q100. Hex non-inverting HIGH-to-LOW level shifter

74LVC125A. 1. General description. 2. Features and benefits. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

74HC30-Q100; 74HCT30-Q100

Hex inverter with open-drain outputs

74LVC1G125-Q100. Bus buffer/line driver; 3-state

74AHC541-Q100; 74AHCT541-Q100

Temperature range Name Description Version XC7SET32GW 40 C to +125 C TSSOP5 plastic thin shrink small outline package; 5 leads; body width 1.

74AUP1G04-Q100. The 74AUP1G04-Q100 provides the single inverting buffer.

2-input EXCLUSIVE-OR gate

74VHC08; 74VHCT08. The 74VHC08; 74VHCT08 provide the quad 2-input AND function.

The 74LVC10A provides three 3-input NAND functions.

74LVC273-Q100. Octal D-type flip-flop with reset; positive-edge trigger

Dual buffer/line driver; 3-state

74LVC14A-Q100. Hex inverting Schmitt trigger with 5 V tolerant input

2-input AND gate with open-drain output. The 74AHC1G09 is a high-speed Si-gate CMOS device.

74LVC General description. 2. Features and benefits. Ordering information. Octal D-type flip-flop with data enable; positive-edge trigger

74LVC General description. 2. Features and benefits. 3. Ordering information. Triple 3-input OR gate. The 74LVC332 is a triple 3-input OR gate.

74LVC1G79-Q100. Single D-type flip-flop; positive-edge trigger. The 74LVC1G79_Q100 provides a single positive-edge triggered D-type flip-flop.

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

74HC1G32-Q100; 74HCT1G32-Q100

74HC1G02-Q100; 74HCT1G02-Q100

The 74LV08 provides a quad 2-input AND function.

74HC2G08-Q100; 74HCT2G08-Q100

74HC32-Q100; 74HCT32-Q100

Octal bus transceiver; 3-state

Bus buffer/line driver; 3-state

74AHC30-Q100; 74AHCT30-Q100

Octal buffer/line driver; 3-state

Dual buffer/line driver; 3-state

The 74AXP1G04 is a single inverting buffer.

74HC2G16; 74HCT2G16. The 74HC2G16; 74HCT2G16 is a high-speed Si-gate CMOS device. The 74HC2G16; 74HCT2G16 provides two buffers.

74LVC823A-Q General description. 2. Features and benefits

74AHC541; 74AHCT541. Octal buffer/line driver; 3-state. The 74AHC541; 74AHCT541 is a high-speed Si-gate CMOS device.

74HC541; 74HCT541. Octal buffer/line driver; 3-state

The 74AUP2G34 provides two low-power, low-voltage buffers.

74LVC1G18 1-of-2 non-inverting demultiplexer with 3-state deselected output Rev. 3 2 December 2016 Product data sheet 1. General description

74HC366; 74HCT366. Hex buffer/line driver; 3-state; inverting

74HC153-Q100; 74HCT153-Q100

Single D-type flip-flop; positive-edge trigger. The 74LVC1G79 provides a single positive-edge triggered D-type flip-flop.

74HC08-Q100; 74HCT08-Q100

74ALVC04. 1 General description. 2 Features and benefits. 3 Ordering information. Hex inverter

74AVC16374-Q General description. 2. Features and benefits. 16-bit edge triggered D-type flip-flop; 3.6 V tolerant; 3-state

74HC368; 74HCT368. Hex buffer/line driver; 3-state; inverting

74AHC244; 74AHCT244. Octal buffer/line driver; 3-state. The 74AHC244; 74AHCT244 is a high-speed Si-gate CMOS device.

74HC03-Q100; 74HCT03-Q100

74AHC02; 74AHCT02. The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

The 74LV08 provides a quad 2-input AND function.

74AHC14-Q100; 74AHCT14-Q100

74LVC126A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad buffer/line driver with 5 V tolerant input/outputs; 3-state

Low-power configurable multiple function gate

74HC1G02; 74HCT1G02. The standard output currents are half those of the 74HC02 and 74HCT02.

Octal bus transceiver; 3-state

Single supply translating buffer/line driver; 3-state

74AHC86; 74AHCT86. Quad 2-input EXCLUSIVE-OR gate. The 74AHC86; 74AHCT86 provides a 2-input exclusive-or function.

74HC1G86; 74HCT1G86. 2-input EXCLUSIVE-OR gate. The standard output currents are half those of the 74HC/HCT86.

Dual buffer/line driver; 3-state

Low-power triple buffer with open-drain output

Low-power configurable multiple function gate

The 74LV32 provides a quad 2-input OR function.

Dual supply buffer/line driver; 3-state

74HC253; 74HCT253. Dual 4-input multiplexer; 3-state

74AHC2G126; 74AHCT2G126

XC7SET General description. 2. Features. 3. Applications. Ordering information. Inverting Schmitt trigger

74HC1G08; 74HCT1G08. 1 General description. 2 Features. 3 Ordering information. 2-input AND gate

74HC151-Q100; 74HCT151-Q100

74HC365; 74HCT365. Hex buffer/line driver; 3-state

2-input single supply translating NAND gate

74HC2G125; 74HCT2G125

The 74LVC00A provides four 2-input NAND gates.

74AHC2G241; 74AHCT2G241

74HC2G08; 74HCT2G General description. 2. Features and benefits. 3. Ordering information. Dual 2-input AND gate

Low-power 3-input EXCLUSIVE-OR gate. The 74AUP1G386 provides a single 3-input EXCLUSIVE-OR gate.

74LVC32A. 1. General description. 2. Features and benefits. 3. Ordering information. Quad 2-input OR gate

74HC373-Q100; 74HCT373-Q100

7-stage binary ripple counter

74HC540; 74HCT540. Octal buffer/line driver; 3-state; inverting

74AHC1G125; 74AHCT1G125

74HC1GU04GV. 1. General description. 2. Features. 3. Ordering information. Marking. 5. Functional diagram. Inverter

The 74LVC1G02 provides the single 2-input NOR function.

Low-power dual Schmitt trigger inverter

74AHC14; 74AHCT14. Hex inverting Schmitt trigger

74HC30; 74HCT General description. 2. Features and benefits. 3. Ordering information. 8-input NAND gate

Low-power buffer/line driver; 3-state

74AHC125; 74AHCT125. Quad buffer/line driver; 3-state

The 74ABT125 high-performance BiCMOS device combines low static and dynamic power dissipation with high speed and high output drive.

74HC107-Q100; 74HCT107-Q100

74AHC1G126; 74AHCT1G126

74HC1G125; 74HCT1G125

74HC126; 74HCT126. Quad buffer/line driver; 3-state

74HC4002; 74HCT General description. 2. Features and benefits. 3. Ordering information. Dual 4-input NOR gate

74AHC1G00; 74AHCT1G00

74AVC20T245-Q General description. 2. Features and benefits

74HC132-Q100; 74HCT132-Q100

Low-power buffer and inverter. The 74AUP2G3404 is a single buffer and single inverter.

74HC2G34; 74HCT2G34. The 74HC2G34; 74HCT2G34 is a high-speed Si-gate CMOS device. The 74HC2G34; 74HCT2G34 provides two buffers.

Low-power buffer with voltage-level translator

Transcription:

Octal buffer/line driver with 5 V tolerant inputs/outputs; 3-state Rev. 2 4 March 2013 Product data sheet 1. General description The is an octal non-inverting buffer/line driver with 5 V tolerant inputs and outputs. The output enable inputs OE1 and OE2 control the 3-state outputs. This device is fully specified for partial power-down applications using I OFF. The I OFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be applied to the outputs. These features allow the use of these devices as translators in mixed 3.3 V and 5 V applications. This product has been qualified to the utomotive Electronics Council (EC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits utomotive product qualification in accordance with EC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C 5 V tolerant inputs for interfacing with 5 V logic Wide supply voltage range from 1.2 V to 3.6 V CMOS low power consumption Direct interface with TTL levels Complies with JEDEC standard: JESD8-7 (1.65 V to 1.95 V) JESD8-5 (2.3 V to 2.7 V) JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-114F exceeds 2000 V MM JESD22-115- exceeds 200 V (C = 200 pf, R = 0 )

3. Ordering information Table 1. Type number Ordering information Package 4. Functional diagram Temperature range Name Description Version 74LVC541D-Q100 40 C to +125 C SO20 plastic small outline package; 20 leads; body width 7.5 mm 74LVC541PW-Q100 40 C to +125 C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm 74LVC541BQ-Q100 40 C to +125 C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 4.5 0.85 mm SOT163-1 SOT360-1 SOT764-1 2 0 Y0 18 3 1 Y1 17 1 19 & EN 4 2 Y2 16 2 3 18 17 5 3 Y3 15 4 5 16 15 6 4 Y4 14 6 7 14 13 7 5 Y5 13 8 12 9 11 8 6 Y6 12 mna898 9 7 Y7 11 1 19 OE1 OE2 mna900 Fig 1. IEC logic symbol Fig 2. Functional diagram Product data sheet Rev. 2 4 March 2013 2 of 16

5. Pinning information 5.1 Pinning (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 3. Pin configuration for SO20 and TSSOP20 Fig 4. Pin configuration for DHVQFN20 5.2 Pin description Table 2. Pin description Symbol Pin Description OE1 1 output enable input (active LOW) [0:7] 2, 3, 4, 5, 6, 7, 8, 9 data input GND 10 ground (0 V) Y[0:7] 18, 17, 16, 15, 14, 13, 12, 11 bus output OE2 19 output enable input (active LOW) V CC 20 supply voltage Product data sheet Rev. 2 4 March 2013 3 of 16

6. Functional description Table 3. Functional table [1] Input Output OE1 OE2 n Yn L L L L L L H H X H X Z H X X Z [1] H = HIGH voltage level L = LOW voltage level X = don t care Z = high-impedance OFF-state 7. Limiting values Table 4. Limiting values In accordance with the bsolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit V CC supply voltage 0.5 +6.5 V I IK input clamping current V I < 0 V 50 - m V I input voltage [1] 0.5 +5.5 V I OK output clamping current V O > V CC or V O < 0 V - 50 m V O output voltage output HIGH or LOW state [2] 0.5 V CC + 0.5 V output 3-state or power-down [2] 0.5 +6.5 V I O output current V O = 0 V to V CC - 50 m I CC supply current - 100 m I GND ground current 100 - m T stg storage temperature 60 +150 C P tot total power dissipation T amb = 40 C to +125 C [3] - 500 mw [1] The minimum input voltage ratings may be exceeded if the input current ratings are observed. [2] The output voltage ratings may be exceeded if the output current ratings are observed. [3] For SO20 packages: above 70 C the value of P tot derates linearly with 8 mw/k. For TSSOP20 packages: above 60 C the value of P tot derates linearly with 5.5 mw/k. For DHVQFN20 packages: above 60 C the value of P tot derates linearly with 4.5 mw/k. Product data sheet Rev. 2 4 March 2013 4 of 16

8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V CC supply voltage 1.65-3.6 V 9. Static characteristics functional 1.2 - - V V I input voltage 0-5.5 V V O output voltage output HIGH or LOW state 0 - V CC V output 3-state 0-5.5 V T amb ambient temperature 40 - +125 C t/v input transition rise and fall rate V CC = 2.3 V to 2.7 V 0-20 ns/v V CC = 2.7 V to 3.6 V 0-10 ns/v Table 6. Static characteristics t recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max V IH HIGH-level V CC = 1.2 V 1.08 - - 1.08 - V input voltage V CC = 1.65 V to 1.95 V 0.65 V CC - - 0.65 V CC - V V CC = 2.3 V to 2.7 V 1.7 - - 1.7 - V V CC = 2.7 V to 3.6 V 2.0 - - 2.0 - V V IL LOW-level V CC = 1.2 V - - 0.12-0.12 V input voltage V CC = 1.65 V to 1.95 V - - 0.35 V CC - 0.35 V CC V V CC = 2.3 V to 2.7 V - - 0.7-0.7 V V CC = 2.7 V to 3.6 V - - 0.8-0.8 V V OH HIGH-level V I =V IH or V IL output I O = 100 ; voltage V CC = 1.65 V to 3.6 V V CC 0.2 - - V CC 0.3 - V I O = 4 m; V CC = 1.65 V 1.2 - - 1.05 - V I O = 8 m; V CC = 2.3 V 1.8 - - 1.65 - V I O = 12 m; V CC = 2.7 V 2.2 - - 2.05 - V I O = 18 m; V CC = 3.0 V 2.4 - - 2.25 - V I O = 24 m; V CC = 3.0 V 2.2 - - 2.0 - V V OL LOW-level output voltage V I =V IH or V IL I O =100; - - 0.2-0.3 V V CC = 1.65 V to 3.6 V I O =4m; V CC = 1.65 V - - 0.45-0.65 V I O =8m; V CC = 2.3 V - - 0.6-0.8 V I O =12m; V CC = 2.7 V - - 0.4-0.6 V I O =24m; V CC = 3.0 V - - 0.55-0.8 V Product data sheet Rev. 2 4 March 2013 5 of 16

Table 6. Static characteristics continued t recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max - 0.1 5-20 I I I OZ I OFF I CC I CC C I input leakage current OFF-state output current power-off leakage current supply current additional supply current input capacitance V I = 5.5 V or GND; V CC =3.6V [1] ll typical values are measured at V CC = 3.3 V (unless stated otherwise) and T amb =25C. 10. Dynamic characteristics V I =V IH or V IL ; V O =5.5VorGND; V CC =3.6V - 0.1 5-20 V I or V O =5.5V; V CC = 0.0 V - 0.1 10-20 V I =V CC or GND; I O =0; V CC =3.6V per input pin; V I =V CC 0.6 V; I O =0; V CC = 2.7 V to 3.6 V - 0.1 10-40 - 5 500-5000 - 5.0 - - - pf Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max t pd propagation n to Yn; see Figure 5 [2] delay V CC = 1.2 V - 14.0 - - - ns V CC = 1.65 V to 1.95 V 1.5 6.5 13.8 1.5 16.0 ns V CC = 2.3 V to 2.7 V 1.0 3.5 6.8 1.0 7.9 ns V CC = 2.7 V 1.5 3.5 5.6 1.5 7.0 ns V CC = 3.0 V to 3.6 V 1.0 2.9 5.1 1.0 6.5 ns t en enable time OEn toyn; see Figure 6 [2] V CC = 1.2 V - 20.0 - - - ns V CC = 1.65 V to 1.95 V 1.8 7.7 16.0 1.8 18.5 ns V CC = 2.3 V to 2.7 V 1.5 4.3 8.8 1.5 10.2 ns V CC = 2.7 V 1.5 4.4 7.5 1.5 9.5 ns V CC = 3.0 V to 3.6 V 1.0 3.5 7.0 1.0 9.0 ns t dis disable time OEn toyn; see Figure 6 [2] V CC =1.2V - 11.0 - - - ns V CC = 1.65 V to 1.95 V 3.0 4.9 10.3 3.0 11.9 ns V CC = 2.3 V to 2.7 V 1.0 2.7 5.9 1.0 6.8 ns V CC = 2.7 V 1.5 3.7 7.0 1.5 9.0 ns V CC = 3.0 V to 3.6 V 1.0 3.3 6.0 1.0 7.5 ns Product data sheet Rev. 2 4 March 2013 6 of 16

Table 7. Dynamic characteristics continued Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 7. Symbol Parameter Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ [1] Max Min Max C PD power per input; V I =GNDtoV [4] CC dissipation V CC = 1.65 V to 1.95 V - 7.7 - - - pf capacitance V CC = 2.3 V to 2.7 V - 11.3 - - - pf V CC = 3.0 V to 3.6 V - 14.4 - - - pf [1] Typical values are measured at T amb =25C and V CC = 1.2 V, 1.8 V, 2.5 V, 2.7 V, and 3.3 V respectively. [2] t pd is the same as t PLH and t PHL. t en is the same as t PZL and t PZH. t dis is the same as t PLZ and t PHZ. [3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. [4] C PD is used to determine the dynamic power dissipation (P D in W). P D =C PD V CC 2 f i N+(C L V CC 2 f o ) where: f i = input frequency in MHz; f o = output frequency in MHz C L = output load capacitance in pf V CC = supply voltage in Volts N = number of inputs switching (C L V 2 CC f o ) = sum of the outputs. 11. C waveforms V I n input GND t PHL t PLH V OH Yn output V OL mna901 Fig 5. = 1.5 V at V CC 2.7 V. =0.5 V CC at V CC <2.7V. V OL and V OH are typical output voltage levels that occur with the output load. Input (n) to output (Yn) propagation delays Product data sheet Rev. 2 4 March 2013 7 of 16

V I OEn input GND t PLZ t PZL output LOW-to-OFF OFF-to-LOW V CC V OL V X t PHZ t PZH V OH output HIGH-to-OFF OFF-to-HIGH GND outputs enabled V Y outputs disabled outputs enabled mna902 Fig 6. = 1.5 V at V CC 2.7 V. =0.5 V CC at V CC <2.7V. V X = V OL + 0.3 V at V CC 2.7 V. V X = V OL + 0.15 V at V CC <2.7V. V Y = V OH 0.3 V at V CC 2.7 V. V Y = V OH 0.15 V at V CC < 2.7 V. V OL and V OH are typical output voltage levels that occur with the output load. 3-state enable and disable times Product data sheet Rev. 2 4 March 2013 8 of 16

V I negative pulse 0 V 90 % 10 % t W t f t r t r t f V I positive pulse 0 V 10 % 90 % t W V EXT V CC G V I DUT V O RL RT CL RL 001aae331 Fig 7. Test data is given in Table 8. Definitions for test circuit: R L = Load resistance. C L = Load capacitance including jig and probe capacitance. R T = Termination resistance should be equal to output impedance Z o of the pulse generator. V EXT = External voltage for measuring switching times. Test circuit for measuring switching times Table 8. Test data Supply voltage Input Load V EXT V I t r, t f C L R L t PLH, t PHL t PLZ, t PZL t PHZ, t PZH 1.2 V V CC 2ns 30pF 1 k open 2 V CC GND 1.65 V to 1.95 V V CC 2ns 30pF 1 k open 2 V CC GND 2.3 V to 2.7 V V CC 2ns 30pF 500 open 2 V CC GND 2.7V 2.7V 2.5 ns 50 pf 500 open 2 V CC GND 3.0Vto3.6V 2.7V 2.5 ns 50 pf 500 open 2 V CC GND Product data sheet Rev. 2 4 March 2013 9 of 16

12. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E X c y H E v M Z 20 11 Q 2 1 ( ) 3 pin 1 index L p L θ 1 e b p 10 w M detail X 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches max. 2.65 0.1 1 2 3 b p c D (1) E (1) e H (1) E L L p Q v w y Z 0.3 0.1 0.012 0.004 2.45 2.25 0.096 0.089 0.25 0.01 0.49 0.36 0.019 0.014 0.32 0.23 0.013 0.009 13.0 12.6 0.51 0.49 7.6 7.4 0.30 0.29 1.27 10.65 10.00 0.419 0.394 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 0.05 1.4 0.055 1.1 0.4 0.043 0.016 1.1 1.0 0.043 0.039 0.25 0.25 0.1 0.01 0.01 0.004 θ 0.9 0.4 o 8 o 0.035 0 0.016 OUTLINE VERSION REFERENCES IEC JEDEC JEIT EUROPEN PROJECTION ISSUE DTE SOT163-1 075E04 MS-013 99-12-27 03-02-19 Fig 8. Package outline SOT163-1 (SO20) Product data sheet Rev. 2 4 March 2013 10 of 16

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 D E X c y H E v M Z 20 11 Q pin 1 index 2 1 ( ) 3 θ 1 10 w M e b p detail X L p L 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT 1 2 3 b p c D (1) E (2) e H (1) E L L p Q v w y Z max. mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 θ o 8 o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT360-1 MO-153 EUROPEN PROJECTION ISSUE DTE 99-12-27 03-02-19 Fig 9. Package outline SOT360-1 (TSSOP20) Product data sheet Rev. 2 4 March 2013 11 of 16

DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm SOT764-1 D B E 1 c terminal 1 index area detail X terminal 1 index area e 1 e b 2 9 v M w M C C B y 1 C C y L 1 10 E h e 20 11 19 12 D h X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT (1) max. 1 b c D (1) D h E (1) Eh e e1 L v w y y 1 mm 1 0.05 0.00 0.30 0.18 0.2 4.6 4.4 3.15 2.85 2.6 2.4 1.15 0.85 0.5 3.5 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC JEIT SOT764-1 - - - MO-241 - - - EUROPEN PROJECTION ISSUE DTE 02-10-17 03-01-27 Fig 10. Package outline SOT764-1 (DHVQFN20) Product data sheet Rev. 2 4 March 2013 12 of 16

13. bbreviations Table 9. cronym CDM DUT ESD MM HBM TTL MIL bbreviations Description Charged Device Model Device Under Test ElectroStatic Discharge Machine Model Human Body Model Transistor-Transistor Logic Military 14. Revision history Table 10. Revision history Document ID Release date Data sheet status Change notice Supersedes v.2 20130304 Product data sheet - v.1 Modifications: Changed interlacing into interfacing (errata) in features list. v.1 20130219 Product data sheet - - Product data sheet Rev. 2 4 March 2013 13 of 16

15. Legal information 15.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nexperia.com. 15.2 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. Nexperia does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet short data sheet is an extract from a full data sheet with the same product type number(s) and title. short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local Nexperia sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between Nexperia and its customer, unless Nexperia and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the Nexperia product is deemed to offer functions and qualities beyond those described in the Product data sheet. 15.3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, Nexperia does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Nexperia takes no responsibility for the content in this document if provided by an information source outside of Nexperia. In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use in automotive applications This Nexperia product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of a Nexperia product can reasonably be expected to result in personal injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. pplications pplications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer s applications and products planned, as well as for the planned application and use of customer s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer s applications or products, or the application or use by customer s third party customer(s). Customer is responsible for doing all necessary testing for the customer s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the bsolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of Nexperia products by customer. Product data sheet Rev. 2 4 March 2013 14 of 16

No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Translations non-english (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: ll referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Product data sheet Rev. 2 4 March 2013 15 of 16

17. Contents 1 General description...................... 1 2 Features and benefits.................... 1 3 Ordering information..................... 2 4 Functional diagram...................... 2 5 Pinning information...................... 3 5.1 Pinning............................... 3 5.2 Pin description......................... 3 6 Functional description................... 4 7 Limiting values.......................... 4 8 Recommended operating conditions........ 5 9 Static characteristics..................... 5 10 Dynamic characteristics.................. 6 11 C waveforms.......................... 7 12 Package outline........................ 10 13 bbreviations.......................... 13 14 Revision history........................ 13 15 Legal information....................... 14 15.1 Data sheet status...................... 14 15.2 Definitions............................ 14 15.3 Disclaimers........................... 14 15.4 Trademarks........................... 15 16 Contact information..................... 15 17 Contents.............................. 16 For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 04 March 2013