EGR224 F 18 Assignment #4 ------------------------------------------------------------------------------------------------------------- Due Date: Friday (Section 10), October 19, by 5 pm (slide it under my office door) Friday (Section 20), October 19, by 5 pm (slide it under my office door) Assigned Readings: Lecture notes pages 52 68 1. [5 pts] Consider the following circuit. Complete the timing diagram below. The initial values of Q1 and Q0 are both 1. NOTE: Please re-draw the timing diagram on a separate sheet of paper as part of your homework submission. The timing diagram: Must occupy a whole page in landscape mode Must be drawn either with a software program (AutoCad, Word, anything that can draw straight lines) or very neatly by hand using straight edges Must be clearly legible and easy to understand 2. [5 pts] Complete the timing diagram on the right based on the schematic shown on the left. Same rules apply as Problem #1 above. The initial values of Q1 and Q0 are both 0. 1
3. [15 pts] Design a counter which counts in the following sequence: 000, 001, 011, 111, 110, 100, 000, Use positive edge triggered D-type flip-flops a. [2 pts] Derive the truth table consisting of current states of the counter (QNQN-1 Q0) as the inputs and next states of the counter (QN * QN-1 * Q0 * ) as outputs. Show the complete truth table. b. [3 pts] Derive the equations for each output. Minimize them (using any approach) as much as you can. Show your work! c. [5 pts] Draw the final schematic using the D-type flip-flops and provide proper connections between inputs and outputs. d. [5 pts] Draw the timing diagram for the schematic obtained in Part c above. The timing diagram should cover all the possible state transition mentioned in the problem statement. Please draw timing diagram on a separate sheet of paper as part of your homework submission. Assume all QN s to be 0 to begin with. NOTE: Include following signals in your timing diagram i.e., CLK, all the Q s and all the D s. 4. [5 pts] Given the following State Transition Diagram (STD), complete the timing chart below: 2
5. [5 pts] Consider the following state transition table: INPUT CURRENT STATE NEXT STATE OUTPUTS Is X a Mealy or Moore output? Is Y a Mealy or Moore output? Justify your answer Justify your answer 6. [5 pts] Given the Timing Diagram below, for a state machine that has one input (EN) and two state variables Q1 and Q0, derive a state transition diagram (STD): 3
7. [35 points] Design an FSM for the vending machine. A sequential network is used to control the operation of a vending machine which dispenses a $0.15 product. The network has two inputs, Nickel (N), and Dime (D), and has two outputs, Change Returned (C), and Product Delivered (P). The coin detector mechanism in the vending machine is synchronized with the same clock as the sequential network you are to design. The coin detector outputs a single 1 to the N, or D input for every nickel or dime, respectively that the customer inserts. Only one input will be 1 at a time. When the customer has inserted at least $0.15 in any combination of nickels and dimes, the vending machine must give change and dispense the product. The coin return mechanism gives change by returning nickels to the customer. For every 1 output on C, the coin return mechanism will return one nickel to the customer. The product is dispensed when the network outputs a single 1 on output R. The network should reset after dispensing the product. EXAMPLE: look like this: The customer inserts two nickels and a dime. The network inputs and outputs could INPUTS: N = 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 D = 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 OUTPUTS: R = 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 C = 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 Note that any number of zeros can occur between two 1 inputs. Your deliverables are: [1 pt] A description of your design, explaining your design choices, challenges, etc. [4 pts] A clearly drawn, neat, legible state transition diagram (using Word, Dia, Visio, or similar). Figure 1 on page 56 of your lecture notes is a standard that you can use to measure your own drawing s quality. [1 pt] The state assignment (Using minimum number of bits) [3 pts] The next-state transition table [3 pts] The logic equations derived from your table (minimize them) [1 pt] Now, do the state assignment (One hot encoding) 4
[3 pts] The next-state transition table [3 pts] The logic equations derived from your table (minimize them) [1 pt] Which one of the encoding scheme provides simpler expression? Choose that one to implement. [1 pt] Output logic table (using the above chosen encoding scheme) [2 pts] Output logic equation [5 pts] A final, complete schematic for the whole FSM, professionally drawn (using Xilinx ISE). [7 pts] Simulations of your FSM s behavior in Xilinx. Make sure you annotate your simulations or somehow otherwise indicate to your instructor what each simulation means. Do not expect your instructor to look at a bunch of signals going high and low and be able to figure out what it means! 5